summaryrefslogtreecommitdiff
path: root/drivers/pci/controller
AgeCommit message (Collapse)AuthorFilesLines
2023-08-31Merge tag 'pci-v6.6-changes' of ↵Linus Torvalds45-248/+655
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Add locking to read/modify/write PCIe Capability Register accessors for Link Control and Root Control - Use pci_dev_id() when possible instead of manually composing ID from dev->bus->number and dev->devfn Resource management: - Move prototypes for __weak sysfs resource files to linux/pci.h to fix 'no previous prototype' warnings - Make more I/O port accesses depend on HAS_IOPORT - Use devm_platform_get_and_ioremap_resource() instead of open-coding platform_get_resource() followed by devm_ioremap_resource() Power management: - Ensure devices are powered up while accessing VPD - If device is powered-up, keep it that way while polling for PME - Only read PCI_PM_CTRL register when available, to avoid reading the wrong register and corrupting dev->current_state Virtualization: - Avoid Secondary Bus Reset on NVIDIA T4 GPUs Error handling: - Remove unused pci_disable_pcie_error_reporting() - Unexport pci_enable_pcie_error_reporting(), used only by aer.c - Unexport pcie_port_bus_type, used only by PCI core VGA: - Simplify and clean up typos in VGA arbiter Apple PCIe controller driver: - Initialize pcie->nvecs (number of available MSIs) before use Broadcom iProc PCIe controller driver: - Use of_property_read_bool() instead of low-level accessors for boolean properties Broadcom STB PCIe controller driver: - Assert PERST# when probing BCM2711 because some bootloaders don't do it Freescale i.MX6 PCIe controller driver: - Add .host_deinit() callback so we can clean up things like regulators on probe failure or driver unload Freescale Layerscape PCIe controller driver: - Add support for link-down notification so the endpoint driver can process LINK_DOWN events - Add suspend/resume support, including manual PME_Turn_off/PME_TO_Ack handshake - Save Link Capabilities during probe so they can be restored when handling a link-up event, since the controller loses the Link Width and Link Speed values during reset Intel VMD host bridge driver: - Fix disable of bridge windows during domain reset; previously we cleared the base/limit registers, which actually left the windows enabled Marvell MVEBU PCIe controller driver: - Remove unused busn member Microchip PolarFlare PCIe controller driver: - Fix interrupt bit definitions so the SEC and DED interrupt handlers work correctly - Make driver buildable as a module - Read FPGA MSI configuration parameters from hardware instead of hard-coding them Microsoft Hyper-V host bridge driver: - To avoid a NULL pointer dereference, skip MSI restore after hibernate if MSI/MSI-X hasn't been enabled NVIDIA Tegra194 PCIe controller driver: - Revert 'PCI: tegra194: Enable support for 256 Byte payload' because Linux doesn't know how to reduce MPS from to 256 to 128 bytes for endpoints below a switch (because other devices below the switch might already be operating), which leads to 'Malformed TLP' errors Qualcomm PCIe controller driver: - Add DT and driver support for interconnect bandwidth voting for 'pcie-mem' and 'cpu-pcie' interconnects - Fix broken SDX65 'compatible' DT property - Configure controller so MHI bus master clock will be switched off while in ASPM L1.x states - Use alignment restriction from EPF core in EPF MHI driver - Add Endpoint eDMA support - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driversupport - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driversupport - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driversupport - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driver - Use iATU for EPF MHI transfers smaller than 4K to avoid eDMA setup latency - Add sa8775p DT binding and driver support Rockchip PCIe controller driver: - Use 64-bit mask on MSI 64-bit PCI address to avoid zeroing out the upper 32 bits SiFive FU740 PCIe controller driver: - Set the supported number of MSI vectors so we can use all available MSI interrupts Synopsys DesignWare PCIe controller driver: - Add generic dwc suspend/resume APIs (dw_pcie_suspend_noirq() and dw_pcie_resume_noirq()) to be called by controller driver suspend/resume ops, and a controller callback to send PME_Turn_Off MicroSemi Switchtec management driver: - Add support for PCIe Gen5 devices Miscellaneous: - Reorder and compress to reduce size of struct pci_dev - Fix race in DOE destroy_work_on_stack() - Add stubs to avoid casts between incompatible function types - Explicitly include correct DT includes to untangle headers" * tag 'pci-v6.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (96 commits) PCI: qcom-ep: Add ICC bandwidth voting support dt-bindings: PCI: qcom: ep: Add interconnects path PCI: qcom-ep: Treat unknown IRQ events as an error dt-bindings: PCI: qcom: Fix SDX65 compatible PCI: endpoint: Add kernel-doc for pci_epc_mem_init() API PCI: epf-mhi: Use iATU for small transfers PCI: epf-mhi: Add support for SM8450 PCI: epf-mhi: Add eDMA support PCI: qcom-ep: Add eDMA support PCI: epf-mhi: Make use of the alignment restriction from EPF core PCI/PM: Only read PCI_PM_CTRL register when available PCI: qcom: Add support for sa8775p SoC dt-bindings: PCI: qcom: Add sa8775p compatible PCI: qcom-ep: Pass alignment restriction to the EPF core PCI: Simplify pcie_capability_clear_and_set_word() control flow PCI: Tidy config space save/restore messages PCI: Fix code formatting inconsistencies PCI: Fix typos in docs and comments PCI: Fix pci_bus_resetable(), pci_slot_resetable() name typos PCI: Simplify pci_dev_driver() ...
2023-08-29Merge branch 'pci/misc'Bjorn Helgaas29-38/+28
- Reorder struct pci_dev to avoid holes and reduce size (Christophe JAILLET) - Change pdev->rom_attr_enabled to single bit since it's only a boolean value (Christophe JAILLET) - Use struct_size() in pirq_convert_irt_table() instead of hand-writing it (Christophe JAILLET) - Explicitly include correct DT includes to untangle headers (Rob Herring) - Fix a DOE race between destroy_work_on_stack() and the stack-allocated task->work struct going out of scope in pci_doe() (Ira Weiny) - Use pci_dev_id() when possible instead of manually composing ID from dev->bus->number and dev->devfn (Xiongfeng Wang, Zheng Zengkai) - Move pci_create_resource_files() declarations to linux/pci.h for alpha build warnings (Arnd Bergmann) - Remove unused hotplug function declarations (Yue Haibing) - Remove unused mvebu struct mvebu_pcie.busn (Pali Rohár) - Unexport pcie_port_bus_type (Bjorn Helgaas) - Remove unnecessary sysfs ID local variable initialization (Bjorn Helgaas) - Fix BAR value printk formatting to accommodate 32-bit values (Bjorn Helgaas) - Use consistent pointer types for config access syscall get_user() and put_user() uses (Bjorn Helgaas) - Simplify AER_RECOVER_RING_SIZE definition (Bjorn Helgaas) - Simplify pci_pio_to_address() (Bjorn Helgaas) - Simplify pci_dev_driver() (Bjorn Helgaas) - Fix pci_bus_resetable(), pci_slot_resetable() name typos (Bjorn Helgaas) - Fix code and doc typos and code formatting (Bjorn Helgaas) - Tidy config space save/restore messages (Bjorn Helgaas) * pci/misc: PCI: Tidy config space save/restore messages PCI: Fix code formatting inconsistencies PCI: Fix typos in docs and comments PCI: Fix pci_bus_resetable(), pci_slot_resetable() name typos PCI: Simplify pci_dev_driver() PCI: Simplify pci_pio_to_address() PCI/AER: Simplify AER_RECOVER_RING_SIZE definition PCI: Use consistent put_user() pointer types PCI: Fix printk field formatting PCI: Remove unnecessary initializations PCI: Unexport pcie_port_bus_type PCI: mvebu: Remove unused busn member PCI: Remove unused function declarations PCI/sysfs: Move declarations to linux/pci.h PCI/P2PDMA: Use pci_dev_id() to simplify the code PCI/IOV: Use pci_dev_id() to simplify the code PCI/AER: Use pci_dev_id() to simplify the code PCI: apple: Use pci_dev_id() to simplify the code PCI/DOE: Fix destroy_work_on_stack() race PCI: Explicitly include correct DT includes x86/PCI: Use struct_size() in pirq_convert_irt_table() PCI: Change pdev->rom_attr_enabled to single bit PCI: Reorder pci_dev fields to reduce holes
2023-08-29Merge branch 'pci/controller/resources'Bjorn Helgaas4-8/+4
- Use Use devm_platform_get_and_ioremap_resource() instead of open-coding platform_get_resource() followed by devm_ioremap_resource() (Yang Li) * pci/controller/resources: PCI: imx6: Use devm_platform_get_and_ioremap_resource() PCI: xgene-msi: Use devm_platform_get_and_ioremap_resource() PCI: v3: Use devm_platform_get_and_ioremap_resource() PCI: rcar-gen2: Use devm_platform_get_and_ioremap_resource()
2023-08-29Merge branch 'pci/controller/remove-void-cast'Bjorn Helgaas3-8/+24
- Add stubs for devm action functions that call clk_disable_unprepare() to avoid casts between incompatible function types (Krzysztof Wilczyński) * pci/controller/remove-void-cast: PCI: microchip: Remove cast between incompatible function type PCI: keembay: Remove cast between incompatible function type PCI: meson: Remove cast between incompatible function type
2023-08-29Merge branch 'pci/controller/vmd'Bjorn Helgaas1-2/+17
- Fix disable of bridge windows during domain reset; previously we cleared the base/limit registers, which left the windows enabled (Nirmal Patel) * pci/controller/vmd: PCI: vmd: Disable bridge window for domain reset
2023-08-29Merge branch 'pci/controller/tegra194'Bjorn Helgaas1-10/+0
- Revert "PCI: tegra194: Enable support for 256 Byte payload" because Linux doesn't know how to reduce MPS from to 256 to 128 bytes for Endpoints below a Switch (because other devices below the Switch might already be operating), which leads to Malformed TLP errors (Vidya Sagar) * pci/controller/tegra194: Revert "PCI: tegra194: Enable support for 256 Byte payload"
2023-08-29Merge branch 'pci/controller/rockchip'Bjorn Helgaas1-3/+3
- Use 64-bit mask on MSI 64-bit PCI address to avoid zeroing out the upper 32 bits (Rick Wertenbroek) * pci/controller/rockchip: PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI address
2023-08-29Merge branch 'pci/controller/qcom-ep'Bjorn Helgaas1-1/+73
- Log unknown Qcom Endpoint IRQ events at error level, not debug level (Manivannan Sadhasivam) - Add DT and driver support for qcom interconnect bandwidth voting for "pcie-mem" and "cpu-pcie" interconnects (Krishna chaitanya chundru) * pci/controller/qcom-ep: PCI: qcom-ep: Add ICC bandwidth voting support dt-bindings: PCI: qcom: ep: Add interconnects path PCI: qcom-ep: Treat unknown IRQ events as an error
2023-08-29Merge branch 'pci/controller/qcom-edma'Bjorn Helgaas1-1/+4
- Pass the Qcom Endpoint 4K alignment requirement for outbound windows to the EPF core so EPF drivers can use it (Manivannan Sadhasivam) - Use alignment restriction from EPF core in Qcom EPF MHI driver (Manivannan Sadhasivam) - Add Qcom Endpoint eDMA support by enabling the eDMA IRQ (Manivannan Sadhasivam) - Add Qcom MHI eDMA support (Manivannan Sadhasivam) - Add Qcom Snapdragon SM8450 support to the EPF MHI driver (Manivannan Sadhasivam) - Use iATU for EPF MHI transfers smaller than 4K to avoid eDMA setup latency (Manivannan Sadhasivam) - Add pci_epc_mem_init() kernel-doc (Manivannan Sadhasivam) * pci/controller/qcom-edma: PCI: endpoint: Add kernel-doc for pci_epc_mem_init() API PCI: epf-mhi: Use iATU for small transfers PCI: epf-mhi: Add support for SM8450 PCI: epf-mhi: Add eDMA support PCI: qcom-ep: Add eDMA support PCI: epf-mhi: Make use of the alignment restriction from EPF core PCI: qcom-ep: Pass alignment restriction to the EPF core
2023-08-29Merge branch 'pci/controller/qcom'Bjorn Helgaas2-1/+2
- Configure controller so MHI bus master clock will be switched off while in ASPM L1.x states (Manivannan Sadhasivam) - Add sa8775p DT binding and driver support (Mrinmay Sarkar) - Fix broken DT SDX65 "compatible" property (Krzysztof Kozlowski) * pci/controller/qcom: dt-bindings: PCI: qcom: Fix SDX65 compatible PCI: qcom: Add support for sa8775p SoC dt-bindings: PCI: qcom: Add sa8775p compatible PCI: qcom-ep: Switch MHI bus master clock off during L1SS
2023-08-29Merge branch 'pci/controller/microchip'Bjorn Helgaas2-162/+233
- Fix DED and SEC interrupt bit offsets so interrupt handlers work correctly (Daire McNamara) - Make driver buildable as a module (Daire McNamara) - Reorganize register #defines to align with hardware docs (Daire McNamara) - Tweak register accessors to simplify callers (Daire McNamara) - Refactor interrupt initialisation (Daire McNamara) - Read FPGA MSI configuration parameters from hardware instead of hard-coding them (Daire McNamara) - Re-partition code between probe() and init() (Daire McNamara) * pci/controller/microchip: PCI: microchip: Re-partition code between probe() and init() PCI: microchip: Gather MSI information from hardware config registers PCI: microchip: Clean up initialisation of interrupts PCI: microchip: Enable event handlers to access bridge and control pointers PCI: microchip: Align register, offset, and mask names with HW docs PCI: microchip: Enable building driver as a module PCI: microchip: Correct the DED and SEC interrupt bit offsets
2023-08-29Merge branch 'pci/controller/layerscape'Bjorn Helgaas1-0/+20
- Add support for link-down notification so the endpoint driver can process LINK_DOWN events (Frank Li) - Save Link Capabilities during probe so they can be restored when handling a link-up event, since the controller loses the Link Width and Link Speed values during reset (Xiaowei Bao) * pci/controller/layerscape: PCI: layerscape: Add workaround for lost link capabilities during reset PCI: layerscape: Add support for link-down notification
2023-08-29Merge branch 'pci/controller/iproc'Bjorn Helgaas1-3/+2
- Use of_property_read_bool() instead of low-level accessors for boolean properties (Rob Herring) * pci/controller/iproc: PCI: iproc: Use of_property_read_bool() for boolean properties
2023-08-29Merge branch 'pci/controller/hv'Bjorn Helgaas1-0/+3
- To avoid a NULL pointer dereference, skip MSI restore after hibernate if MSI/MSI-X hasn't been enabled (Dexuan Cui) * pci/controller/hv: PCI: hv: Fix a crash in hv_pci_restore_msi_msg() during hibernation
2023-08-29Merge branch 'pci/controller/fu740'Bjorn Helgaas1-0/+1
- Set the supported number of MSI vectors so we can use all available MSI interrupts (Yong-Xuan Wang) * pci/controller/fu740: PCI: fu740: Set the number of MSI vectors
2023-08-29Merge branch 'pci/controller/dwc'Bjorn Helgaas4-9/+231
- Add an imx6 .host_deinit() callback so we can clean up things like regulators on probe failure or driver unload (Mark Brown) - Add PCIE_PME_TO_L2_TIMEOUT_US value for controller drivers that need to manually synchronize power removal (Frank Li) - Add generic dwc suspend/resume APIs (dw_pcie_suspend_noirq() and dw_pcie_resume_noirq()) to be called by controller driver suspend/resume ops, and a controller callback to send PME_Turn_Off (Frank Li) - Add layerscape suspend/resume support, including manual PME_Turn_off/PME_TO_Ack handshake (Hou Zhiqiang, Frank Li) * pci/controller/dwc: PCI: layerscape: Add power management support for ls1028a PCI: dwc: Implement generic suspend/resume functionality PCI: Add PCIE_PME_TO_L2_TIMEOUT_US L2 ready timeout value PCI: dwc: Provide deinit callback for i.MX
2023-08-29Merge branch 'pci/controller/brcmstb'Bjorn Helgaas1-1/+5
- Assert PERST# when probing BCM2711 because some bootloaders don't do it (Jim Quinlan) * pci/controller/brcmstb: PCI: brcmstb: Remove stale comment PCI: brcmstb: Assert PERST# on BCM2711
2023-08-29PCI: qcom-ep: Add ICC bandwidth voting supportKrishna chaitanya chundru1-0/+72
Add support for voting interconnect (ICC) bandwidth based on the link speed and width. This commit is inspired from the basic interconnect support added to pcie-qcom driver in commit c4860af88d0c ("PCI: qcom: Add basic interconnect support"). The interconnect support is kept optional to be backward compatible with legacy device trees. [kwilczynski: add missing kernel-doc for the icc_mem variable] Link: https://lore.kernel.org/linux-pci/1689751218-24492-5-git-send-email-quic_krichai@quicinc.com Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2023-08-29PCI: qcom-ep: Treat unknown IRQ events as an errorManivannan Sadhasivam1-1/+1
Sometimes, the Qcom PCIe EP controller can receive some interrupts unknown to the driver, like safety interrupts in newer SoCs. In those cases, if the driver doesn't clear the interrupts, it will end up in an interrupt storm. However, the users will not know about it because the log is treated as a debug message. So let's treat the unknown event log as an error so that it at least makes the user aware, thereby getting fixed eventually. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20230726152931.18134-1-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2023-08-26PCI: qcom-ep: Add eDMA supportManivannan Sadhasivam1-1/+3
Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA) peripheral for offloading the data transfer between the PCIe bus and memory. Let's add support for it by enabling the eDMA IRQ in the driver. The eDMA DMA Engine driver will handle the rest of the functionality. Since the eDMA on Qualcomm platforms only uses a single IRQ for all channels, use 1 for edma.nr_irqs. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20230717065459.14138-4-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2023-08-25PCI: qcom: Add support for sa8775p SoCMrinmay Sarkar1-0/+1
Add support for sa8775p SoC that uses controller version 5.90 reusing the 1.9.0 config. Link: https://lore.kernel.org/linux-pci/1689960276-29266-3-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
2023-08-25PCI: qcom-ep: Pass alignment restriction to the EPF coreManivannan Sadhasivam1-0/+1
Qcom PCIe EP controllers have 4K alignment restriction for the outbound window address. Hence, pass this info to the EPF core so that the EPF drivers can make use of this info. Link: https://lore.kernel.org/linux-pci/20230717065459.14138-2-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2023-08-25PCI: Fix typos in docs and commentsBjorn Helgaas1-1/+1
Fix typos in docs and comments. Link: https://lore.kernel.org/r/20230824193712.542167-11-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
2023-08-25PCI: mvebu: Remove unused busn memberPali Rohár1-1/+0
The busn member of struct mvebu_pcie is unused, so drop it. Link: https://lore.kernel.org/r/20220905192310.22786-5-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2023-08-24PCI: brcmstb: Remove stale commentJim Quinlan1-1/+0
A comment says that Multi-MSI is not supported by the driver. A past commit [1] added this feature, so the comment is incorrect and is removed. [1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI") Link: https://lore.kernel.org/r/20230623144100.34196-6-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2023-08-24PCI: brcmstb: Assert PERST# on BCM2711Jim Quinlan1-0/+5
The current PCIe driver assumes PERST# is asserted when probe() is invoked. Some older versions of the 2711/RPi bootloader left PERST# unasserted, as the Raspian OS does assert PERST# on probe(). For this reason, we assert PERST# for BCM2711 SOCs (i.e. RPi). Link: https://lore.kernel.org/r/20230623144100.34196-5-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2023-08-24PCI: layerscape: Add power management support for ls1028aHou Zhiqiang1-9/+131
Add PME_Turn_off/PME_TO_Ack handshake sequence for ls1028a platform. Implemented on top of common dwc dw_pcie_suspend(resume)_noirq() functions to handle system enter/exit suspend states. Link: https://lore.kernel.org/r/20230821184815.2167131-4-Frank.Li@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
2023-08-24PCI: dwc: Implement generic suspend/resume functionalityFrank Li2-0/+99
Introduce an helper function (dw_pcie_get_ltssm()) to retrieve SMLH_LTSS_STATE. Add common dw_pcie_suspend(resume)_noirq() API to implement the DWC controller generic suspend/resume functionality. Add a controller specific callback to send the PME_Turn_Off message (ie .pme_turn_off) for controller platform specific PME handling. Link: https://lore.kernel.org/r/20230821184815.2167131-3-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> [lpieralisi@kernel.org: commit log] Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
2023-08-24PCI: layerscape: Add workaround for lost link capabilities during resetXiaowei Bao1-0/+19
The endpoint controller loses the Maximum Link Width and Supported Link Speed value from the Link Capabilities Register - initially configured by the Reset Configuration Word (RCW) - during a link-down or hot reset event. Address this issue in the endpoint event handler. Link: https://lore.kernel.org/r/20230720135834.1977616-2-Frank.Li@nxp.com Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
2023-08-24PCI: layerscape: Add support for link-down notificationFrank Li1-0/+1
Add support to pass link-down notification to the endpoint function driver so that it can process the LINK_DOWN event. Link: https://lore.kernel.org/r/20230720135834.1977616-1-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
2023-08-23PCI: fu740: Set the number of MSI vectorsYong-Xuan Wang1-0/+1
The iMSI-RX module of the DW PCIe controller provides multiple sets of MSI_CTRL_INT_i_* registers, and each set is capable of handling 32 MSI interrupts. However, the fu740 PCIe controller driver only enabled one set of MSI_CTRL_INT_i_* registers, as the total number of supported interrupts was not specified. Set the supported number of MSI vectors to enable all the MSI_CTRL_INT_i_* registers on the fu740 PCIe core, allowing the system to fully utilize the available MSI interrupts. Link: https://lore.kernel.org/r/20230807055621.2431-1-yongxuan.wang@sifive.com Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
2023-08-22PCI: hv: Fix a crash in hv_pci_restore_msi_msg() during hibernationDexuan Cui1-0/+3
When a Linux VM with an assigned PCI device runs on Hyper-V, if the PCI device driver is not loaded yet (i.e. MSI-X/MSI is not enabled on the device yet), doing a VM hibernation triggers a panic in hv_pci_restore_msi_msg() -> msi_lock_descs(&pdev->dev), because pdev->dev.msi.data is still NULL. Avoid the panic by checking if MSI-X/MSI is enabled. Link: https://lore.kernel.org/r/20230816175939.21566-1-decui@microsoft.com Fixes: dc2b453290c4 ("PCI: hv: Rework MSI handling") Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: sathyanarayanan.kuppuswamy@linux.intel.com Reviewed-by: Michael Kelley <mikelley@microsoft.com> Cc: stable@vger.kernel.org
2023-08-22PCI: vmd: Disable bridge window for domain resetNirmal Patel1-2/+17
During domain reset process vmd_domain_reset() clears PCI configuration space of VMD root ports. But certain platform has observed following errors and failed to boot. ... DMAR: VT-d detected Invalidation Queue Error: Reason f DMAR: VT-d detected Invalidation Time-out Error: SID ffff DMAR: VT-d detected Invalidation Completion Error: SID ffff DMAR: QI HEAD: UNKNOWN qw0 = 0x0, qw1 = 0x0 DMAR: QI PRIOR: UNKNOWN qw0 = 0x0, qw1 = 0x0 DMAR: Invalidation Time-out Error (ITE) cleared The root cause is that memset_io() clears prefetchable memory base/limit registers and prefetchable base/limit 32 bits registers sequentially. This seems to be enabling prefetchable memory if the device disabled prefetchable memory originally. Here is an example (before memset_io()): PCI configuration space for 10000:00:00.0: 86 80 30 20 06 00 10 00 04 00 04 06 00 00 01 00 00 00 00 00 00 00 00 00 00 01 01 00 00 00 00 20 00 00 00 00 01 00 01 00 ff ff ff ff 75 05 00 00 ... So, prefetchable memory is ffffffff00000000-575000fffff, which is disabled. When memset_io() clears prefetchable base 32 bits register, the prefetchable memory becomes 0000000000000000-575000fffff, which is enabled and incorrect. Here is the quote from section 7.5.1.3.9 of PCI Express Base 6.0 spec: The Prefetchable Memory Limit register must be programmed to a smaller value than the Prefetchable Memory Base register if there is no prefetchable memory on the secondary side of the bridge. This is believed to be the reason for the failure and in addition the sequence of operation in vmd_domain_reset() is not following the PCIe specs. Disable the bridge window by executing a sequence of operations borrowed from pci_disable_bridge_window() and pci_setup_bridge_io(), that comply with the PCI specifications. Link: https://lore.kernel.org/r/20230810215029.1177379-1-nirmal.patel@linux.intel.com Signed-off-by: Nirmal Patel <nirmal.patel@linux.intel.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
2023-08-08PCI: dwc: Provide deinit callback for i.MXMark Brown1-0/+1
The i.MX integration for the DesignWare PCI controller has a _host_exit() operation which undoes everything that the _host_init() operation does but does not wire this up as the host_deinit callback for the core, or call it in any path other than suspend. This means that if we ever unwind the initial probe of the device, for example because it fails, the regulator core complains that the regulators for the device were left enabled: imx6q-pcie 33800000.pcie: iATU: unroll T, 4 ob, 4 ib, align 64K, limit 16G imx6q-pcie 33800000.pcie: Phy link never came up imx6q-pcie 33800000.pcie: Phy link never came up imx6q-pcie: probe of 33800000.pcie failed with error -110 ------------[ cut here ]------------ WARNING: CPU: 2 PID: 46 at drivers/regulator/core.c:2396 _regulator_put+0x110/0x128 Wire up the callback so that the core can clean up after itself. Link: https://lore.kernel.org/r/20230731-pci-imx-regulator-cleanup-v2-1-fc8fa5c9893d@kernel.org Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2023-08-08PCI: microchip: Re-partition code between probe() and init()Daire McNamara1-20/+38
Continuing to use pci_host_common_probe() for the PCIe Root Complex on PolarFire SoC is leading to an extremely large _init() function and some unnatural code flow. Re-partition the code so that some tasks are done in a _probe() routine, which calls pci_host_common_probe() and then use a much smaller _init() function, mainly to enable interrupts after address translation tables are set up. Link: https://lore.kernel.org/r/20230728131401.1615724-8-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-08PCI: microchip: Gather MSI information from hardware config registersDaire McNamara1-28/+37
The PCIe Root Complex on PolarFire SoC is configured at bitstream creation time using Libero. Key MSI-related parameters include the number of MSIs (1/2/4/8/16/32) and the MSI address. In the device driver, extract this information from hardware registers at init time, and use it to configure MSI system, including configuring MSI capability structure correctly in configuration space. Link: https://lore.kernel.org/r/20230728131401.1615724-7-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-08PCI: microchip: Clean up initialisation of interruptsDaire McNamara1-56/+100
Refactor interrupt handling in _init() function into disable_interrupts(), init_interrupts(), clear_sec_errors() and clear ded_errors() because current code is unwieldy and prone to bugs. Disable interrupts as soon as possible and only enable interrupts after address translation is setup to prevent spurious axi2pcie and pcie2axi translation errors being reported. Link: https://lore.kernel.org/r/20230728131401.1615724-6-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-08PCI: microchip: Enable event handlers to access bridge and control pointersDaire McNamara1-15/+16
Minor re-organisation so that event handlers can access both a pointer to the bridge area of the PCIe Root Port and the control area of the PCIe Root Port. Link: https://lore.kernel.org/r/20230728131401.1615724-5-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-08PCI: microchip: Align register, offset, and mask names with HW docsDaire McNamara1-62/+60
Minor code re-organisation so that macros representing registers ascend in numerical order and use the same names as their hardware documentation. Removed registers not used by the driver. Link: https://lore.kernel.org/r/20230728131401.1615724-4-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-08PCI: microchip: Enable building driver as a moduleDaire McNamara2-1/+2
Enable building driver as a module. The expected use case is the driver is built as a module, is installed when needed, and cannot be removed once installed since it is not possible to clean-up the irq_chip data structures on removal, as described in: https://lore.kernel.org/linux-pci/87y1wgbah8.wl-maz@kernel.org/ The driver has .suppress_bind_attrs set to true for the same reasons (ie prevent unbinding, that would leave the kernel with stale IRQ configuration that cannot be cleaned up). Link: https://lore.kernel.org/linux-pci/87y1wgbah8.wl-maz@kernel.org/ Link: https://lore.kernel.org/r/20230728131401.1615724-3-daire.mcnamara@microchip.com Suggested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-08PCI: microchip: Correct the DED and SEC interrupt bit offsetsDaire McNamara1-4/+4
The SEC and DED interrupt bits are laid out the wrong way round so the SEC interrupt handler attempts to mask, unmask, and clear the DED interrupt and vice versa. Correct the bit offsets so that each interrupt handler operates properly. Link: https://lore.kernel.org/r/20230728131401.1615724-2-daire.mcnamara@microchip.com Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver") Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-08PCI: apple: Use pci_dev_id() to simplify the codeXiongfeng Wang1-2/+2
When we have a struct pci_dev *, use pci_dev_id() instead of manually composing the ID with PCI_DEVID() from dev->bus->number and dev->devfn. [bhelgaas: commit log] Link: https://lore.kernel.org/r/20230807134858.116051-2-wangxiongfeng2@huawei.com Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-08-05Revert "PCI: mvebu: Mark driver as BROKEN"Bjorn Helgaas1-1/+0
b3574f579ece ("PCI: mvebu: Mark driver as BROKEN") made it impossible to enable the pci-mvebu driver. The driver does have known problems, but as Russell and Uwe reported, it does work in some configurations, so removing it broke some working setups. Revert b3574f579ece so pci-mvebu is available. Reported-by: Russell King (Oracle) <linux@armlinux.org.uk> Link: https://lore.kernel.org/r/ZMzicVQEyHyZzBOc@shell.armlinux.org.uk Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230804134622.pmbymxtzxj2yfhri@pengutronix.de Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-08-03Revert "PCI: tegra194: Enable support for 256 Byte payload"Vidya Sagar1-10/+0
After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload"), we initialize MPS=256 for tegra194 Root Ports before enumerating the hierarchy. Consider an Endpoint that supports only MPS=128. In the default situation (CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*" parameter), Linux tries to configure the MPS of every device to match the upstream bridge. If the Endpoint is directly below the Root Port, Linux can reduce the Root Port MPS to 128 to match the Endpoint. But if there's a switch in the middle, Linux doesn't reduce the Root Port MPS because other devices below the switch may already be configured with MPS larger than 128. This scenario results in uncorrectable Malformed TLP errors if the Root Port sends TLPs with payloads larger than 128 bytes. These errors can be avoided by using the "pci=pcie_bus_safe" parameter, but it doesn't seem to be a good idea to always have this parameter even for basic functionality to work. Revert commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload") so the Root Ports default to MPS=128, which all devices support. If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf" to get the benefit of larger MPS settings. [bhelgaas: commit log; kwilczynski: retain "u16 val_16" declaration at the top, add missing acked by tag] Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload") Link: https://lore.kernel.org/linux-pci/20230619102604.3735001-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Cc: stable@vger.kernel.org # v6.0-rc1+
2023-07-26Revert "PCI: dwc: Wait for link up only if link is started"Johan Hovold3-23/+11
This reverts commit da56a1bfbab55189595e588f1d984bdfb5cf5924. Bjorn Andersson, Fabio Estevam, Xiaolei Wang, and Jon Hunter reported that da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started") broke controller probing by returning an error in case the link does not come up during host initialisation, for example when the slot is empty. As explained in commit 886a9c134755 ("PCI: dwc: Move link handling into common code") and as indicated by the comment "Ignore errors, the link may come up later" in the code, waiting for link up and ignoring errors is the intended behaviour: Let's standardize this to succeed as there are usecases where devices (and the link) appear later even without hotplug. For example, a reconfigured FPGA device. Reverting the offending commit specifically fixes a regression on Qualcomm platforms like the Lenovo ThinkPad X13s which no longer reach the interconnect sync state if a slot does not have a device populated (e.g. an optional modem). Note that enabling asynchronous probing by default as was done for Qualcomm platforms by commit c0e1eb441b1d ("PCI: qcom: Enable async probe by default"), should take care of any related boot time concerns. Finally, note that the intel-gw driver is the only driver currently not providing a .start_link() callback and instead starts the link in its .host_init() callback, which may avoid an additional one-second timeout during probe by making the link-up wait conditional. If anyone cares, that can be done in a follow-up patch with a proper motivation. [bhelgaas: add Fabio Estevam, Xiaolei Wang, Jon Hunter reports] Fixes: da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started") Link: https://lore.kernel.org/r/20230706082610.26584-1-johan+linaro@kernel.org Reported-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reported-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20230704122635.1362156-1-festevam@gmail.com/ Reported-by: Xiaolei Wang <xiaolei.wang@windriver.com> Link: https://lore.kernel.org/r/20230705010624.3912934-1-xiaolei.wang@windriver.com/ Reported-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/6ca287a1-6c7c-7b90-9022-9e73fb82b564@nvidia.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Sajid Dalvi <sdalvi@google.com> Cc: Ajay Agarwal <ajayagarwal@google.com>
2023-07-18PCI: Explicitly include correct DT includesRob Herring26-34/+25
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Link: https://lore.kernel.org/r/20230714174827.4061572-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-07-13PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI addressRick Wertenbroek1-3/+3
A 32-bit mask was used on the 64-bit PCI address used for mapping MSIs. This would result in the upper 32 bits being unintentionally zeroed and MSIs getting mapped to incorrect PCI addresses if the address had any of the upper bits set. Replace 32-bit mask by appropriate 64-bit mask. [kwilczynski: use GENMASK_ULL() over GENMASK() for 32-bit compatibility] Fixes: dc73ed0f1b8b ("PCI: rockchip: Fix window mapping and address translation for endpoint") Closes: https://lore.kernel.org/linux-pci/8d19e5b7-8fa0-44a4-90e2-9bb06f5eb694@moroto.mountain Link: https://lore.kernel.org/linux-pci/20230703085845.2052008-1-rick.wertenbroek@gmail.com Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Cc: stable@vger.kernel.org
2023-07-13PCI: microchip: Remove cast between incompatible function typeKrzysztof Wilczyński1-2/+8
Rather than casting void(*)(struct clk *) to void (*)(void *), that forces conversion to an incompatible function type, replace the cast with a small local stub function with a signature that matches what the devm_add_action_or_reset() function expects. The sub function takes a void *, then passes it directly to clk_disable_unprepare(), which handles the more specific type. Reported by clang when building with warnings enabled: drivers/pci/controller/pcie-microchip-host.c:866:32: warning: cast from 'void (*)(struct clk *)' to 'void (*)(void *)' converts to incompatible function type [-Wcast-function-type-strict] devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ No functional changes are intended. Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver") Link: https://lore.kernel.org/linux-pci/20230629165956.237832-3-kwilczynski@kernel.org Link: https://lore.kernel.org/linux-pci/20230511-pci-microchip-clk-cast-v1-1-7674f4d4e218@kernel.org Link: https://lore.kernel.org/linux-pci/20230111125323.1911373-3-daire.mcnamara@microchip.com Co-developed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Co-developed-by: Simon Horman <horms@kernel.org> Signed-off-by: Simon Horman <horms@kernel.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-13PCI: keembay: Remove cast between incompatible function typeKrzysztof Wilczyński1-3/+8
Rather than casting void(*)(struct clk *) to void (*)(void *), that forces conversion to an incompatible function type, replace the cast with a small local stub function with a signature that matches what the devm_add_action_or_reset() function expects. The sub function takes a void *, then passes it directly to clk_disable_unprepare(), which handles the more specific type. Reported by clang when building with warnings enabled: drivers/pci/controller/dwc/pcie-keembay.c:172:12: warning: cast from 'void (*)(struct clk *)' to 'void (*)(void *)' converts to incompatible function type [-Wcast-function-type-strict] (void(*)(void *))clk_disable_unprepare, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ No functional changes are intended. Fixes: 0c87f90b4c13 ("PCI: keembay: Add support for Intel Keem Bay") Link: https://lore.kernel.org/linux-pci/20230629165956.237832-2-kwilczynski@kernel.org Acked-by: Srikanth Thokala <srikanth.thokala@intel.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2023-07-13PCI: meson: Remove cast between incompatible function typeKrzysztof Wilczyński1-3/+8
Rather than casting void(*)(struct clk *) to void (*)(void *), that forces conversion to an incompatible function type, replace the cast with a small local stub function with a signature that matches what the devm_add_action_or_reset() function expects. The sub function takes a void *, then passes it directly to clk_disable_unprepare(), which handles the more specific type. Reported by clang when building with warnings enabled: drivers/pci/controller/dwc/pci-meson.c:191:6: warning: cast from 'void (*)(struct clk *)' to 'void (*)(void *)' converts to incompatible function type [-Wcast-function-type-strict] (void (*) (void *))clk_disable_unprepare, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ No functional changes are intended. Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver") Link: https://lore.kernel.org/linux-pci/20230629165956.237832-1-kwilczynski@kernel.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-16 10:34:54 +0300