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path: root/drivers/phy/cadence
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2022-07-08phy: cadence-torrent: Remove unused `regmap` field from state structLars-Peter Clausen1-1/+0
2022-07-08phy: cadence: Sierra: Remove unused `regmap` field from state structLars-Peter Clausen1-1/+0
2022-07-05phy: cdns-dphy: Add support for DPHY TX on J721eRahul T R1-0/+61
2022-07-05phy: cdns-dphy: Add band config for dphy txRahul T R1-1/+39
2022-04-13phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configurationSwapnil Jakhade1-3/+190
2022-03-02phy: cadence: Add Cadence D-PHY Rx driverPratyush Yadav3-0/+264
2022-02-25phy/cadence: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)1-6/+1
2022-02-07phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju1-25/+57
2022-01-24phy: cadence: Sierra: fix error handling bugs in probe()Dan Carpenter1-14/+21
2021-12-27phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade1-1/+108
2021-12-27phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade1-1/+376
2021-12-27phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade1-8/+190
2021-12-27phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade1-5/+26
2021-12-27phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade1-1/+213
2021-12-27phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+72
2021-12-27phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-0/+45
2021-12-27phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade1-0/+38
2021-12-27phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ...Swapnil Jakhade1-10/+11
2021-12-27phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade1-1/+5
2021-12-27phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade1-56/+139
2021-12-27phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade1-9/+4
2021-11-23phy: cadence-torrent: use swap() to make code cleanerYang Guang1-4/+2
2021-10-26phy: cadence-torrent: Add support to output received reference clockSwapnil Jakhade1-11/+148
2021-10-26phy: cadence-torrent: Model reference clock driver as a clock to enable deriv...Swapnil Jakhade1-25/+132
2021-10-26phy: cadence-torrent: Migrate to clk_hw based registration and OF APIsSwapnil Jakhade1-11/+19
2021-08-17phy: cadence-torrent: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+59
2021-08-17phy: cadence-torrent: Add debug information for PHY configurationSwapnil Jakhade1-4/+32
2021-08-17phy: cadence-torrent: Add separate functions for reusable codeSwapnil Jakhade1-18/+35
2021-08-17phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clockSwapnil Jakhade1-0/+162
2021-08-17phy: cadence-torrent: Add PHY registers for DP in array formatSwapnil Jakhade1-288/+334
2021-08-17phy: cadence-torrent: Configure PHY registers as a function of input referenc...Swapnil Jakhade1-408/+422
2021-08-17phy: cadence-torrent: Add enum for supported input reference clock frequenciesSwapnil Jakhade1-13/+38
2021-08-17phy: cadence-torrent: Reorder few functions to remove function declarationsSwapnil Jakhade1-619/+588
2021-08-17phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK messageSwapnil Jakhade1-12/+12
2021-05-31phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()Wang Wensheng1-0/+1
2021-03-31phy: cadence-torrent: Add delay for PIPE clock to be stableKishon Vijay Abraham I1-0/+9
2021-03-31phy: cadence-torrent: Explicitly request exclusive reset controlKishon Vijay Abraham I1-1/+1
2021-03-31phy: cadence-torrent: Do not configure SERDES if it's already configuredKishon Vijay Abraham I1-10/+22
2021-03-31phy: cadence-torrent: Group reset APIs and clock APIsKishon Vijay Abraham I1-31/+53
2021-03-31phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I1-3/+37
2021-03-31phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I2-3/+265
2021-03-31phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I1-0/+3
2021-03-31phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I1-10/+15
2021-03-31phy: cadence-torrent: Use a common header file for Cadence SERDESKishon Vijay Abraham I1-1/+1
2021-03-31phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I1-2/+2
2021-03-31phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I1-11/+25
2021-03-31phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I1-22/+35
2021-03-31phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I1-0/+4
2021-03-31phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I1-1/+6
2021-03-30phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clockSwapnil Jakhade1-16/+31