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path: root/drivers/phy/cadence
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2020-11-16phy: cadence: convert to devm_platform_ioremap_resourceChunfeng Yun3-9/+3
2020-09-18phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configurationSwapnil Jakhade1-0/+254
2020-09-18phy: cadence-torrent: Add PCIe + USB multilink configurationSwapnil Jakhade1-0/+216
2020-09-18phy: cadence-torrent: Add single link USB register sequencesSwapnil Jakhade1-1/+259
2020-09-18phy: cadence-torrent: Add single link SGMII/QSGMII register sequencesSwapnil Jakhade1-0/+89
2020-09-18phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_valsSwapnil Jakhade1-4/+18
2020-09-18phy: cadence-torrent: Add PHY link configuration sequences for single linkSwapnil Jakhade1-0/+44
2020-09-18phy: cadence-torrent: Add clk changes for multilink configurationSwapnil Jakhade1-24/+17
2020-09-18phy: cadence-torrent: Update PHY reset for multilink configurationSwapnil Jakhade1-7/+21
2020-09-18phy: cadence-torrent: Add support for PHY multilink configurationSwapnil Jakhade1-26/+757
2020-09-18phy: cadence-torrent: Add PHY APB reset supportSwapnil Jakhade1-0/+13
2020-09-18phy: cadence-torrent: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-1/+30
2020-09-18phy: cadence-torrent: Add single link PCIe supportSwapnil Jakhade1-30/+266
2020-09-18phy: cadence-torrent: Check total lane count for all subnodes is within limitSwapnil Jakhade1-4/+15
2020-09-18phy: cadence-torrent: Add separate regmap functions for torrent and DPSwapnil Jakhade1-33/+66
2020-09-18phy: cadence-torrent: Enable support for multiple subnodesSwapnil Jakhade1-15/+0
2020-09-18phy: cadence-torrent: Use devm_platform_ioremap_resource() to get reg addressesSwapnil Jakhade1-6/+2
2020-09-18phy: cadence-torrent: Use of_device_get_match_data() to get driver dataSwapnil Jakhade1-8/+5
2020-09-16phy: cadence: torrent: Constify regmap_config structsRikard Falkeborn1-6/+6
2020-09-16phy: cadence: salvo: Constify cdns_nxp_sequence_pairRikard Falkeborn1-3/+3
2020-09-16phy: cadence: Sierra: Constify static structsRikard Falkeborn1-12/+12
2020-09-16Merge branch 'topic/phy_attrs' into nextVinod Koul1-0/+4
2020-09-16phy: cadence-torrent: Set Torrent PHY attributesSwapnil Jakhade1-0/+4
2020-08-31phy: cadence: salvo: Constify cdns_salvo_phy_opsRikard Falkeborn1-1/+1
2020-07-13phy: cadence: salvo: fix wrong bit definitionPeter Chen1-1/+1
2020-05-18phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar1-13/+14
2020-05-15phy: phy-cadence-salvo: add phy .init APIPeter Chen1-1/+11
2020-05-07phy: cadence: salvo: add salvo phy driverPeter Chen3-0/+325
2020-03-20phy: cadence-torrent: Add support for subnode bindingsSwapnil Jakhade1-75/+217
2020-03-20phy: cadence-torrent: Add platform dependent initialization structureSwapnil Jakhade1-0/+9
2020-03-20phy: cadence-torrent: Use regmap to read and write DPTX PHY registersSwapnil Jakhade1-69/+100
2020-03-20phy: cadence-torrent: Use regmap to read and write Torrent PHY registersSwapnil Jakhade1-369/+650
2020-03-20phy: cadence-torrent: Implement PHY configure APIsSwapnil Jakhade1-5/+431
2020-03-20phy: cadence-torrent: Add 19.2 MHz reference clock supportSwapnil Jakhade1-17/+441
2020-03-20phy: cadence-torrent: Refactor code for reusabilitySwapnil Jakhade1-93/+137
2020-03-20phy: cadence-torrent: Add wrapper for DPTX register accessSwapnil Jakhade1-21/+50
2020-03-20phy: cadence-torrent: Add wrapper for PHY register accessSwapnil Jakhade1-65/+77
2020-03-20phy: cadence-torrent: Adopt Torrent nomenclatureSwapnil Jakhade1-53/+58
2020-03-20phy: cadence-dp: Rename to phy-cadence-torrentYuti Amonkar3-5/+5
2020-01-14phy: cadence: Sierra: add phy_reset hookRoger Quadros1-0/+10
2020-01-14phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King1-1/+1
2020-01-08phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I1-1/+1
2020-01-08phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to...Kishon Vijay Abraham I1-0/+21
2020-01-08phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I1-1/+21
2020-01-08phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I1-1/+32
2020-01-08phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I1-1/+1
2020-01-08phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ex...Anil Varughese1-96/+254
2020-01-08phy: cadence: Sierra: Modify register macro names to be in sync with Sierra u...Kishon Vijay Abraham I1-83/+84
2020-01-08phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_opsKishon Vijay Abraham I1-6/+9
2020-01-08phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoCKishon Vijay Abraham I1-0/+14