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2021-02-06phy: qcom-qmp: make a const array static, makes object smallerColin Ian King1-1/+1
Don't populate the const array cfg1_settings on the stack but instead make it static. Makes the object code smaller by 24 bytes: Before: text data bss dec hex filename 73585 20240 64 93889 16ec1 drivers/phy/qualcomm/phy-qcom-qmp.o After: text data bss dec hex filename 73465 20336 64 93865 16ea9 drivers/phy/qualcomm/phy-qcom-qmp.o (gcc version 10.2.0) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210204180313.108876-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: Add support for SM8350 UFS phyVinod Koul1-0/+127
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: Add UFS V5 registers found in SM8350Vinod Koul1-0/+47
Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qualcomm: usb28nm: Add MDM9607 init sequenceKonrad Dybcio1-0/+13
This is required to bring up the PHY on MDM9607-based boards. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210131013124.54484-1-konrad.dybcio@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qusb2: add QUSB2 support for IPQ6018Kathiravan T1-0/+44
Add the phy init sequence for the Super Speed ports found on IPQ6018. Signed-off-by: Kathiravan T <kathirav@codeaurora.org> [baruch: add ipq6018_regs_layout[], drop binding change] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/b8c22dddf1f70d89e135fe1ae705ddc68e295ebb.1611756920.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qmp: Add SC8180X USB phyBjorn Andersson1-0/+3
The Qualcomm SC8180X has two QMP phys used for SuperSpeed USB, which are either the same or very similar to the same found in SM8150. Add a compatible for this, reusing the existing SM8150 USB phy config. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210121014339.1612525-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qmp: Add SC8180X UFS phyBjorn Andersson1-0/+3
The UFS phy found in the Qualcomm SC8180X is either the same or very similar to the phy present in SM8150, so add a compatible and reuse the SM8150 configuration. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210120224531.1610709-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Add configuration for SDM660AngeloGioacchino Del Regno1-0/+15
The SDM660 SoC uses the same configuration as MSM8996, but the clock scheme uses a differential reference clock and none of the SoCs in this series (630, 636 and others) have got a usable PHY_CLK_SCHEME register in the TCSR for clk scheme detection. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-2-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Allow specifying default clock schemeAngeloGioacchino Del Regno1-2/+13
The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qmp: Add SM8350 USB QMP PHYsJack Pham2-0/+312
Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused. Signed-off-by: Jack Pham <jackp@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-17phy: qcom-qmp: Add support for SDX55 QMP PHYManivannan Sadhasivam1-0/+83
Add support for USB3 QMP PHY found in SDX55 platform. SDX55 uses version 4.0.0 of the QMP PHY IP and doesn't make use of "com_aux" clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210111113010.32056-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-12-09Merge tag 'phy-for-5.11' of ↵Greg Kroah-Hartman7-20/+300
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy-for-5.11 - New phy drivers: - Mediatek MT7621 PCIe PHY (promoted from staging) - Ingenic USB phy driver supporting JZ4775 and X2000 - Intel Keem Bay USB PHY driver - Marvell USB HSIC PHY driver supporting MMP3 SoC - AXG MIPI D-PHY driver - Updates: - Conversion to YAML binding for: - Broadcom SATA PHY - Cadence Sierra PHY bindings - STM32 USBC Phy - Support for Exynos5433 PCIe PHY - Support for Qualcomm SM8250 PCIe QMP PHY - Support for Exynos5420 USB2 phy - devm_platform_ioremap_resource conversion for bunch of drivers * tag 'phy-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) drm/mediatek: avoid dereferencing a null hdmi_phy on an error message phy: ingenic: depend on HAS_IOMEM phy: mediatek: statify mtk_hdmi_phy_driver dt-bindings: phy: Convert Broadcom SATA PHY to YAML devicetree: phy: rockchip-emmc add output-tapdelay-select phy: rockchip-emmc: output tap delay dt property PHY: Ingenic: Add USB PHY driver using generic PHY framework. dt-bindings: USB: Add bindings for Ingenic JZ4775 and X2000. USB: PHY: JZ4770: Remove unnecessary function calls. devicetree: phy: rockchip-emmc: pulldown property phy: rockchip: set pulldown for strobe line in dts phy: renesas: rcar-gen3-usb2: disable runtime pm in case of failure phy: mediatek: allow compile-testing the hdmi phy phy/rockchip: Make PHY_ROCKCHIP_INNO_HDMI depend on HAS_IOMEM to fix build error phy: samsung: Merge Kconfig for Exynos5420 and Exynos5250 phy: ralink: phy-mt7621-pci: set correct name in MODULE_DEVICE_TABLE macro phy: ralink: phy-mt7621-pci: drop 'COMPILE_TEST' from Kconfig phy: mediatek: Make PHY_MTK_{XSPHY, TPHY} depend on HAS_IOMEM and OF_ADDRESS to fix build errors phy: tegra: xusb: Fix usb_phy device driver field phy: amlogic: replace devm_reset_control_array_get() ...
2020-11-16phy: qualcomm: Fix 28 nm Hi-Speed USB PHY OF dependencyBryan O'Donoghue1-1/+1
This Kconfig entry should declare a dependency on OF Fixes: 67b27dbeac4d ("phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20201113151225.1657600-3-bryan.odonoghue@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qualcomm: usb: Fix SuperSpeed PHY OF dependencyBryan O'Donoghue1-1/+1
This Kconfig entry should declare a dependency on OF Fixes: 6076967a500c ("phy: qualcomm: usb: Add SuperSpeed PHY driver") Reported-by: kernel test robot <lkp@intel.com> Link: https://lkml.org/lkml/2020/11/13/414 Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20201113151225.1657600-2-bryan.odonoghue@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qualcomm: convert to devm_platform_ioremap_resource(_byname)Chunfeng Yun5-16/+5
Use devm_platform_ioremap_resource(_byname) to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1604642930-29019-10-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: qcom-qmp: Add SM8250 PCIe QMP PHYsManivannan Sadhasivam2-4/+295
SM8250 has multiple different PHY versions: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Add support for these with relevant init sequence. In order to abstract the init sequence, this commit introduces secondary tables which can be used to factor out the unique sequence for each PHY while the former tables can have the common sequence. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201027170033.8475-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-10-28phy: qcom-qmp: Initialize another pointer to NULLStephen Boyd1-1/+1
This probe function is too complicated and should be refactored. For now let's just set this variable to NULL and keep the static analysis tools happy. Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20201026205942.2861828-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-10-02Merge tag 'phy-for-5.10' of ↵Greg Kroah-Hartman4-185/+973
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into usb-next Vinod writes: phy for 5.9 - Core: - New PHY attribute for max_link_rate - New phy drivers: - Rockchip dphy driver moved from staging - Socionext UniPhier AHCI PHY driver - Intel LGM SoC USB phy - Intel Keem Bay eMMC PHY driver - Updates: - Support for imx8mp usb phy - Support for DP Phy and USB3+DP combo phy in QMP driver - Support for Qualcomm sc7180 DP phy - Support for cadence torrent PCIe and USB single linke and multilink configurations along with USB, SGMII/QSGMII configurations * tag 'phy-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) phy: qcom-qmp: initialize the pointer to NULL phy: qcom-qmp: Add support for sc7180 DP phy phy: qcom-qmp: Add support for DP in USB3+DP combo phy phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify phy: qcom-qmp: Get dp_com I/O resource by index phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' phy: qcom-qmp: Move phy mode into struct qmp_phy dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information dt-bindings: phy: ti,phy-j721e-wiz: fix bindings for torrent phy dt-bindings: phy: cdns,torrent-phy: add reset-names phy: rockchip-dphy-rx0: Include linux/delay.h phy: fix USB_LGM_PHY warning & build errors phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configuration phy: cadence-torrent: Add PCIe + USB multilink configuration phy: cadence-torrent: Add single link USB register sequences phy: cadence-torrent: Add single link SGMII/QSGMII register sequences phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals phy: cadence-torrent: Add PHY link configuration sequences for single link phy: cadence-torrent: Add clk changes for multilink configuration ...
2020-10-01phy: qcom-qmp: initialize the pointer to NULLVinod Koul1-3/+3
Smatch complains: drivers/phy/qualcomm/phy-qcom-qmp.c:3899 qcom_qmp_phy_probe() error: uninitialized symbol 'dp_cfg'. drivers/phy/qualcomm/phy-qcom-qmp.c:3900 qcom_qmp_phy_probe() error: uninitialized symbol 'dp_serdes'. drivers/phy/qualcomm/phy-qcom-qmp.c:3902 qcom_qmp_phy_probe() error: uninitialized symbol 'usb_cfg'. This is a warning but not a practical one as dp_cfg, dp_serdes and usb_cfg will be set and used when valid. So we can set the pointers to NULL to quiesce the warnings. Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20201001070911.140019-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Add support for sc7180 DP phyStephen Boyd1-0/+124
Add the necessary compatible strings and phy data for the sc7180 USB3+DP combo phy. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-9-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Add support for DP in USB3+DP combo phyStephen Boyd2-90/+775
Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy driver. We already have support for the USB3 part of the combo phy, so most additions are for the DP phy. Split up the qcom_qmp_phy{enable,disable}() functions into the phy init, power on, power off, and exit functions that the common phy framework expects so that the DP phy can add even more phy ops like phy_calibrate() and phy_configure(). This allows us to initialize the DP PHY and configure the AUX channel before powering on the PHY at the link rate that was negotiated during link training. The general design is as follows: 1) DP controller calls phy_init() to initialize the PHY and configure the dp_com register region. 2) DP controller calls phy_configure() to tune the link rate and voltage swing and pre-emphasis settings. 3) DP controller calls phy_power_on() to enable the PLL and power on the phy. 4) DP controller calls phy_configure() again to tune the voltage swing and pre-emphasis settings determind during link training. 5) DP controller calls phy_calibrate() some number of times to change the aux settings if the aux channel times out during link training. 6) DP controller calls phy_power_off() if the link rate is to be changed and goes back to step 2 to try again at a different link rate. 5) DP controller calls phy_power_off() and then phy_exit() to power down the PHY when it is done. The DP PHY contains a PLL that is different from the one used for the USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk output from the DP PLL after going through various dividers. Introduce clk ops for these two clks that just tell the child clks what the frequency of the pixel and link are. When the phy link rate is configured we call clk_set_rate() to update the child clks in the display clk controller on what rate is in use. The clk frequencies always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or 8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or HBR3) so we simply store the link rate and use that to calculate the clk frequencies. The PLL enable sequence is a little different from other QMP phy PLLs so we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called from phy_power_on(). This should probably be split out better so that each phy has a way to run the final PLL/PHY enable sequence. This code is based on a submission of this phy and PLL in the drm subsystem. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplifyStephen Boyd1-8/+3
We can use the wrapper API here to save some lines and remove the need for the 'base' and 'res' local variable. Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-7-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Get dp_com I/O resource by indexStephen Boyd1-7/+3
The dp_com resource is always at index 1 according to the dts files in the kernel. Get this resource by index so that we don't need to make future additions to the DT binding use 'reg-names'. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-6-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'Stephen Boyd1-57/+56
The serdes I/O region is where the PLL for the phy is controlled. Sometimes the PLL is shared between multiple phys, for example in the PCIe case where there are three phys inside the same wrapper. Other times the PLL is for a single phy, i.e. some USB3 phys. To complete the trifecta we have the USB3+DP combo phy where the USB3 and DP phys each have their own serdes region because they have their own PLL while they both share a common I/O region pertaining to the USB type-c pinout and cable orientation. Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can correlate PLL control to the phy that uses it. This allows us to support the USB3+DP combo phy in this driver. This isn't a problem for the 3-lane/phy PCIe phy because there is a common init function that is the only place the serdes region is programmed. Furthermore, move the configuration data that contains most of the register programming sequences to the qmp phy struct. This data isn't qmp wrapper specific. It is phy specific data used to tune various settings for things like pre-emphasis, bias, etc. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-5-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'Stephen Boyd1-7/+2
We already track if any phy inside the qmp wrapper has been initialized by means of the struct qcom_qmp::init_count member. Let's drop the duplicate 'initialized' member to simplify the code a bit. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-4-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28phy: qcom-qmp: Move phy mode into struct qmp_phyStephen Boyd1-8/+7
The phy mode pertains to the phy itself, i.e. 'struct qmp_phy', not the wrapper, i.e. 'struct qcom_qmp'. Move the phy mode into the phy structure to more accurately reflect what is going on. This also cleans up 'struct qcom_qmp' so that it can eventually be the place where qmp wrapper wide data is located, paving the way for the USB3+DP combo phy. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-3-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-08phy: phy-qcom-apq8064-sata: convert to readl_relaxed_poll_timeout()Chunfeng Yun1-13/+8
Use readl_relaxed_poll_timeout() to simplify code, rename local function read_poll_timeout() as poll_timeout() to avoid repeated definition Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1598320987-25518-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-04Merge tag 'phy-fixes-5.9' of ↵Greg Kroah-Hartman3-10/+13
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-linus Vinod writes: phy: fixes for 5.9 *) platform_no_drv_owner.cocci and return value check qcom ipq806x-usb driver *) correcting register programming for ipq8074 phy *) disable PHY charger detect for omap-usb2-phy * tag 'phy-fixes-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: omap-usb2-phy: disable PHY charger detect phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init phy: qualcomm: fix return value check in qcom_ipq806x_usb_phy_probe() phy: qualcomm: fix platform_no_drv_owner.cocci warnings
2020-08-31phy: qcom-ipq4019-usb: Constify static phy_ops structsRikard Falkeborn1-2/+2
Their only usages is to assign the address to the data field in the of_device_id struct, which is a const void pointer. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200823220025.17588-9-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-08-24treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-1/+1
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
2020-08-23phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY initSivaprakash Murugesan2-7/+11
There were some problem in ipq8074 Gen2 PCIe phy init sequence. 1. Few register values were wrongly updated in the phy init sequence. 2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter register which is added in serdes table causing the wrong register was getting updated. 3. Clocks and resets were not added in the phy init. Fix these to make Gen2 PCIe port on ipq8074 devices to work. Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074") Cc: stable@vger.kernel.org Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1596036607-11877-4-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-08-17phy: qualcomm: fix return value check in qcom_ipq806x_usb_phy_probe()Wei Yongjun1-2/+2
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200723113622.136752-1-weiyongjun1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-08-17phy: qualcomm: fix platform_no_drv_owner.cocci warningsYueHaibing1-1/+0
Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200725031624.31432-1-yuehaibing@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-21phy: qualcomm: fix setting of tx_deamp_3_5db when device property read failsColin Ian King1-1/+1
Currently when reading of the device property for "qcom,tx-deamp_3_5db" fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This looks like a copy-n-paste error and in fact should be assigning the default instead to phy_dwc3->tx_deamp_3_5db Addresses-Coverity: ("Copy-paste error") Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-20phy: qualcomm: add qcom ipq806x dwc usb phy driverAnsuel Smith3-0/+582
This has lost in the original push for the dwc3 qcom driver. This is needed for ipq806x SoC as without this the usb ports doesn't work at all. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Tested-by: Jonathan McDowell <noodles@earth.li> Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-08phy: qcom: remove ufs qmp phy driverVinod Koul8-1598/+0
The UFS specific QMP PHY driver started off supporting the 14nm and 20nm hardware. With the 20nm support marked broken for a long time and the 14nm support added to the common QMP PHY, this driver has not been used in a while. So delete it Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200629145452.123035-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-snps: Add a set mode callbackWesley Cheng1-0/+12
The set mode handler is used to keep track of the current role of the device. This is used for enabling certain resources within the PHY depending on if the device is behaving as a host or device. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/20200625195444.15130-3-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-snps: Add runtime suspend and resume handlersWesley Cheng1-0/+73
Allow for the PHY to be put into a powered down state when possible. Add the required suspend and resume callbacks, which will determine what resources can be turned off depending on the cable status. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/20200625195444.15130-2-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-qmp: Add QMP V4 USB3 PHY support for sm8250Jonathan Marek2-0/+208
Add both the DP and UNI PHY for primary/secondary usb controllers. The tables are very similar to sm8150 (serdes_tbl is identical), but there are some differences. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200524021416.17049-4-jonathan@marek.ca Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-qmp: Add QMP V4 USB3 UNIPHYJonathan Marek2-0/+155
Add support for the USB3 PHY used by the secondary usb controller on sm8150 Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200524021416.17049-3-jonathan@marek.ca Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: qcom-qmp: Allow different values for second laneJonathan Marek1-12/+40
The primary USB PHY on sm8250 sets some values differently for the second lane. This makes it possible to represent that. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200524021416.17049-2-jonathan@marek.ca Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: qcom-qusb2: Add ipq8074 device compatibleSivaprakash Murugesan1-0/+3
Add ipq8074 qusb2 device compatible for high speed usb support. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Tested-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Link: https://lore.kernel.org/r/1591625479-4483-5-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-24phy: qcom-qmp: Add USB QMP PHY support for IPQ8074Sivaprakash Murugesan1-0/+102
Add QMP USB PHY found in IPQ8074 Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Tested-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1591625479-4483-4-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-22Merge tag 'phy-for-5.8' of ↵Greg Kroah-Hartman6-44/+902
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into usb-next Kishon writes: phy: for 5.8 *) Add new PHY driver to support Cadence SALVO PHY which supports USB3 & USB2 *) Add new PHY driver to support Intel ComboPhy which supports PCIe, SATA and EMAC *) Add new PHY driver for Qualcomm IPQ40xx USB PHY *) Add new PHY driver for Synopsys FemtoPHY V2 driver used in Qualcomm SOCs *) Add support for Qualcomm SM8250 UFS PHY and SM8150 QMP USB3 PHY in qcom-qmp-phy driver *) Add support for Amlogic USB2 PHY on Meson8m2 in phy-meson8b-usb2 driver *) Add DisplayPort mode support in Wiz (TI Cadence PHY wrapper), to enable eDP in TI's J721E SoC *) Add support for super speed USB PHY in TI's AM654 SoC *) Add fix in Broadcom Stingray USB PHY to get USB PHY PLL lock reliably *) Add fix in Samsung phy-s5pv210-usb2 to get USB working on s5pv210 *) Add fix in Amlogic phy-meson8b-usb2 to get host only mode working on Meson8 *) Add fix in Cadence phy-cadence-sierra to get USB3 device disconnect issue *) Convert meson8b-usb2-phy, qcom-qmp-phy, rcar-gen3-phy-usb2 and rcar-gen3-phy-usb3 device tree binding to YAML schema *) Minor fixes and cleanups in phy-cpcap-usb, j721e-wiz, omap-usb2, phy-bcm-sr-usb, phy-brcm-usb PHY driver Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) phy: intel: Add driver support for ComboPhy dt-bindings: phy: Add YAML schemas for Intel ComboPhy dt-bindings: phy: Add PHY_TYPE_XPCS definition phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180 dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180 dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml phy: cadence: sierra: Fix for USB3 U1/U2 state phy: ti: am654: add support for USB super-speed phy: ti: am654: show up in regmap debugfs drivers: phy: sr-usb: do not use internal fsm for USB2 phy init dt-bindings: phy: renesas: usb3-phy: add r8a77961 support dt-bindings: phy: renesas: usb3-phy: convert bindings to json-schema dt-bindings: phy: renesas: usb2-phy: add r8a77961 support dt-bindings: phy: renesas: usb2-phy: convert bindings to json-schema phy: qcom-qmp: Ensure register indirection arrays initialized phy: omap-usb2: Clean up exported header phy: phy-bcm-ns2-usbdrd: Constify phy_ops phy: phy-brcm-usb: Constify static structs phy: sr-usb: Constify phy_ops ...
2020-05-19phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180Sandeep Maheswaram1-0/+38
Adding QMP v3 USB3 PHY support for SC7180. Adding only usb phy reset in the list to avoid reset of DP block. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1589510358-3865-5-git-send-email-sanm@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-18phy: qcom-qmp: Ensure register indirection arrays initializedBjorn Andersson1-9/+11
It's possible that struct qmp_phy_cfg->regs references an array that is smaller than the possible register lookups that is going to be performed, with the resulting out-of-bounds read resulting in undefined behavior. One such example is when during qcom_qmp_phy_com_init() performs a qphy_setbits() on entry QPHY_PCS_POWER_DOWN_CONTROL (i.e. 17) with msm8996_ufsphy_regs_layout only being 12 entries long. Solve this by inflating all "regs_layout" arrays to ensure that any remaining entries are zero-initialized, as expected by the code. Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200515013643.2081941-1-bjorn.andersson@linaro.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-05phy: qcom-qmp: Rename UFS PCS QMP v4 registersWesley Cheng2-30/+30
The UFS QMP v4 PHY has a largely different register set versus USB and PCIe. Rename the register offsets to denote that the value is specific for the UFS PCS register. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USBWesley Cheng1-4/+19
The register map for SM8150 QMP USB SSPHY has moved QPHY_POWER_DOWN_CONTROL to a different offset. Allow for an offset in the register table to override default value if it is a DP capable PHY. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05phy: qcom-qmp: Add SM8150 QMP USB3 PHY supportJack Pham2-2/+348
Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCsWesley Cheng3-0/+298
This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There are potentially multiple instances of this UTMI PHY on the SOC, all which can utilize this driver. The V2 driver will have a different register map compared to V1. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Philipp Zabel <pza@pengutronix.de> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-27 16:18:59 +0300