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path: root/drivers/pinctrl/pinctrl-gemini.c
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2018-10-10pinctrl: gemini: Fix up TVC clock groupLinus Walleij1-8/+36
The previous fix made the TVC clock get muxed in on the D-Link DIR-685 instead of giving nagging warnings of this not working. Not good. We didn't want that, as it breaks video. Create a specific group for the TVC CLK, and break out a specific GPIO group for it on the SL3516 so we can use that line as GPIO if we don't need the TVC CLK. Fixes: d17f477c5bc6 ("pinctrl: gemini: Mask and set properly") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10pinctrl: gemini: Drop noisy debug printsLinus Walleij1-16/+16
The dev_info() in the pin control driver is really just good for debug, so drop it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-10pinctrl: gemini: Mask and set properlyLinus Walleij1-1/+2
The code was written under the assumption that the regmap_update_bits() would mask the bits in the mask and set the bits in the value. It missed the points that it will not set bits in the value unless these are also masked in the mask. Set value bits that are not in the mask will simply be ignored. Fixes: 06351d133dea ("pinctrl: add a Gemini SoC pin controller") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-06-26pinctrl: gemini: Mask properlyLinus Walleij1-0/+2
Some logical error in the gemini pin control driver made it not mask and write properly for the GMAC. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-03Merge tag 'pinctrl-v4.16-1' of ↵Linus Torvalds1-1/+83
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.16 kernel cycle. Like with GPIO it is actually a bit calm this time. Core changes: - After lengthy discussions and partly due to my ignorance, we have merged a patch making pinctrl_force_default() and pinctrl_force_sleep() reprogram the states into the hardware of any hogged pins, even if they are already in the desired state. This only apply to hogged pins since groups of pins owned by drivers need to be managed by each driver, lest they could not do things like runtime PM and put pins to sleeping state even if the system as a whole is not in sleep. New drivers: - New driver for the Microsemi Ocelot SoC. This is used in ethernet switches. - The X-Powers AXP209 GPIO driver was extended to also deal with pin control and moved over from the GPIO subsystem. This circuit is a mixed-mode integrated circuit which is part of AllWinner designs. - New subdriver for the Qualcomm MSM8998 SoC, core of a high end mobile devices (phones) chipset. - New subdriver for the ST Microelectronics STM32MP157 MPU and STM32F769 MCU from the STM32 family. - New subdriver for the MediaTek MT7622 SoC. This is used for routers, repeater, gateways and such network infrastructure. - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has multimedia features and target "smart devices", I guess in-car entertainment, in-flight entertainment, industrial control panels etc. General improvements: - Incremental improvements on the SH-PFC subdrivers for things like the CAN bus. - Enable the glitch filter on Baytrail GPIOs used for interrupts. - Proper handling of pins to GPIO ranges on the Semtec SX150X - An IRQ setup ordering fix on MCP23S08. - A good set of janitorial coding style fixes" * tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits) pinctrl: mcp23s08: fix irq setup order pinctrl: Forward declare struct device pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding pinctrl: stm32: add STM32F769 MCU support pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping pinctrl: sx150x: Register pinctrl before adding the gpiochip pinctrl: sx150x: Unregister the pinctrl on release pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe() pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show() pinctrl: pinmux: Use seq_putc() in pinmux_pins_show() pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show() pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call pinctrl: mediatek: mt7622: fix potential uninitialized value being returned pinctrl: uniphier: refactor drive strength get/set functions pinctrl: imx7ulp: constify struct imx_cfg_params_decode pinctrl: imx: constify struct imx_pinctrl_soc_info pinctrl: imx7d: simplify imx7d_pinctrl_probe pinctrl: imx: use struct imx_pinctrl_soc_info as a const pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly. pinctrl: qcom: Add msm8998 pinctrl driver ...
2017-12-07pinctrl: gemini: Support drive strength settingLinus Walleij1-0/+81
The Gemini pin controller can set drive strength for a few select groups of pins (not individually). Implement this for GMAC0 and 1 (ethernet ports), IDE and PCI. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-30pinctrl: gemini: Fix usage of 3512 groupsLinus Walleij1-1/+1
The pin config lookup function was still hardcoding the 3516 pin set, which is obviously wrong. Use the pointer in the state container. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-30pinctrl: gemini: Add two missing GPIO groupsLinus Walleij1-1/+2
The 3512 has two more GPIO groups on GPIO area 0, so let's make it possible to combine these with the function. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-14pinctrl: gemini: Fix missing pad descriptionsLinus Walleij1-0/+2
A pretty clever static checker found a bug in my patch: I added more bits to a bitmask but didn't extend the array indexed to the same bitmask. Fixes: 756a024f3983 ("pinctrl: gemini: Fix GMAC groups") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Fix GMAC groupsLinus Walleij1-25/+54
The GMII groups need to be split across GMAC0 and GMAC1 since GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7 so we might want just one interface out. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Implement clock skew/delay configLinus Walleij1-4/+174
This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Use generic DT parserLinus Walleij1-62/+4
We can just use the generic Device Tree parser code in this driver and save some code. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-14pinctrl: gemini: Add missing functionsLinus Walleij1-0/+10
Some two functions were missing from the Gemini pin control driver. Noticed when trying to use ethernet. Fix it up by adding them. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: add a Gemini SoC pin controllerLinus Walleij1-0/+2359
This adds a pin control (only multiplexing) driver for the Gemini SoC so we can sort out this complex platform in an orderly manner. This driver will detect the chip/package version as SL3512 or SL3516 (also known as CS3512 and CS3516 etc) and register the apropriate pin set. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>