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path: root/drivers/pinctrl/qcom/pinctrl-msm8660.c
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2023-10-10pinctrl: qcom/msm: Convert to platform remove callback returning voidUwe Kleine-König1-1/+1
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). To convert all those qcom pinctrl drivers, make msm_pinctrl_remove() return void (instead of zero) and use .remove_new in all drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231009162510.335208-3-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-16pinctrl: qcom: Refactor generic qcom pinctrl driverRohit Agarwal1-6/+6
Reuse the generic pingroup struct from pinctrl.h in msm_pingroup along with the macro defined. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-05-16pinctrl: qcom: Remove the msm_function structRohit Agarwal1-124/+116
Remove the msm_function struct to reuse the generic pinfunction struct. Also, define a generic PINFUNCTION macro that can be used across qcom target specific pinctrl files to avoid code repetition. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner1-9/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-01-03pinctrl: qcom: msm8660: rename some SDC1->SDC4Linus Walleij1-3/+3
These four pins are for SDC4, not SDC1. They are grouped for SDC4 later in the file so this must be a typo. Reviewed-by: Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-08pinctrl: qcom: establish proper EBI2 pin groupsLinus Walleij1-22/+46
After some digging around I found documentation (!) of the APQ8060 EBI2 pin groups. It turns out I first need to split the group in two: ebi2cs and ebi2 proper. The chip select pins are kind of orthogonal to the other EBI2 pins since CS1B and CS2B can be muxed over address bits 7 and 6 (don't know why, but they can). This is good to fix up before we add users. Also found what the "holes" in the assignment all the way up to gpio158 was actually for. All mux documentation comes from "Snapdragon(TM) S3 APQ8060-based DragonBoard(TM) GPIO User Guide Rev. E August 10, 2012", published by Bsquare Corporation. As the documentation seems a bit hard to come by I put some comments in the group definitions so that it is clear to all readers what is going on here and what the lines are used for. Cc: Björn Andersson <bjorn.andersson@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-04pinctrl: qcom: add support for EBI2Linus Walleij1-32/+42
Add support to mux in the second external bus interface as follows: - CS1 and CS2 on GPIO39 and GPIO40 as func 2 - ADDR_7 thru ADDR_0 on GPIO123 thru GPIO130 as func 1 - CS4, CS3 and CS0 on GPIO132, GPIO133, GPIO134 as func 1 - DATA_15 thru DATA_0 on GPIO135 thru GPIO150 as func 1 - OE on GPIO151 as func 1 - ADV on GPIO153 as func 1 - WE on GPIO157 as func 1 This external bus is used on the APQ8060 Dragonboard to connect an external SMSC9211 ethernet adapter, but there are many other usecases for the EBI2. Cc: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Björn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: qcom: Add MSM8660 pinctrl definitionsBjorn Andersson1-0/+984
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>