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2022-05-28Merge tag 'pinctrl-v5.19-1' of ↵Linus Torvalds97-3912/+6678
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Pretty big this time. Mostly due to (nice) Renesas refactorings. Core changes: - New helpers from Andy such as for_each_gpiochip_node() affecting both GPIO and pin control, improving a bunch of drivers in the process. - Pulled in Marc Zyngiers work to make IRQ chips immutable, and started to apply fixups on top. New drivers: - New driver for Marvell MVEBU 98DX2530. - New driver for Mediatek MT8195. - Support Qualcomm PMX65 and PM6125. - New driver for Qualcomm SC7280 LPASS pin control. - New driver for Rockchip RK3588. - New driver for NXP Freescale i.MXRT1170. - New driver for Mediatek MT6795 Helio X10. Improvements: - Several Aspeed G6 cleanups and non-critical fixes. - Thorought refactoring of some of the ever improving Renesas drivers. - Clean up Mediatek MT8192 bindings a bit. - PWM output and clock monitoring in the Ocelot LAN966x driver. - Thorough refactoring and cleanup of the Ralink drivers such as RT2880, RT3883, RT305X, MT7620, MT7621, MT7628 splitting these into proper sub-drivers" * tag 'pinctrl-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (161 commits) pinctrl: apple: Use a raw spinlock for the regmap pinctrl: berlin: bg4ct: Use devm_platform_*ioremap_resource() APIs pinctrl: intel: Fix kernel doc format, i.e. add return sections dt-bindings: pinctrl: qcom: Drop 'maxItems' on 'wakeup-parent' pinctrl: starfive: Make the irqchip immutable pinctrl: mediatek: Add pinctrl driver for MT6795 Helio X10 dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings pinctrl: freescale: Add i.MXRT1170 pinctrl driver support dt-bindings: pinctrl: add i.MXRT1170 pinctrl Documentation dt-bindings: pinctrl: rockchip: increase max amount of device functions dt-bindings: pinctrl: qcom,pmic-gpio: add 'gpio-reserved-ranges' dt-bindings: pinctrl: qcom,pmic-gpio: add 'input-disable' dt-bindings: pinctrl: qcom,pmic-gpio: describe gpio-line-names dt-bindings: pinctrl: qcom,pmic-gpio: fix matching pin config dt-bindings: pinctrl: qcom,pmic-gpio: document PM8150L and PMM8155AU pinctrl: qcom: spmi-gpio: Add pm6125 compatible dt-bindings: pinctrl: qcom-pmic-gpio: Add pm6125 compatible pinctrl: intel: Drop unused irqchip member in struct intel_pinctrl pinctrl: intel: make irq_chip immutable pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask() ...
2022-05-27Merge tag 'gpio-updates-for-v5.19' of ↵Linus Torvalds12-252/+187
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio updates from Bartosz Golaszewski: "We have lots of small changes all over the place, but no huge reworks or new drivers: - use ioread()/iowrite() interfaces instead of raw inb()/outb() in drivers - make irqchips immutable due to the new warning popping up when drivers try to modify the irqchip structures - add new compatibles to dt-bindings for realtek-otto, renesas-rcar and pca95xx - add support for new models to gpio-rcar, gpio-pca953x & gpio-realtek-otto - allow parsing of GPIO hogs represented as children nodes of gpio-uniphier - define a set of common GPIO consumer strings in dt-bindings - shrink code in gpio-ml-ioh by using more devres interfaces - pass arguments to devm_kcalloc() in correct order in gpio-sim - add new helpers for iterating over GPIO firmware nodes and descriptors to gpiolib core and use it in several drivers - drop unused syscon_regmap_lookup_by_compatible() function - correct format specifiers and signedness of variables in GPIO ACPI - drop unneeded error checks in gpio-ftgpio - stop using the deprecated of_gpio.h header in gpio-zevio - drop platform_data support in gpio-max732x - simplify Kconfig dependencies in gpio-vf610 - use raw spinlocks where needed to make PREEMPT_RT happy - fix return values in board files using gpio-pcf857x - convert more drivers to using fwnode instead of of_node - minor fixes and improvements in gpiolib core" * tag 'gpio-updates-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (55 commits) gpio: sifive: Make the irqchip immutable gpio: rcar: Make the irqchip immutable gpio: pcf857x: Make the irqchip immutable gpio: pca953x: Make the irqchip immutable gpio: dwapb: Make the irqchip immutable gpio: sim: Use correct order for the parameters of devm_kcalloc() gpio: ml-ioh: Convert to use managed functions pcim* and devm_* gpio: ftgpio: Remove unneeded ERROR check before clk_disable_unprepare gpio: ws16c48: Utilize iomap interface gpio: gpio-mm: Utilize iomap interface gpio: 104-idio-16: Utilize iomap interface gpio: 104-idi-48: Utilize iomap interface gpio: 104-dio-48e: Utilize iomap interface gpio: zevio: drop of_gpio.h header gpio: max77620: Make the irqchip immutable dt-bindings: gpio: pca95xx: add entry for pca6408 gpio: pca953xx: Add support for pca6408 gpio: max732x: Drop unused support for irq and setup code via platform data gpio: vf610: drop the SOC_VF610 dependency for GPIO_VF610 gpio: syscon: Remove usage of syscon_regmap_lookup_by_compatible ...
2022-05-25pinctrl: apple: Use a raw spinlock for the regmapHector Martin1-0/+1
The irqchip ops are called with a raw spinlock held, so the subsequent regmap usage cannot use a plain spinlock. spi-hid-apple-of spi0.0: spihid_apple_of_probe:74 ============================= [ BUG: Invalid wait context ] 5.18.0-asahi-00176-g0fa3ab03bdea #1337 Not tainted ----------------------------- kworker/u20:3/86 is trying to lock: ffff8000166b5018 (pinctrl_apple_gpio:462:(&regmap_config)->lock){....}-{3:3}, at: regmap_lock_spinlock+0x18/0x30 other info that might help us debug this: context-{5:5} 7 locks held by kworker/u20:3/86: #0: ffff800017725d48 ((wq_completion)events_unbound){+.+.}-{0:0}, at: process_one_work+0x1c8/0x670 #1: ffff80001e33bdd0 (deferred_probe_work){+.+.}-{0:0}, at: process_one_work+0x1c8/0x670 #2: ffff800017d629a0 (&dev->mutex){....}-{4:4}, at: __device_attach+0x30/0x17c #3: ffff80002414e618 (&ctlr->add_lock){+.+.}-{4:4}, at: spi_add_device+0x40/0x80 #4: ffff800024116990 (&dev->mutex){....}-{4:4}, at: __device_attach+0x30/0x17c #5: ffff800022d4be58 (request_class){+.+.}-{4:4}, at: __setup_irq+0xa8/0x720 #6: ffff800022d4bcc8 (lock_class){....}-{2:2}, at: __setup_irq+0xcc/0x720 Fixes: a0f160ffcb83 ("pinctrl: add pinctrl/GPIO driver for Apple SoCs") Signed-off-by: Hector Martin <marcan@marcan.st> Link: https://lore.kernel.org/r/20220524142206.18833-1-marcan@marcan.st Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-24Merge tag 'irq-core-2022-05-23' of ↵Linus Torvalds3-36/+57
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull interrupt handling updates from Thomas Gleixner: "Core code: - Make the managed interrupts more robust by shutting them down in the core code when the assigned affinity mask does not contain online CPUs. - Make the irq simulator chip work on RT - A small set of cpumask and power manageent cleanups Drivers: - A set of changes which mark GPIO interrupt chips immutable to prevent the GPIO subsystem from modifying it under the hood. This provides the necessary infrastructure and converts a set of GPIO and pinctrl drivers over. - A set of changes to make the pseudo-NMI handling for GICv3 more robust: a missing barrier and consistent handling of the priority mask. - Another set of GICv3 improvements and fixes, but nothing outstanding - The usual set of improvements and cleanups all over the place - No new irqchip drivers and not even a new device tree binding! 100+ interrupt chips are truly enough" * tag 'irq-core-2022-05-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (39 commits) irqchip: Add Kconfig symbols for sunxi drivers irqchip/gic-v3: Fix priority mask handling irqchip/gic-v3: Refactor ISB + EOIR at ack time irqchip/gic-v3: Ensure pseudo-NMIs have an ISB between ack and handling genirq/irq_sim: Make the irq_work always run in hard irq context irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x irqchip/gic: Improved warning about incorrect type irqchip/csky: Return true/false (not 1/0) from bool functions irqchip/imx-irqsteer: Add runtime PM support irqchip/imx-irqsteer: Constify irq_chip struct irqchip/armada-370-xp: Enable MSI affinity configuration irqchip/aspeed-scu-ic: Fix irq_of_parse_and_map() return value irqchip/aspeed-i2c-ic: Fix irq_of_parse_and_map() return value irqchip/sun6i-r: Use NULL for chip_data irqchip/xtensa-mx: Fix initial IRQ affinity in non-SMP setup irqchip/exiu: Fix acknowledgment of edge triggered interrupts irqchip/gic-v3: Claim iomem resources dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicit irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWP irqchip/gic-v3: Detect LPI invalidation MMIO registers ...
2022-05-22Merge tag 'intel-pinctrl-v5.19-2' of ↵Linus Walleij6-72/+110
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.19-2 * Fix immutable IRQ chip examples in the GPIO documentation * Make use of immutable IRQ chip in Intel pin control drivers * Add module alias for Intel Apollo Lake The following is an automated git shortlog grouped by driver: baytrail: - make irq_chip immutable broxton: - Add module alias for Intel Apollo Lake cherryview: - Use GPIO chip pointer in chv_gpio_irq_mask_unmask() - make irq_chip immutable Documentation: - gpio: Advertise irqd_to_hwirq() helper in the examples - gpio: Fix IRQ mask and unmask examples intel: - Fix kernel doc format, i.e. add return sections - Drop unused irqchip member in struct intel_pinctrl - make irq_chip immutable lynxpoint: - make irq_chip immutable
2022-05-22pinctrl: berlin: bg4ct: Use devm_platform_*ioremap_resource() APIszhaoxiao1-2/+1
Use devm_platform_get_and_ioremap_resource() and devm_platform_ioremap_resource() APIs instead of their open coded analogues. Signed-off-by: zhaoxiao <zhaoxiao@uniontech.com> Link: https://lore.kernel.org/r/20220520052021.25631-1-zhaoxiao@uniontech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-20pinctrl: intel: Fix kernel doc format, i.e. add return sectionsAndy Shevchenko1-0/+5
Kernel doc validator is not happy: pinctrl-intel.c:865: warning: No description found for return value of 'intel_gpio_to_pin' pinctrl-intel.c:904: warning: No description found for return value of 'intel_pin_to_gpio' 2 warnings Add return sections to the kernel documentation of the above mentioned functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-19Merge tag 'pinctrl-v5.18-3' of ↵Linus Torvalds3-4/+6
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - Fix an altmode in the Ocelot driver - Fix the IES control pins in the Mediatek MT8365 driver - Sunxi (AMLogic) driver: - Fix the UART2 function pin assignments - Fix the signal name of the PA2 SPI pin * tag 'pinctrl-v5.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: sunxi: f1c100s: Fix signal name comment for PA2 SPI pin pinctrl: sunxi: fix f1c100s uart2 function pinctrl: mediatek: mt8365: fix IES control pins pinctrl: ocelot: Fix for lan966x alt mode
2022-05-19pinctrl: starfive: Make the irqchip immutableGeert Uytterhoeven1-3/+8
Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning to indicate if the gpiolib is altering the internals of irqchips. Following this change the following warning is now observed for the starfive driver: gpio gpiochip0: (11910000.pinctrl): not an immutable chip, please consider fixing it! Fix this by making the irqchip in the starfive driver immutable. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5eb66be34356afd5eb0ea9027329e0939d03d3a0.1652884852.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-19pinctrl: mediatek: Add pinctrl driver for MT6795 Helio X10AngeloGioacchino Del Regno4-0/+2329
Add support for the MediaTek Helio X10 (MT6795) SoC's GPIO/pinmux controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220517083957.11816-3-angelogioacchino.delregno@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-19pinctrl: freescale: Add i.MXRT1170 pinctrl driver supportJesse Taube3-0/+357
Add the pinctrl driver support for i.MXRT1170. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20220517032802.451743-11-Mr.Bossman075@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-19pinctrl: qcom: spmi-gpio: Add pm6125 compatibleMarijn Suijten1-0/+1
The pm6125 has 9 GPIOs with no holes inbetween. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220511220613.1015472-4-marijn.suijten@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-18pinctrl: intel: Drop unused irqchip member in struct intel_pinctrlAndy Shevchenko1-2/+0
There is no users of irqchip member in struct intel_pinctrl. Drop it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-18pinctrl: intel: make irq_chip immutableAndy Shevchenko1-15/+25
Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-17pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask()Andy Shevchenko1-4/+3
The callers already have dereferenced pointer to GPIO chip, no need to do it again in chv_gpio_irq_mask_unmask(). Hence, replace IRQ data pointer by GPIO chip pointer. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-16pinctrl: lynxpoint: make irq_chip immutableAndy Shevchenko1-10/+16
Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch hwirq variable to use the correct type for the sake of consistency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-16pinctrl: cherryview: make irq_chip immutableAndy Shevchenko1-27/+38
Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch to use hwirq variable instead of pin for the sake of consistency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-16pinctrl: baytrail: make irq_chip immutableAndy Shevchenko1-17/+25
Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. While at it, switch to use hwirq variable instead of offset for the sake of consistency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-14pinctrl: stm32: Unshadow np variable in stm32_pctl_probe()Andy Shevchenko1-12/+9
The np variable is used globally for stm32_pctl_probe() and in one of its code branches. cppcheck is not happy with that: pinctrl-stm32.c:1530:23: warning: Local variable 'np' shadows outer variable [shadowVariable] Instead of simply renaming one of the variables convert some code to use a device pointer directly. Fixes: bb949ed9b16b ("pinctrl: stm32: Switch to use for_each_gpiochip_node() helper") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20220507102257.26414-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-14pinctrl: sunxi: f1c100s: Fix signal name comment for PA2 SPI pinAndre Przywara1-1/+1
The manual describes function 0x6 of pin PA2 as "SPI1_CLK", so change the comment to reflect that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220504170736.2669595-1-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-14pinctrl: sunxi: fix f1c100s uart2 functionIotaHydrae1-1/+1
Change suniv f1c100s pinctrl,PD14 multiplexing function lvds1 to uart2 When the pin PD13 and PD14 is setting up to uart2 function in dts, there's an error occurred: 1c20800.pinctrl: unsupported function uart2 on pin PD14 Because 'uart2' is not any one multiplexing option of PD14, and pinctrl don't know how to configure it. So change the pin PD14 lvds1 function to uart2. Signed-off-by: IotaHydrae <writeforever@foxmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/tencent_70C1308DDA794C81CAEF389049055BACEC09@qq.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-14Merge tag 'renesas-pinctrl-for-v5.19-tag2' of ↵Linus Walleij35-2497/+1173
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.19 (take two) - Reserved field optimizations, - Miscellaneous fixes and improvements.
2022-05-11pinctrl: broxton: Add module alias for Intel Apollo LakeAndy Shevchenko1-0/+1
We have platform device IDs for Broxton and Apollo Lake, but module alias is provided only for the former. Make it consistent by providing an alias for Apollo Lake. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-05-09pinctrl: microchip-sgpio: Switch to use fwnode instead of of_nodeAndy Shevchenko1-1/+1
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220503151517.59115-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-09pinctrl: equilibrium: Switch to use fwnode instead of of_nodeAndy Shevchenko2-10/+11
GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220503151321.58800-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-05pinctrl: microchip-sgpio: make irq_chip immutableMichael Walle1-5/+9
Since recently, the kernel is nagging about mutable irq_chips: [ 4.967050] gpio gpiochip1: (e2004190.gpio-input): not an immutable chip, please consider fixing it! Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220428111622.1395831-1-michael@walle.cc Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-05Merge branch 'irq/gpio-immutable' of ↵Linus Walleij3-36/+57
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into devel
2022-05-05pinctrl: stm32: Fix up errorpath after mergeLinus Walleij1-0/+4
When merging the for_each_gpiochip_node() changes, I made some mistakes by not disabling the clocks on the errorpath, fix it up. Fixes: a0912083086d ("Merge tag 'intel-gpio-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel") Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Fabien Dessenne <fabien.dessenne@foss.st.com> Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-05-05Merge branch 'irq/gpio-immutable' of ↵Bartosz Golaszewski3-36/+57
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into gpio/for-next This pulls in changes improving the handling of immutable irqchips in core gpiolib and several drivers.
2022-05-05pinctrl: renesas: checker: Add reserved field checksGeert Uytterhoeven1-1/+10
Add checks for discovering registers with reserved fields that could benefit from being described using variable-width reserved field shorthands, reducing kernel size. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7786: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-13/+8
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 79 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/22487451ff7d8cce0182354c9553f3b171cc34d9.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7785: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-36/+24
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 150 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/07a238f13f80674d86719a5e869c65a2e0b8c1c1.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7757: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-57/+38
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 115 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/05c69ca8710134bb96ec8f7d18bafe42418f3510.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7734: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-12/+9
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 161 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/18e476c0a9f0af5b5d511d1c4922c6e299d1847a.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7724: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-3/+4
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 8 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/696dcad42a8b8395276301eb5dd5c5a895826f35.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7723: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-31/+39
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 105 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/5d7ef2fa02c2137d2d243fc183d18220c9aaf7b8.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7722: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-122/+80
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 396 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c3965b6f9ea603b185924136f859c6eca7d5d6f4.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7720: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-29/+28
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 128 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/4b290f93a7edb1f91c97da90e67b7f6f3df62951.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh73a0: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-57/+30
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 154 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e74738b403cc15b3407e7568d323fdae8e7b30dd.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7269: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-39/+43
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 406 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/feb1e865c2b6abbc0db24243143ea09ad143f6df.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7264: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-52/+52
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 572 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/434c274f626b2eab3539fe2ab80c6eda164e07fa.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: sh7203: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-32/+21
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 281 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c625b4eee298b88c2ee47ed80b0dea5d02ed56d1.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-60/+27
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 183 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e50f9c8ef1261b7ceb6b1be637d4019fe7312250.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a779a0: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-131/+72
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 556 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7db3751ecf96fcc469bd14eeb02d69e565956151.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a77995: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-85/+22
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 422 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d74af80fdb7b6d78b10634238a88e55a139e5c22.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a77990: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-92/+29
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 226 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/924ba4505e33180e078ca72a1db8db13c193cbea.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a77980: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-63/+28
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 198 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/0bf6b069a794b3c56c0c9311ac4b2ada577a9cb7.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a77970: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-93/+29
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 268 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/33dd9bc41df888f132e2e6921d2ff38225b68105.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a7796: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-105/+32
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 496 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/81f3586749bb1117c5636e9a9663d25e77cbe158.1649865241.git.geert+renesas@glider.be
2022-05-05pinctrl: renesas: r8a77965: Optimize fixed-width reserved fieldsGeert Uytterhoeven1-105/+32
Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 496 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2aff2f4c1ed6d834370ce6dd9379c8c93bfc0a92.1649865241.git.geert+renesas@glider.be
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