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path: root/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
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2017-01-21scsi: hisi_sas: decrease running_req in hisi_sas_slot_task_free()Xiang Chen1-2/+0
There is an issue that hisi_sas_dev.running_req is not decremented properly for internal abort and TMF. To resolve, only decrease running_req in hisi_sas_slot_task_free() Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-01-21scsi: hisi_sas: fix probe ordering problemXiang Chen1-6/+2
There is a potential probe issue in how we trigger the hw initialisation. Although we use 1s timer to delay hw initialisation, there is still a potential that sas_register_ha() is not be finished before we start the PHY init from hw->hw_init(). To avoid this issue, initialise the hw after sas_register_ha() in the same probe context. Note: it is not necessary to use 1s timer now (modified v2 hw only). Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-01-21scsi: hisi_sas: modify hard reset for directed-attached diskXiang Chen1-0/+10
Correctly set registers in v2 for root PHY hardreset for directly attached disk. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-01-21scsi: hisi_sas: modify some values of ITCT tableXiang Chen1-4/+10
Set SMP connection timeout and continue AWT timer; Clear ITCT table when dev gone. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-01-21scsi: hisi_sas: workaround v2 hw SATA IO timeout issueXiang Chen1-1/+74
The v2 SAS controller needs more time to detect channel idle and send setup link request than SATA disk does, so it is difficult for the SAS controller to setup an STP link. Therefore it may cause some IO timeouts. We need to periodically configure the SAS controller so it doesn't receive STP setup requests from SATA disks for a while, so IO can be sent during this period. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-01-06scsi: hisi_sas: lock sensitive regions when servicing CQ interruptJohn Garry1-0/+2
There is a bug in the current driver in that certain hisi_hba and port structure elements which we access when servicing the CQ interrupt do not use thread-safe accesses; these include hisi_sas_port linked-list of active slots (hisi_sas_port.entry), bitmap of currently allocated IPTT (in hisi_hba.slot_index_tags), and completion queue read pointer. As a solution, lock these elements with the hisi_hba.lock. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-01-06scsi: hisi_sas: service v2 hw CQ ISR with taskletJohn Garry1-6/+18
Currently the all the slot processing for the completion queue is done in ISR context. It is judged that the slot processing can take a long time, especially when a SATA NCQ completes (upto 32 slots). So, as a solution, defer the bulk of the ISR processing to tasklet context. Each CQ will have its down tasklet. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-12-08scsi: hisi_sas: support deferred probe for v2 hwJohn Garry1-0/+12
In the hip06 and hip07 SoCs, the interrupt lines from the SAS controllers are connected to mbigen hw module [1]. The mbigen module is probed with module_init, and, as such, is not guaranteed to probe before the SAS driver. So we need to support deferred probe. We check for probe deferral in the hw layer probe, so we not probe into the main layer and allocate shost, memories, etc., to later learn that we need to defer the probe. [1] ./Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-29scsi: hisi_sas: shift vs compare typosDan Carpenter1-6/+6
There are some typos where we intended "<<" but have "<". Seems likely to cause a bunch of problems. Fixes: d3b688d3c69d ("scsi: hisi_sas: add v2 hw support for ECC and AXI bus fatal error") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: John Garry <john.garry@huawei.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: add PHY set linkrate support for v1 and v2 hwXiang Chen1-0/+45
Add the function to set PHY min and max linkrate through sysfs interface. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: use atomic64_t for hisi_sas_device.running_reqJohn Garry1-2/+2
Sometimes the value of hisi_sas_device.running_req would go negative unless we have the check for running_req >= 0 before trying to decrement. This is because using running_req is not thread-safe. As such, the value for running_req may be actually incorrect, so use atomic64_t instead. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: check SATA FIS when directly attaching SATA deviceXiang Chen1-0/+10
Check ERR bit of status to decide whether there is something wrong with initial register-D2H FIS. If error exists, PHY reset the channel to restart OOB. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: modify some values in get_ata_protocol()Xiang Chen1-2/+12
Modify and add some SATA commands according to SATA protocol. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: delete repeated configuration in free_device_v2_hw()Xiang Chen1-2/+0
Delete repeated configuration items for hisi_sas_device() when we free a device. These items are now only set in hisi_sas_dev_gone(). Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: only process broadcast change in phy_bcast_v2_hw()Xiang Chen1-1/+7
There are many BROADCAST primitives generated by the host. We are only interested in BROADCAST (CHANGE) primitives currently, so only process this. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: alloc queue id of slot according to device idXiang Chen1-17/+12
Currently slots are allocated from queues in a round-robin fashion. This causes a problem for internal commands in device mode. For this mode, we should ensure that the internal abort command is the last command seen in the host for that device. We can only ensure this when we place the internal abort command after the preceding commands for device that in the same queue, as there is no order in which the host will select a queue to execute the next command. This queue restriction makes supporting scsi mq more tricky in the future, but should not be a blocker. Note: Even though v1 hw does not support internal abort, the allocation method is chosen to be the same for consistency. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-25scsi: hisi_sas: add v2 hw support for ECC and AXI bus fatal errorXiang Chen1-5/+420
For ECC 1bit error, logic can recover it, so we only print a warning. For ECC multi-bit and AXI bus fatal error, we panic. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-09scsi: hisi_sas: Add v2 hw support for different refclkJohn Garry1-1/+3
The hip06 D03 and hip07 D05 boards have different reference clock frequencies for the SAS controller. Register PHY_CTRL needs to be programmed differently according to this frequency, so add support for this. The default register setting in PHY_CTRL is for 50MHz, so only update this register when the refclk frequency is 66MHz. For ACPI we expect the _RST handler to set the correct value for PHY_CTRL (we're forced to take different approach for DT and ACPI as ACPI does not support fixed-clock device). Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-11-09scsi: hisi_sas: Add device tree support for hip07John Garry1-0/+1
Chipset hip07 incorporates v2 hw. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: send three identify before phy upJohn Garry1-4/+16
When the v2 hw is attached with many disks through an expander, there may be OOB reset resulting in a PHY going down after the speed is negotiated (very low probability). This issue is resolved by modifying the link control registers to send three identify frames before the PHY is ready (according to 6.10.3.3.2 in SAS 3.0 spec) and close ready when the PHY is down. Signed-off-by: NengLong Zhao <zhaonenglong@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: add missing SATA pending device type to v2 hwJohn Garry1-0/+1
In setup_itct_v2_hw(), SATA device type SAS_SATA_PENDING is missing, so add it. Note: The HiSi SAS controller does not support SATA PM, so do not handle SAS_SATA_PM_PORT or SAS_SATA_PM. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: remove init_id_frame_v2_hw()John Garry1-10/+0
Function config_id_frame_v2_hw() is called twice for each PHY during initialisation, which is unneeded. So remove init_id_frame_v2_hw(), which only calls config_id_frame_v2_hw(). We will keep the call to config_id_frame_v2_hw() in start_phy_v2_hw() since it will be used for PHY reset functions. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: fix HBA SAS addr endianness for v2 hwJohn Garry1-4/+4
The endianness for the SAS address in the TX_ID_DWORD registers is set incorrectly. We see errors like this in the boot log: [ 7.583284] sas: target proto 0x0 at 50000d1108e7923f:0x1f not handled This is due to the host SAS addr not matching the PHY SAS addr in the expander host-attached phy discovery responses. To fix, we byte swap the SAS addr from BE to LE (which is the endianness of the SAS controller). Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: fix phy8 linkrate calculation in phy_up_v2_hw()John Garry1-3/+0
In function phy_up_v2_hw(), we needlessly recalculate the phy linkrate for all phys, and the calculation is incorrect for phy8, so remove this code. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: disable dlvry queues once at reset for v2 hwJohn Garry1-3/+1
The Delivery queue enable register should only be written to once at reset for v2 hw. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: keep CHL_INT2 masked for v2 HWJohn Garry1-6/+0
None of the CHL_INT2 interrupts are serviced in the channel irq ISR, so leave the interrupt source masked. The interrupt mask is initially set in init_reg_v2_hw(). Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: save delivery queue write pointerJohn Garry1-3/+6
Optimise by saving an avoidable read in the get_free_slot function. The delivery queue write pointer will only be updated by software, so don't bother re-reading what was already written in the previous call to start_delivery function. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-09-14scsi: hisi_sas: save completion queue read pointerJohn Garry1-3/+2
Optimise by saving an avoidable read in the cq interrupt. The queue read pointer will only be updated by software, so don't bother re-reading what was already written in the previous interrupt. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-08-26scsi: hisi_sas: add v2 hw slot complete internal abort supportJohn Garry1-0/+31
Add code in slot_complete_v2_hw() to deal with the slots which have completed due to internal abort. The status codes have the following meaning: - STAT_IO_ABORTED: the IO has been aborted due to internal abort, whether by device or individual abort command - STAT_IO_COMPLETE: internal abort command has completed successfully for device or individual abort command - STAT_IO_NO_DEVICE: internal abort command has completed for device but cannot find any IO - STAT_IO_NOT_VALID: internal abort command has completed for single command but could not find the command Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-08-26scsi: hisi_sas: add prep_abort_v2_hw()John Garry1-0/+33
Add function to prepare the an internal abort for v2 hw. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-07-13hisi_sas: fix the inconsistent lock issue reported by CONFIG_PROVE_LOCKINGJohn Garry1-5/+0
It is not necessary to surround call to notify_port_event(, PORTE_BROADCAST_RCVD) by spin_lock_irqsave(), so remove. This was causing a warn, as below: ================================= [ INFO: inconsistent lock state ] 4.4.8+ #12 Not tainted --------------------------------- inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. kworker/u64:1/168 [HC0[0]:SC0[0]:HE1:SE1] takes: (&(&hisi_hba->lock)->rlock){?.....}, at: [<ffffffc00052c708>] alloc_dev_quirk_v2_hw+0x48/0xec {IN-HARDIRQ-W} state was registered at: [<ffffffc0000fc764>] mark_lock+0x19c/0x6a0 [<ffffffc0000fdc14>] __lock_acquire+0xa2c/0x1d00 [<ffffffc0000ff654>] lock_acquire+0x58/0x7c [<ffffffc0008b609c>] _raw_spin_lock_irqsave+0x54/0x6c [<ffffffc00052d3c0>] int_chnl_int_v2_hw+0x1c4/0x248 [<ffffffc0001098e8>] handle_irq_event_percpu+0x9c/0x144 [<ffffffc0001099d4>] handle_irq_event+0x44/0x74 [<ffffffc00010cd68>] handle_fasteoi_irq+0xb4/0x188 [<ffffffc000108ea8>] generic_handle_irq+0x24/0x38 [<ffffffc0001091fc>] __handle_domain_irq+0x60/0xac [<ffffffc00008261c>] gic_handle_irq+0xcc/0x168 [<ffffffc0000855ac>] el1_irq+0x6c/0xe0 [<ffffffc0000f7414>] default_idle_call+0x1c/0x34 [<ffffffc0000f7654>] cpu_startup_entry+0x1d4/0x228 [<ffffffc0008aecd8>] rest_init+0x150/0x160 [<ffffffc000c4b95c>] start_kernel+0x3a4/0x3b8 [<00000000008bb000>] 0x8bb000 irq event stamp: 32661 hardirqs last enabled at (32661): [<ffffffc0008b41a8>] __mutex_unlock_slowpath+0x108/0x18c hardirqs last disabled at (32660): [<ffffffc0008b40e4>] __mutex_unlock_slowpath+0x44/0x18c softirqs last enabled at (25114): [<ffffffc0000bde68>] __do_softirq+0x210/0x27c softirqs last disabled at (25095): [<ffffffc0000be224>] irq_exit+0x9c/0xe8 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&(&hisi_hba->lock)->rlock); <Interrupt> lock(&(&hisi_hba->lock)->rlock); *** DEADLOCK *** 2 locks held by kworker/u64:1/168: #0: ("%s"shost->work_q_name){++++.+}, at: [<ffffffc0000d2980>] process_one_work+0x134/0x3cc #1: ((&sw->work)#2){+.+.+.}, at: [<ffffffc0000d2980>] process_one_work+0x134/0x3cc stack backtrace: CPU: 4 PID: 168 Comm: kworker/u64:1 Not tainted 4.4.8+ #12 Hardware name: Huawei Technologies Co., Ltd. D03/D03, BIOS 1.12 01/01/1900 Workqueue: scsi_wq_1 sas_discover_domain Call trace: [<ffffffc000089988>] dump_backtrace+0x0/0x114 [<ffffffc000089ab0>] show_stack+0x14/0x1c [<ffffffc00035ac50>] dump_stack+0xb4/0xf0 [<ffffffc0000fc524>] print_usage_bug+0x210/0x2b4 [<ffffffc0000fcbc4>] mark_lock+0x5fc/0x6a0 [<ffffffc0000fd9e8>] __lock_acquire+0x800/0x1d00 [<ffffffc0000ff654>] lock_acquire+0x58/0x7c [<ffffffc0008b5edc>] _raw_spin_lock+0x44/0x58 [<ffffffc00052c708>] alloc_dev_quirk_v2_hw+0x48/0xec [<ffffffc000528214>] hisi_sas_dev_found+0x48/0x1b8 [<ffffffc00051a9b8>] sas_notify_lldd_dev_found+0x34/0xe0 [<ffffffc00051e5e8>] sas_discover_root_expander+0x58/0x128 [<ffffffc00051b38c>] sas_discover_domain+0x4bc/0x564 [<ffffffc0000d29ec>] process_one_work+0x1a0/0x3cc [<ffffffc0000d2d50>] worker_thread+0x138/0x438 [<ffffffc0000d9494>] kthread+0xdc/0xf0 [<ffffffc000085c50>] ret_from_fork+0x10/0x40 Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-07-13hisi_sas: add v2 hw ACPI supportJohn Garry1-25/+43
Add support in v2 hw driver for ACPI. A check on whether an ACPI handle is available for the device is used to decide on whether to use ACPI reset handler or syscon for hw reset. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-09libata/libsas: Define ATA_CMD_NCQ_NON_DATAHannes Reinecke1-0/+1
Define the NCQ NON DATA command and update libsas to handle it correctly. Signed-off-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-05-09libsas: enable FPDMA SEND/RECEIVEHannes Reinecke1-0/+2
Update libsas and dependent drivers to handle FPDMA SEND/RECEIVE correctly. Signed-off-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-04-15hisi_sas: add alloc_dev_quirk_v2_hw()John Garry1-0/+30
Add custom version of function to allocate device, alloc_dev_quirk_v2_hw(). For sata devices the device id bit0 should be 0. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinicke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15hisi_sas: add slot_index_alloc_quirk_v2_hw()John Garry1-0/+28
Add v2 hw custom function slot_index_alloc_quirk_v2_hw(). SAS devices should have IPTT bit0 equal to 1. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinicke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15hisi_sas: for v2 hw only set ITCT qw2 for SAS deviceJohn Garry1-5/+6
This patch fixes the ITCT table setup as it should be configured differently for SAS and SATA devices. For SATA disks there is no need to set qw2 (already zeroed). Also, link parameters for Bus inactive limit, max connection time limit, and reject to open limit timers parameters are changed to match global config register, MAX_CON_TIME_LIMIT_TIME, as recommended by hw team. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15hisi_sas: add v2 hw support for >4 SATA physJohn Garry1-7/+10
This patch adds support for directly attaching SATA disks to phy 4-8. The problem was that only registers concerned with phy 0-3 were being considered in sata_int_v2_hw(). The issue was not detected previously as the development board only exposed phy 0-3; the new board provides access to 8 phys. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15hisi_sas: fix v2 hw multiple SATA disk issueJohn Garry1-3/+1
Intermittently it is found that when multiple SATA disks are directly connected to the host that some disks are not detected. The problem is that all set bitfields in ENT_INT_SRC1 are cleared for all phys in sata_int_v2_hw() - it should clear the set bit for the phy being serviced. Also unnecessary double-write to ENT_INT_SRC1 and ENT_INT_SRC_MSK1 is removed (remaining writes are done at end label). Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-04-15hisi_sas: use device linkrate in MCR for v2 hwJohn Garry1-1/+1
Contrary to the field name, the MCR (max connection rate) in the ITCT should hold the device linkrate (linkrate of the connected phy), and not the max linkrate. This fixes an issue seen where some SATA drives connected through an expander which would not attach. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-03-01hisi_sas: use slot abort in v2 hwJohn Garry1-3/+12
When TRANS_TX_ERR_FRAME_TXED error occurs in a slot, the command should be re-attempted. This error is equivalent to meaning that the queue is full in the sdev (and not the host). A superflous debug statement is also removed in the slot complete handler. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 tmf functionsJohn Garry1-0/+23
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 slot error handlerJohn Garry1-0/+421
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 path to send ATA commandJohn Garry1-0/+162
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 code for itct setup and freeJohn Garry1-0/+92
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 code to send smp commandJohn Garry1-0/+71
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 path to send ssp frameJohn Garry1-0/+185
Include code to prep ssp frame and deliver to hardware. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 cq interrupt handlerJohn Garry1-0/+190
Also include slot_complete_v2_hw handler Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 SATA interrupt handlerJohn Garry1-0/+100
Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-02-24hisi_sas: add v2 channel interrupt handlerJohn Garry1-0/+79
This also includes broadcast handler. Unlike v1 hw, broadcast does not have its own dedicated interrupt. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-31 01:00:09 +0300