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path: root/drivers/spi/spi-tegra114.c
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2022-04-19spi: spi-tegra114: using pm_runtime_resume_and_get instead of ↵Minghao Chi1-6/+3
pm_runtime_get_sync Using pm_runtime_resume_and_get is more appropriate for simplifing code Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220412070951.2532157-1-chi.minghao@zte.com.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-08spi: tegra114: Add missing IRQ check in tegra_spi_probeMiaoqian Lin1-0/+4
This func misses checking for platform_get_irq()'s call and may passes the negative error codes to request_threaded_irq(), which takes unsigned IRQ #, causing it to fail with -EINVAL, overriding an original error code. Stop calling request_threaded_irq() with invalid IRQ #s. Fixes: f333a331adfa ("spi/tegra114: add spi driver") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220128165238.25615-1-linmq006@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-08-05spi: modify set_cs_timing parameterMason Zhang1-4/+4
This patch modified set_cs_timing parameter, no need pass in spi_delay to set_cs_timing callback. By the way, we modified the mediatek and tegra114 spi driver to fix build err. In mediatek spi driver, We have support set absolute time not clk_count, and call this function in prepare_message not user's API. Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com> Link: https://lore.kernel.org/r/20210804133746.6742-1-Mason.Zhang@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-05-10spi: tegra114: Fix an error messageChristophe JAILLET1-2/+1
'ret' is known to be 0 here. No error code is available, so just remove it from the error message. Fixes: f333a331ad ("spi/tegra114: add spi driver") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/e2593974c9484b7055177ad0c9237c8e343946be.1620399829.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-09spi: tegra114: fix reference leak in tegra spi opsZhang Qilong1-0/+2
pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to pm_runtime_put_noidle will result in reference leak in two callers(tegra_spi_setup and tegra_spi_resume), so we should fix it. Fixes: f333a331adfac ("spi/tegra114: add spi driver") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20201103141306.5607-1-zhangqilong3@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-08spi: tegra114: Simplify with dev_err_probe()Krzysztof Kozlowski1-8/+3
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200901152713.18629-10-krzk@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2020-05-28spi: tegra114: Fix runtime PM imbalance on errorDinghao Liu1-0/+1
pm_runtime_get_sync() increments the runtime PM usage counter even when it returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Link: https://lore.kernel.org/r/20200523125704.30300-1-dinghao.liu@zju.edu.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2019-12-25spi: tegra114: use true,false for bool variablezhengbin1-2/+2
Fixes coccicheck warning: drivers/spi/spi-tegra114.c:272:2-17: WARNING: Assignment of 0/1 to bool variable drivers/spi/spi-tegra114.c:275:2-17: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Link: https://lore.kernel.org/r/1577159526-33689-4-git-send-email-zhengbin13@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-11-15spi: tegra114: Use dma_request_chan() directly for channel requestPeter Ujfalusi1-2/+1
dma_request_slave_channel_reason() is: #define dma_request_slave_channel_reason(dev, name) \ dma_request_chan(dev, name) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20191113094256.1108-9-peter.ujfalusi@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-15spi: tegra114: change format for `spi_set_cs_timing()` functionAlexandru Ardelean1-2/+20
The initial version of `spi_set_cs_timing()` was implemented with consideration only for clock-cycles as delay. For cases like `CS setup` time, it's sometimes needed that micro-seconds (or nano-seconds) are required, or sometimes even longer delays, for cases where the device needs a little longer to start transferring that after CS is asserted. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20190926105147.7839-15-alexandru.ardelean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-10-15spi: tegra114: use `spi_transfer_delay_exec` helperAlexandru Ardelean1-14/+3
The tegra114 driver has a weird/separate `tegra_spi_transfer_delay()` function that does 2 delays: one mdelay() and one udelay(). This was introduced via commit f4fade12d506e14867a2b0a5e2f7aaf227297d8b ("spi/tegra114: Correct support for cs_change"). There doesn't seem to be a mention in that commit message to suggest a specific need/use-case for having the 2 delay calls. For the most part, udelay() should be sufficient. This change replaces it with the new `spi_transfer_delay_exec()`, which should do the same thing. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20190926105147.7839-11-alexandru.ardelean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-06-10Merge tag 'v5.2-rc4' into spi-5.3Mark Brown1-12/+1
Linux 5.2-rc4
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-23spi: tegra114: set master cleanup and also invoke it on probe errorSowjanya Komatineni1-0/+3
This patch sets master cleanup and also invokes tegra spi clean on tegra spi probe failure to release tegra spi client data. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-15spi: tegra114: add support for TX and RX trimmersSowjanya Komatineni1-2/+65
Tegra SPI master controller has programmable trimmers to adjust the data with respect to the clock. These trimmers are programmed in TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY fields of COMMAND2 register. SPI TX trimmer is to adjust the outgoing data with respect to the outgoing clock and SPI RX trimmer is to adjust the loopback clock with respect to the incoming data from the slave device. These trimmers vary based on trace lengths of the platform design for each of the slaves on the SPI bus and optimal value programmed is from the platform validation across PVT. This patch adds support for configuring TX and RX clock delay trimmers through the device tree properties. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-15spi: tegra114: add support for HW CS timingSowjanya Komatineni1-2/+46
This patch implements set_cs_timing SPI controller method to allow SPI client driver to configure device specific SPI CS timings. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-15spi: tegra114: add support for hw based csSowjanya Komatineni1-12/+27
Tegra SPI controller supports both HW and SW based CS control for SPI transfers. This patch adds support for HW based CS control where CS is driven to active state during the transfer and is driven inactive at the end of the transfer directly by the HW. This patch enables the use of HW based CS only for single transfers without cs_change request. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-15spi: tegra114: add support for gpio based CSSowjanya Komatineni1-0/+13
This patch adds support for GPIO based CS control through SPI core function spi_set_cs. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-02Merge branch 'spi-5.2' into spi-nextMark Brown1-7/+90
2019-05-02spi: tegra114: fix PIO transferSowjanya Komatineni1-2/+3
This patch fixes PIO mode transfer to use PIO bit in SPI_COMMAND1 register. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-08spi: tegra114: add support for interrupt maskSowjanya Komatineni1-5/+48
This patch creates tegra_spi_soc_data structure to maintain and implement SPI HW feature differences between different Tegra chips and also creates a separate compatible string for T124/T210. Tegra210 and later has a separate interrupt mask register SPI_INTR_MASK for enabling or disabling interrupts while Tegra124 and prior uses interrupt enable bits in SPI_DMA_CTL register. This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to identify this and implements accordingly. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-08spi: tegra114: add 3 wire transfer mode supportSowjanya Komatineni1-1/+6
This patch adds 3 wire transfer support to SPI mode list along with its implementation. 3 wire or Bi-directional mode uses only one serial data pin for the transfer. SPI in master mode uses MOSI data line only and MISO data line is not used. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-08spi: tegra114: add dual mode supportSowjanya Komatineni1-1/+7
This patch adds support for dual mode SPI transfer. Dual mode uses both MOSI and MISO lines in parallel where the data is interleaved on MOSI and MISO lines increasing the throughput. Packet from Tx FIFO is transmitted on both MOSI and MISO lines and packet to Rx FIFO is received from both MOSI and MISO lines. Even bits are transmitted or received on the MOSI data line and odd bits are transmitted or received on the MISO data line. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-05spi: tegra114: set bus number based on idSowjanya Komatineni1-0/+4
This patch sets SPI device id from the device tree as the bus number. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-05spi: tegra114: use unpacked mode for below 4 bytesSowjanya Komatineni1-1/+2
Packed mode expects minimum transfer length of 4 bytes. This patch fixes this by using unpacked mode for transfers less than 4 bytes. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-05spi: tegra114: set supported bits per wordSowjanya Komatineni1-0/+1
Tegra SPI supports 4 through 32 bits per word. This patch sets bits_per_word_mask accordingly to support transfer with these bits per word. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-05spi: tegra114: dump SPI registers during timeoutSowjanya Komatineni1-0/+18
This patch dumps SPI registers on transfer error or timeout for debug purpose. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-05Merge branch 'spi-5.1' into spi-5.2Mark Brown1-62/+146
2019-04-05spi: tegra114: avoid reset call in atomic contextSowjanya Komatineni1-4/+5
This patch moves SPI controller reset out of spin lock. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-05spi: tegra114: de-assert CS before SPI mode changeSowjanya Komatineni1-6/+16
With SW CS, during the transfer completion CS is de-asserted by writing default command1 register value to SPI_COMMAND1 register. With this both mode and CS state are set at the same time and if current transfer mode is different to default SPI mode and if mode change happens prior to CS de-assert, clock polarity can change while CS is active before transfer finishes. This causes Slave to see spurious clock edges resulting in data mismatch. This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to its default value so through out the transfer it will be in same SPI mode. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: add SPI_LSB_FIRST supportSowjanya Komatineni1-1/+6
Tegra SPI controller supports lsb first mode. Default is MSB bit first and on selection of SPI_LSB_FIRST through SPI mode transmission happens with LSB bit first. This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it on request. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: use packed mode for 32 bits per wordSowjanya Komatineni1-1/+1
Fixes: Use packed mode for 32 bits per word transfers to increase performance as each packet is a full 32-bit word. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: reset controller on probeSowjanya Komatineni1-14/+18
Fixes: SPI driver can be built as module so perform SPI controller reset on probe to make sure it is in valid state before initiating transfer. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: configure dma burst size to fifo trig levelSowjanya Komatineni1-22/+30
Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels to avoid mismatch. SPI FIFO trigger levels are calculated based on the transfer length. So this patch moves DMA slave configuration to happen before start of DMAs. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: flush fifosSowjanya Komatineni1-9/+30
Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO overflow or underrun errors. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: terminate dma and reset on transfer timeoutSowjanya Komatineni1-0/+9
Fixes: terminate DMA and perform controller reset on transfer timeout to clear the FIFO's and errors. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: fix for unpacked mode transfersSowjanya Komatineni1-7/+36
Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked mode when transfer length is not a multiple of requested bits per word. unpacked mode transfers fails when the transfer includes partial bytes in the last word. Total words to be written/read to/from FIFO is computed based on transfer length and bits per word. Unpacked mode includes 0 padding bytes for partial words to align with bits per word and these extra bytes are also accounted for calculating bytes left to transfer in the current driver. This causes extra bytes access of tx/rx buffers along with buffer index position crossing actual length where remain_len becomes negative and due to unsigned type, negative value is a 32 bit representation of signed value and transferred bytes never meets the actual transfer length resulting in transfer timeout and a hang. This patch fixes this with proper computation of the actual bytes to fill in FIFO during transmit and the actual bytes to read from FIFO during receive ignoring 0 padded bytes. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-04-01spi: tegra114: clear packed bit for unpacked modeSowjanya Komatineni1-0/+2
Fixes: Clear packed bit when not using packed mode. Packed bit is not cleared when not using packed mode. This results in transfer timeouts for the unpacked mode transfers followed by the packed mode transfers. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-10-09spi: tegra114: correct register name in definitionRalf Ramsauer1-3/+3
According to "Tegra K1 Processor Technical Reference Manual" (p. 2448), bit 20 of SPI_COMMAND1 is called CS_SW_VAL and not CS_SS_VAL. Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-07-19spi: tegra114: explicitly request exclusive reset controlPhilipp Zabel1-1/+1
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Mark Brown <broonie@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-spi@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-04-24spi: tegra: fix spelling mistake: "trasfer" -> "transfer"Colin Ian King1-1/+1
trivial fix to spelling mistake in dbg_err messages Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-10-20spi: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-09-03spi: tegra114: Fix checkpatch issueJingoo Han1-0/+9
Fix the following checkpatch warnings. WARNING: Missing a blank line after declarations Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-05-07spi: tegra114: Make of_device_id array constJingoo Han1-1/+1
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-03-30Merge remote-tracking branches 'spi/topic/sunxi', 'spi/topic/tegra114', ↵Mark Brown1-2/+2
'spi/topic/ti-qspi', 'spi/topic/ti-ssp', 'spi/topic/topcliff-pch', 'spi/topic/txx9', 'spi/topic/xcomm' and 'spi/topic/xfer' into spi-next
2014-03-30Merge remote-tracking branches 'spi/topic/imx', 'spi/topic/init', ↵Mark Brown1-1/+0
'spi/topic/mpc512x-psc', 'spi/topic/mpc52xx', 'spi/topic/mxs', 'spi/topic/nuc900', 'spi/topic/oc-tiny' and 'spi/topic/octeon' into spi-next
2014-03-30Merge remote-tracking branches 'spi/topic/bus-num', 'spi/topic/cleanup', ↵Mark Brown1-19/+3
'spi/topic/clps711x', 'spi/topic/coldfire', 'spi/topic/completion' and 'spi/topic/davinci' into spi-next
2014-02-16spi: Remove explictly set bus_num and num_chipselect to default settingAxel Lin1-1/+0
The purpose of commit 1e8a52e18cfb "spi: By default setup spi_masters with 1 chipselect and dynamics bus number" is to avoid setting default value for bus_num and num_chipselect in spi master drivers. So let's remove the duplicate code. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-By: David Daney <david.daney@cavium.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-12spi: Remove duplicate code to check chip_selectAxel Lin1-2/+0
In spi_add_device(), we have the code to validate spi->chip_select. So remove the duplicate code in various drivers. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-11spi: tegra114: Convert to use master->max_speed_hzAxel Lin1-16/+3
Use master->max_speed_hz instead of tspi->spi_max_frequency, so spi core will handle checking transfer speed. In additional, since commit 052eb2d49006 'spi: core: Set max_speed_hz of spi_device default to max_speed_hz of controller', spi core will also set default spi->max_speed_hz if it is not set. So remove the duplicate code in tegra_spi_setup. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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