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2019-07-26spi: fix ctrl->num_chipselect constraintTudor Ambarus1-5/+7
[ Upstream commit f9481b08220d7dc1ff21e296a330ee8b721b44e4 ] at91sam9g25ek showed the following error at probe: atmel_spi f0000000.spi: Using dma0chan2 (tx) and dma0chan3 (rx) for DMA transfers atmel_spi: probe of f0000000.spi failed with error -22 Commit 0a919ae49223 ("spi: Don't call spi_get_gpio_descs() before device name is set") moved the calling of spi_get_gpio_descs() after ctrl->dev is set, but didn't move the !ctrl->num_chipselect check. When there are chip selects in the device tree, the spi-atmel driver lets the SPI core discover them when registering the SPI master. The ctrl->num_chipselect is thus expected to be set by spi_get_gpio_descs(). Move the !ctlr->num_chipselect after spi_get_gpio_descs() as it was before the aforementioned commit. While touching this block, get rid of the explicit comparison with 0 and update the commenting style. Fixes: 0a919ae49223 ("spi: Don't call spi_get_gpio_descs() before device name is set") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-07-26spi: rockchip: turn down tx dma burstsEmil Renner Berthing1-2/+2
[ Upstream commit 47300728fb213486a830565d2af49da967c9d16a ] This fixes tx and bi-directional dma transfers on rk3399-gru-kevin. It seems the SPI fifo must have room for 2 bursts when the dma_tx_req signal is generated or it might skip some words. This in turn makes the rx dma channel never complete for bi-directional transfers. Fix it by setting tx burst length to fifo_len / 4 and the dma watermark to fifo_len / 2. However the rk3399 TRM says (sic): "DMAC support incrementing-address burst and fixed-address burst. But in the case of access SPI and UART at byte or halfword size, DMAC only support fixed-address burst and the address must be aligned to word." So this relies on fifo_len being a multiple of 16 such that the burst length (= fifo_len / 4) is a multiple of 4 and the addresses will be word-aligned. Fixes: dcfc861d24ec ("spi: rockchip: adjust dma watermark and burstlen") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-07-10spi: bitbang: Fix NULL pointer dereference in spi_unregister_masterYueHaibing1-1/+1
[ Upstream commit 5caaf29af5ca82d5da8bc1d0ad07d9e664ccf1d8 ] If spi_register_master fails in spi_bitbang_start because device_add failure, We should return the error code other than 0, otherwise calling spi_bitbang_stop may trigger NULL pointer dereference like this: BUG: KASAN: null-ptr-deref in __list_del_entry_valid+0x45/0xd0 Read of size 8 at addr 0000000000000000 by task syz-executor.0/3661 CPU: 0 PID: 3661 Comm: syz-executor.0 Not tainted 5.1.0+ #28 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.10.2-1ubuntu1 04/01/2014 Call Trace: dump_stack+0xa9/0x10e ? __list_del_entry_valid+0x45/0xd0 ? __list_del_entry_valid+0x45/0xd0 __kasan_report+0x171/0x18d ? __list_del_entry_valid+0x45/0xd0 kasan_report+0xe/0x20 __list_del_entry_valid+0x45/0xd0 spi_unregister_controller+0x99/0x1b0 spi_lm70llp_attach+0x3ae/0x4b0 [spi_lm70llp] ? 0xffffffffc1128000 ? klist_next+0x131/0x1e0 ? driver_detach+0x40/0x40 [parport] port_check+0x3b/0x50 [parport] bus_for_each_dev+0x115/0x180 ? subsys_dev_iter_exit+0x20/0x20 __parport_register_driver+0x1f0/0x210 [parport] ? 0xffffffffc1150000 do_one_initcall+0xb9/0x3b5 ? perf_trace_initcall_level+0x270/0x270 ? kasan_unpoison_shadow+0x30/0x40 ? kasan_unpoison_shadow+0x30/0x40 do_init_module+0xe0/0x330 load_module+0x38eb/0x4270 ? module_frob_arch_sections+0x20/0x20 ? kernel_read_file+0x188/0x3f0 ? find_held_lock+0x6d/0xd0 ? fput_many+0x1a/0xe0 ? __do_sys_finit_module+0x162/0x190 __do_sys_finit_module+0x162/0x190 ? __ia32_sys_init_module+0x40/0x40 ? __mutex_unlock_slowpath+0xb4/0x3f0 ? wait_for_completion+0x240/0x240 ? vfs_write+0x160/0x2a0 ? lockdep_hardirqs_off+0xb5/0x100 ? mark_held_locks+0x1a/0x90 ? do_syscall_64+0x14/0x2a0 do_syscall_64+0x72/0x2a0 entry_SYSCALL_64_after_hwframe+0x49/0xbe Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 702a4879ec33 ("spi: bitbang: Let spi_bitbang_start() take a reference to master") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-06-15dmaengine: idma64: Use actual device for DMA transfersAndy Shevchenko1-6/+1
[ Upstream commit 5ba846b1ee0792f5a596b9b0b86d6e8cdebfab06 ] Intel IOMMU, when enabled, tries to find the domain of the device, assuming it's a PCI one, during DMA operations, such as mapping or unmapping. Since we are splitting the actual PCI device to couple of children via MFD framework (see drivers/mfd/intel-lpss.c for details), the DMA device appears to be a platform one, and thus not an actual one that performs DMA. In a such situation IOMMU can't find or allocate a proper domain for its operations. As a result, all DMA operations are failed. In order to fix this, supply parent of the platform device to the DMA engine framework and fix filter functions accordingly. We may rely on the fact that parent is a real PCI device, because no other configuration is present in the wild. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [for tty parts] Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: Fix zero length xfer bugChris Lesiak1-0/+2
[ Upstream commit 5442dcaa0d90fc376bdfc179a018931a8f43dea4 ] This fixes a bug for messages containing both zero length and unidirectional xfers. The function spi_map_msg will allocate dummy tx and/or rx buffers for use with unidirectional transfers when the hardware can only do a bidirectional transfer. That dummy buffer will be used in place of a NULL buffer even when the xfer length is 0. Then in the function __spi_map_msg, if he hardware can dma, the zero length xfer will have spi_map_buf called on the dummy buffer. Eventually, __sg_alloc_table is called and returns -EINVAL because nents == 0. This fix prevents the error by not using the dummy buffer when the xfer length is zero. Signed-off-by: Chris Lesiak <chris.lesiak@licor.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: imx: stop buffer overflow in RX FIFO flushTrent Piepho1-1/+1
[ Upstream commit c842749ea1d32513f9e603c074d60d7aa07cb2ef ] Commit 71abd29057cb ("spi: imx: Add support for SPI Slave mode") added an RX FIFO flush before start of a transfer. In slave mode, the master may have sent more data than expected and this data will still be in the RX FIFO at the start of the next transfer, and so needs to be flushed. However, the code to do the flush was accidentally saving this data into the previous transfer's RX buffer, clobbering the contents of whatever followed that buffer. Change it to empty the FIFO and throw away the data. Every one of the RX functions for the different eCSPI versions and modes reads the RX FIFO data using the same readl() call, so just use that, rather than using the spi_imx->rx function pointer and making sure all the different rx functions have a working "throw away" mode. There is another issue, which affects master mode when switching from DMA to PIO. There can be extra data in the RX FIFO which triggers this flush code, causing memory corruption in the same manner. I don't know why this data is unexpectedly in the FIFO. It's likely there is a different bug or erratum responsible for that. But regardless of that, I think this is proper fix the for bug at hand here. Fixes: 71abd29057cb ("spi: imx: Add support for SPI Slave mode") Cc: Jiada Wang <jiada_wang@mentor.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: rspi: Fix sequencer reset during initializationGeert Uytterhoeven1-3/+6
[ Upstream commit 26843bb128590edd7eba1ad7ce22e4b9f1066ce3 ] While the sequencer is reset after each SPI message since commit 880c6d114fd79a69 ("spi: rspi: Add support for Quad and Dual SPI Transfers on QSPI"), it was never reset for the first message, thus relying on reset state or bootloader settings. Fix this by initializing it explicitly during configuration. Fixes: 0b2182ddac4b8837 ("spi: add support for Renesas RSPI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi : spi-topcliff-pch: Fix to handle empty DMA buffersAditya Pakki1-2/+13
[ Upstream commit f37d8e67f39e6d3eaf4cc5471e8a3d21209843c6 ] pch_alloc_dma_buf allocated tx, rx DMA buffers which can fail. Further, these buffers are used without a check. The patch checks for these failures and sends the error upstream. Signed-off-by: Aditya Pakki <pakki001@umn.edu> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: export tracepoint symbols to modulesArnd Bergmann1-0/+2
[ Upstream commit ca1438dcb34c7fcad63b6ce14ea63a870b92a69b ] The newly added tracepoints in the spi-mxs driver cause a link error when the driver is a loadable module: ERROR: "__tracepoint_spi_transfer_stop" [drivers/spi/spi-mxs.ko] undefined! ERROR: "__tracepoint_spi_transfer_start" [drivers/spi/spi-mxs.ko] undefined! I'm not quite sure where to put the export statements, but directly after the inclusion of the header seems as good as any other place. Fixes: f3fdea3af405 ("spi: mxs: add tracing to custom .transfer_one_message callback") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: stm32-qspi: add spi_master_put in release functionLudovic Barre1-18/+28
[ Upstream commit a88eceb17ac7e8dc4ad9995681af61c8371668f4 ] This patch adds spi_master_put in release function to drop the controller's refcount. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: tegra114: reset controller on probeSowjanya Komatineni1-14/+18
[ Upstream commit 019194933339b3e9b486639c8cb3692020844d65 ] Fixes: SPI driver can be built as module so perform SPI controller reset on probe to make sure it is in valid state before initiating transfer. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: Add missing error handling for CS GPIOsGeert Uytterhoeven1-0/+2
[ Upstream commit 1723fdec5fcbc4de3d26bbb23a9e1704ee258955 ] While devm_gpiod_get_index_optional() returns NULL if the GPIO is not present (i.e. -ENOENT), it may still return other error codes, like -EPROBE_DEFER. Currently these are not handled, leading to unrecoverable failures later in case of probe deferral: gpiod_set_consumer_name: invalid GPIO (errorpointer) gpiod_direction_output: invalid GPIO (errorpointer) gpiod_set_value_cansleep: invalid GPIO (errorpointer) gpiod_set_value_cansleep: invalid GPIO (errorpointer) gpiod_set_value_cansleep: invalid GPIO (errorpointer) Detect and propagate errors to fix this. Fixes: f3186dd876697e69 ("spi: Optionally use GPIO descriptors for CS GPIOs") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: Don't call spi_get_gpio_descs() before device name is setAndrey Smirnov1-18/+19
[ Upstream commit 0a919ae49223d32ac0e8be3494547fcd1e4aa0aa ] Move code calling spi_get_gpio_descs() to happen after ctlr->dev's name is set in order to have proper GPIO consumer names. Before: cat /sys/kernel/debug/gpio gpiochip0: GPIOs 0-31, parent: platform/40049000.gpio, vf610-gpio: gpio-6 ( |regulator-usb0-vbus ) out lo gpiochip1: GPIOs 32-63, parent: platform/4004a000.gpio, vf610-gpio: gpio-36 ( |scl ) in hi gpio-37 ( |sda ) in hi gpio-40 ( |(null) CS1 ) out lo gpio-41 ( |(null) CS0 ) out lo ACTIVE LOW gpio-42 ( |miso ) in hi gpio-43 ( |mosi ) in lo gpio-44 ( |sck ) out lo After: cat /sys/kernel/debug/gpio gpiochip0: GPIOs 0-31, parent: platform/40049000.gpio, vf610-gpio: gpio-6 ( |regulator-usb0-vbus ) out lo gpiochip1: GPIOs 32-63, parent: platform/4004a000.gpio, vf610-gpio: gpio-36 ( |scl ) in hi gpio-37 ( |sda ) in hi gpio-40 ( |spi0 CS1 ) out lo gpio-41 ( |spi0 CS0 ) out lo ACTIVE LOW gpio-42 ( |miso ) in hi gpio-43 ( |mosi ) in lo gpio-44 ( |sck ) out lo Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Mark Brown <broonie@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: linux-spi@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: pxa2xx: fix SCR (divisor) calculationFlavio Suligoi1-2/+6
[ Upstream commit 29f2133717c527f492933b0622a4aafe0b3cbe9e ] Calculate the divisor for the SCR (Serial Clock Rate), avoiding that the SSP transmission rate can be greater than the device rate. When the division between the SSP clock and the device rate generates a reminder, we have to increment by one the divisor. In this way the resulting SSP clock will never be greater than the device SPI max frequency. For example, with: - ssp_clk = 50 MHz - dev freq = 15 MHz without this patch the SSP clock will be greater than 15 MHz: - 25 MHz for PXA25x_SSP and CE4100_SSP - 16,56 MHz for the others Instead, with this patch, we have in both case an SSP clock of 12.5MHz, so the max rate of the SPI device clock is respected. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-31spi: atmel-quadspi: fix crash while suspendingClaudiu Beznea1-2/+4
[ Upstream commit e5c27498a0403b270620b1a8a0a66e3efc222fb6 ] atmel_qspi objects are kept in spi_controller objects, so, first get pointer to spi_controller object and then get atmel_qspi object from spi_controller object. Fixes: 2d30ac5ed633 ("mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-03-10Merge tag 'pci-v5.1-changes' of ↵Linus Torvalds1-1/+0
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - Use match_string() instead of reimplementing it (Andy Shevchenko) - Enable SERR# forwarding for all bridges (Bharat Kumar Gogada) - Use Latency Tolerance Reporting if already enabled by platform (Bjorn Helgaas) - Save/restore LTR info for suspend/resume (Bjorn Helgaas) - Fix DPC use of uninitialized data (Dongdong Liu) - Probe bridge window attributes only once at enumeration-time to fix device accesses during rescan (Bjorn Helgaas) - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du Changbin) - Use config header type (not class code) identify bridges more reliably (Honghui Zhang) - Work around Intel Denverton incorrect Trace Hub BAR size reporting (Alexander Shishkin) - Reorder pciehp cached state/hardware state updates to avoid missed interrupts (Mika Westerberg) - Turn ibmphp semaphores into completions or mutexes (Arnd Bergmann) - Mark expected switch fall-through (Mathieu Malaterre) - Use of_node_name_eq() for node name comparisons (Rob Herring) - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang) - Consolidate Rohm Vendor ID definitions (Andy Shevchenko) - Use u32 (not __u32) for things not exposed to userspace (Logan Gunthorpe) - Fix locking semantics of bus and slot reset interfaces (Alex Williamson) - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang) - Allow portdrv to claim subtractive decode Ports so PCIe services will work for them (Honghui Zhang) - Report PCIe links that become degraded at run-time (Alexandru Gagniuc) - Blacklist Gigabyte X299 Root Port power management to fix Thunderbolt hotplug (Mika Westerberg) - Revert runtime PM suspend/resume callbacks that broke PME on network cable plug (Mika Westerberg) - Disable Data Link State Changed interrupts to prevent wakeup immediately after suspend (Mika Westerberg) - Extend altera to support Stratix 10 (Ley Foon Tan) - Allow building altera driver on ARM64 (Ley Foon Tan) - Replace Douglas with Tom Joseph as Cadence PCI host/endpoint maintainer (Lorenzo Pieralisi) - Add DT support for R-Car RZ/G2E (R8A774C0) (Fabrizio Castro) - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I) - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay Abraham I) - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I) - Simplify dwc (remove unnecessary header includes, name variables consistently, reduce inverted logic, etc) (Gustavo Pimentel) - Add i.MX8MQ support (Andrey Smirnov) - Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel) - Work around imx7d PCIe PLL erratum (Trent Piepho) - Don't assert qcom reset GPIO during probe (Bjorn Andersson) - Skip dwc MSI init if MSIs have been disabled (Lucas Stach) - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya Nakamura) - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of open-coded reimplementation (Maya Nakamura) - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura) - Fix mediatek MMIO size computation to enable full size of available MMIO space (Honghui Zhang) - Fix mediatek DMA window size computation to allow endpoint DMA access to full DRAM address range (Honghui Zhang) - Fix mvebu prefetchable BAR regression caused by common bridge emulation that assumed all bridges had prefetchable windows (Thomas Petazzoni) - Make advk_pci_bridge_emul_ops static (Wei Yongjun) - Configure MPS settings for VMD root ports (Jon Derrick) * tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (92 commits) PCI: Update PCIEPORTBUS Kconfig help text PCI: Fix "try" semantics of bus and slot reset PCI/LINK: Report degraded links via link bandwidth notification dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 PCI: altera: Enable driver on ARM64 PCI: altera: Add Stratix 10 PCIe support PCI/PME: Fix possible use-after-free on remove PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static PCI: dwc: skip MSI init if MSIs have been explicitly disabled PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset() PCI: hv: Replace hv_vp_set with hv_vpset PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM PCI: mediatek: Fix memory mapped IO range size computation PCI: dwc: Remove superfluous shifting in definitions PCI: dwc: Make use of GENMASK/FIELD_PREP PCI: dwc: Make use of BIT() in constant definitions PCI: dwc: Share code for dw_pcie_rd/wr_other_conf() PCI: dwc: Make use of IS_ALIGNED() PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ ...
2019-03-04Merge branch 'spi-5.1' into spi-nextMark Brown30-1141/+4799
2019-03-04Merge branch 'spi-5.0' into spi-linusMark Brown11-76/+91
2019-03-04spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3Geert Uytterhoeven1-1/+7
While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support bits-per-word values in the full range 8..32, the variants present in R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32. Obtain the value from family-specific sh_msiof_chipdata to fix this. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-22spi: sifive: Remove redundant dev_err call in sifive_spi_probe()Wei Yongjun1-1/+0
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-22spi: sifive: Remove spi_master_put in sifive_spi_remove()Wei Yongjun1-1/+0
The call to spi_master_put() in sifive_spi_remove() is redundant since the master is registered using devm_spi_register_master() and no reference hold by using spi_master_get() in sifive_spi_remove(). This is detected by Coccinelle semantic patch. Fixes: 484a9a68d669 ("spi: sifive: Add driver for the SiFive SPI controller") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-21spi: spi-gpio: fix SPI_CS_HIGH capabilityRussell King1-2/+2
spi-gpio is capable of dealing with active-high chip-selects. Unfortunately, commit 4b859db2c606 ("spi: spi-gpio: add SPI_3WIRE support") broke this by setting master->mode_bits, which overrides the setting in the spi-bitbang code. Fix this. [Fixed a trivial conflict with SPI_3WIRE_HIZ support -- broonie] Fixes: 4b859db2c606 ("spi: spi-gpio: add SPI_3WIRE support") Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2019-02-20Merge branch 'for-5.0' of ↵Mark Brown10-74/+89
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.1
2019-02-20spi: pxa2xx: Setup maximum supported DMA transfer lengthAndy Shevchenko1-0/+1
When the commit b6ced294fb61 ("spi: pxa2xx: Switch to SPI core DMA mapping functionality") switches to SPI core provided DMA helpers, it missed to setup maximum supported DMA transfer length for the controller and thus users mistakenly try to send more data than supported with the following warning: ili9341 spi-PRP0001:01: DMA disabled for transfer length 153600 greater than 65536 Setup maximum supported DMA transfer length in order to make users know the limit. Fixes: b6ced294fb61 ("spi: pxa2xx: Switch to SPI core DMA mapping functionality") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
2019-02-19spi: sifive: Add driver for the SiFive SPI controllerYash Shah3-0/+457
Add driver for the SiFive SPI controller on the HiFive Unleashed board. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-13spi: sprd: Add a prefix for SPI DMA channel macrosBaolin Wang1-21/+21
Add a prefix for SPI DMA channel macros to avoid namespace conflicts, and no functional changes. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-13spi: sprd: spi: sprd: Add DMA mode supportLanqing Liu1-3/+290
Add DMA mode support for the Spreadtrum SPI controller, and we will enable SPI interrupt to help to complete the SPI transfer work in DMA mode. Signed-off-by: Lanqing Liu <lanqing.liu@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-13spi: sprd: Add the SPI irq function for the SPI DMA modeLanqing Liu1-0/+51
The SPI irq event will use to complete the SPI work in the SPI DMA mode, so this patch is a preparation for the following DMA mode support. Moreover the SPI interrupt can be fired when removing the SPI controller, so we should make sure the SPI controller has stopped the queue in remove function before freeing the SPI irq. Signed-off-by: Lanqing Liu <lanqing.liu@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-12spi: use gpio[d]_set_value_cansleep for setting chipselect GPIOFelix Fietkau1-2/+3
Sleeping is safe inside spi_transfer_one_message, and some GPIO chips are running on slow busses (such as I2C GPIO expanders) and need to sleep for setting values. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-12spi: gpio: Advertise support for SPI_CS_HIGHJonathan Neuschäfer1-1/+2
The spi-gpio driver already handles different chip select polarities, but so far this was not advertised in master->mode_bits. This patch fixes mmc_spi on top of spi_gpio, which is useful in some testing scenarios. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-08spi: sh-msiof: Replace spi_master by spi_controllerGeert Uytterhoeven1-85/+83
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-08spi: sh-hspi: Replace spi_master by spi_controllerGeert Uytterhoeven1-18/+18
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-08spi: rspi: Replace spi_master by spi_controllerGeert Uytterhoeven1-85/+85
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: add support for sam9x60 qspi controllerTudor Ambarus1-35/+128
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. It uses different transfer type bits in IFR register. It has dedicated registers to specify a read or a write instruction: Read Instruction Code Register (RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have identical fields. Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: add support for named peripheral clockTudor Ambarus1-15/+18
Naming clocks is a good practice. Keep supporting unnamed peripheral clock, to be backward compatible with old DTs. While here, rename clk to pclk, to indicate that it is a peripheral clock. Suggested-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: rework transfer macrosTudor Ambarus1-9/+4
Split the TFRTYP_TRSFR_ bitfields in 2: one bit encoding the mem/reg transfer type and one bit encoding the direction of the transfer (read/write). Remove NOP when setting read transfer type. Remove useless setting of write transfer type when op->data.dir == SPI_MEM_DATA_IN && !op->data.nbytes. QSPI_IFR_TFRTYP_TRSFR_WRITE is specific just to sama5d2 qspi, rename it to QSPI_IFR_SAMA5D2_WRITE_TRSFR. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: switch to SPDX license identifiersTudor Ambarus1-12/+1
Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: return appropriate error codeTudor Ambarus1-2/+2
Return -ENOTSUPP when atmel_qspi_find_mode() fails. Propagate the error in atmel_qspi_exec_op(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: remove unnecessary castTudor Ambarus1-1/+1
The cast is done implicitly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: fix naming schemeTudor Ambarus1-8/+8
Let general names to core drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: drop wrappers for iomem accessesTudor Ambarus1-28/+17
The wrappers hid that the accesses are relaxed. Drop them. Suggested-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: order header files inclusion alphabeticallyTudor Ambarus1-5/+4
Cosmetic change, no functional change. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: cache MR value to avoid a write accessTudor Ambarus1-1/+13
Set the controller by default in Serial Memory Mode (SMM) at probe. Cache Mode Register (MR) value to avoid write access when setting the controller in serial memory mode at exec_op(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: spi-fsl-dspi: Provide support for DSPI slave mode operation (Vybryd vf610)Lukasz Majewski1-10/+30
The NXP's Vybryd vf610 can work as a SPI slave device (the CS and clock signals are provided by master). It is possible to specify a single device to work in that mode. As we do use DMA for transferring data, the RX channel must be prepared for incoming data. Moreover, in slave mode we just set a subset of control fields in configuration registers (CTAR0, PUSHR). For testing the spidev_test program has been used. Test script for this patch can be found here: https://github.com/lmajewski/tests-spi/blob/master/tests/spi/spi_tests.sh Signed-off-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-02PCI: Move Rohm Vendor ID to generic listAndy Shevchenko1-1/+0
Move the Rohm Vendor ID to pci_ids.h instead of defining it in several drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2019-01-31spi-atmel: support inter-word delayJonas Bonn1-5/+6
If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly. Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board). Signed-off-by: Jonas Bonn <jonas@norrbonn.se> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-31spi: support inter-word delay requirement for devicesJonas Bonn1-0/+5
Some devices are slow and cannot keep up with the SPI bus and therefore require a short delay between words of the SPI transfer. The example of this that I'm looking at is a SAMA5D2 with a minimum SPI clock of 400kHz talking to an AVR-based SPI slave. The AVR cannot put bytes on the bus fast enough to keep up with the SoC's SPI controller even at the lowest bus speed. This patch introduces the ability to specify a required inter-word delay for SPI devices. It is up to the controller driver to configure itself accordingly in order to introduce the requested delay. Note that, for spi_transfer, there is already a field word_delay that provides similar functionality. This field, however, is specified in clock cycles (and worse, SPI controller cycles, not SCK cycles); that makes this value dependent on the master clock instead of the device clock for which the delay is intended to provide some relief. This patch leaves this old word_delay in place and provides a time-based word_delay_us alongside it; the new field fits in the struct padding so struct size is constant. There is only one in-kernel user of the word_delay field and presumably that driver could be reworked to use the time-based value instead. The time-based delay is limited to 8 bits as these delays are intended to be short. The SAMA5D2 that I've tested this on limits delays to a maximum of ~100us, which is already many word-transfer periods even at the minimum transfer speed supported by the controller. Signed-off-by: Jonas Bonn <jonas@norrbonn.se> CC: Mark Brown <broonie@kernel.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: linux-spi@vger.kernel.org CC: devicetree@vger.kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-29spi: mxs: add tracing to custom .transfer_one_message callbackUwe Kleine-König1-0/+5
Driver specific implementations for .transfer_one_message need to call the tracing stuff themself. This is necessary to make spi tracing actually useful. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-29spi: spi-mem: spi-fsl-qspi: typo fix in author nameYogesh Narayan Gaur1-2/+2
Typo fix in Author Boris Brezillon last name and update with new email address. Fixes: 84d043185dbe ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-29spi: ti-qspi: Fix mmap read when more than one CS in useVignesh R1-3/+3
Commit 4dea6c9b0b64 ("spi: spi-ti-qspi: add mmap mode read support") has has got order of parameter wrong when calling regmap_update_bits() to select CS for mmap access. Mask and value arguments are interchanged. Code will work on a system with single slave, but fails when more than one CS is in use. Fix this by correcting the order of parameters when calling regmap_update_bits(). Fixes: 4dea6c9b0b64 ("spi: spi-ti-qspi: add mmap mode read support") Cc: stable@vger.kernel.org Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-23 06:35:34 +0300