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2023-04-14Merge tag 'devicetree-fixes-for-6.2-3' of ↵Linus Torvalds1-0/+5
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree fixes from Rob Herring: - Fix interaction between fw_devlink and DT overlays causing devices to not be probed - Fix the compatible string for loongson,cpu-interrupt-controller * tag 'devicetree-fixes-for-6.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: treewide: Fix probing of devices in DT overlays dt-bindings: interrupt-controller: loongarch: Fix mismatched compatible
2023-04-11treewide: Fix probing of devices in DT overlaysGeert Uytterhoeven1-0/+5
When loading a DT overlay that creates a device, the device is not probed, unless the DT overlay is unloaded and reloaded again. After the recent refactoring to improve fw_devlink, it no longer depends on the "compatible" property to identify which device tree nodes will become struct devices. fw_devlink now picks up dangling consumers (consumers pointing to descendent device tree nodes of a device that aren't converted to child devices) when a device is successfully bound to a driver. See __fw_devlink_pickup_dangling_consumers(). However, during DT overlay, a device's device tree node can have sub-nodes added/removed without unbinding/rebinding the driver. This difference in behavior between the normal device instantiation and probing flow vs. the DT overlay flow has a bunch of implications that are pointed out elsewhere[1]. One of them is that the fw_devlink logic to pick up dangling consumers is never exercised. This patch solves the fw_devlink issue by marking all DT nodes added by DT overlays with FWNODE_FLAG_NOT_DEVICE (fwnode that won't become device), and by clearing the flag when a struct device is actually created for the DT node. This way, fw_devlink knows not to have consumers waiting on these newly added DT nodes, and to propagate the dependency to an ancestor DT node that has the corresponding struct device. Based on a patch by Saravana Kannan, which covered only platform and spi devices. [1] https://lore.kernel.org/r/CAGETcx_bkuFaLCiPrAWCPQz+w79ccDp6=9e881qmK=vx3hBMyg@mail.gmail.com Fixes: 4a032827daa89350 ("of: property: Simplify of_link_to_phandle()") Link: https://lore.kernel.org/r/CAGETcx_+rhHvaC_HJXGrr5_WAd2+k5f=rWYnkCZ6z5bGX-wj4w@mail.gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Saravana Kannan <saravanak@google.com> Tested-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Link: https://lore.kernel.org/r/e1fa546682ea4c8474ff997ab6244c5e11b6f8bc.1680182615.git.geert+renesas@glider.be Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-02Merge tag 'spi-fix-v6.3' of ↵Linus Torvalds3-7/+12
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A small set of fixes for SPI drivers, Krishna has been doing a bunch of work on Tegra210 QuadSPI and found a bunch of issues there and there's a couple of small fixes for other drivers too" * tag 'spi-fix-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: tegra210-quad: Fix iterator outside loop spi: tegra210-quad: Fix validate combined sequence spi: tegra210-quad: set half duplex flag spi: spi-sn-f-ospi: fix duplicate flag while assigning to mode_bits spi: cadence-quadspi: Fix cancel the indirect read mask
2023-02-28spi: tegra210-quad: Fix iterator outside loopKrishna Yarlagadda1-4/+8
Fix warn: iterator used outside loop: 'xfer'. 'xfer' variable contain invalid value in few conditions. Complete transfer within DATA phase in successful case and at the end for failed transfer. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link:https://lore.kernel.org/all/202210191211.46FkzKmv-lkp@intel.com/ Fixes: 8777dd9dff40 ("spi: tegra210-quad: Fix combined sequence") Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/20230227200428.45832-1-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-27Merge tag 'soc-drivers-6.3' of ↵Linus Torvalds1-7/+7
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "As usual, there are lots of minor driver changes across SoC platforms from NXP, Amlogic, AMD Zynq, Mediatek, Qualcomm, Apple and Samsung. These usually add support for additional chip variations in existing drivers, but also add features or bugfixes. The SCMI firmware subsystem gains a unified raw userspace interface through debugfs, which can be used for validation purposes. Newly added drivers include: - New power management drivers for StarFive JH7110, Allwinner D1 and Renesas RZ/V2M - A driver for Qualcomm battery and power supply status - A SoC device driver for identifying Nuvoton WPCM450 chips - A regulator coupler driver for Mediatek MT81xxv" * tag 'soc-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits) power: supply: Introduce Qualcomm PMIC GLINK power supply soc: apple: rtkit: Do not copy the reg state structure to the stack soc: sunxi: SUN20I_PPU should depend on PM memory: renesas-rpc-if: Remove redundant division of dummy soc: qcom: socinfo: Add IDs for IPQ5332 and its variant dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its variant dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1 firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/ MAINTAINERS: Update qcom CPR maintainer entry dt-bindings: firmware: document Qualcomm SM8550 SCM dt-bindings: firmware: qcom,scm: add qcom,scm-sa8775p compatible soc: qcom: socinfo: Add Soc IDs for IPQ8064 and variants dt-bindings: arm: qcom,ids: Add Soc IDs for IPQ8064 and variants soc: qcom: socinfo: Add support for new field in revision 17 soc: qcom: smd-rpm: Add IPQ9574 compatible soc: qcom: pmic_glink: remove redundant calculation of svid soc: qcom: stats: Populate all subsystem debugfs files dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes soc: qcom: pmic_glink: add CONFIG_NET/CONFIG_OF dependencies soc: qcom: pmic_glink: Introduce altmode support ...
2023-02-24Merge tag 'driver-core-6.3-rc1' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg KH: "Here is the large set of driver core changes for 6.3-rc1. There's a lot of changes this development cycle, most of the work falls into two different categories: - fw_devlink fixes and updates. This has gone through numerous review cycles and lots of review and testing by lots of different devices. Hopefully all should be good now, and Saravana will be keeping a watch for any potential regression on odd embedded systems. - driver core changes to work to make struct bus_type able to be moved into read-only memory (i.e. const) The recent work with Rust has pointed out a number of areas in the driver core where we are passing around and working with structures that really do not have to be dynamic at all, and they should be able to be read-only making things safer overall. This is the contuation of that work (started last release with kobject changes) in moving struct bus_type to be constant. We didn't quite make it for this release, but the remaining patches will be finished up for the release after this one, but the groundwork has been laid for this effort. Other than that we have in here: - debugfs memory leak fixes in some subsystems - error path cleanups and fixes for some never-able-to-be-hit codepaths. - cacheinfo rework and fixes - Other tiny fixes, full details are in the shortlog All of these have been in linux-next for a while with no reported problems" [ Geert Uytterhoeven points out that that last sentence isn't true, and that there's a pending report that has a fix that is queued up - Linus ] * tag 'driver-core-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (124 commits) debugfs: drop inline constant formatting for ERR_PTR(-ERROR) OPP: fix error checking in opp_migrate_dentry() debugfs: update comment of debugfs_rename() i3c: fix device.h kernel-doc warnings dma-mapping: no need to pass a bus_type into get_arch_dma_ops() driver core: class: move EXPORT_SYMBOL_GPL() lines to the correct place Revert "driver core: add error handling for devtmpfs_create_node()" Revert "devtmpfs: add debug info to handle()" Revert "devtmpfs: remove return value of devtmpfs_delete_node()" driver core: cpu: don't hand-override the uevent bus_type callback. devtmpfs: remove return value of devtmpfs_delete_node() devtmpfs: add debug info to handle() driver core: add error handling for devtmpfs_create_node() driver core: bus: update my copyright notice driver core: bus: add bus_get_dev_root() function driver core: bus: constify bus_unregister() driver core: bus: constify some internal functions driver core: bus: constify bus_get_kset() driver core: bus: constify bus_register/unregister_notifier() driver core: remove private pointer from struct bus_type ...
2023-02-24Merge tag 'tty-6.3-rc1' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty / serial driver updates from Greg KH: "Here is the big set of serial and tty driver updates for 6.3-rc1. Once again, Jiri and Ilpo have done a number of core vt and tty/serial layer cleanups that were much needed and appreciated. Other than that, it's just a bunch of little tty/serial driver updates: - qcom-geni-serial driver updates - liteuart driver updates - hvcs driver cleanups - n_gsm updates and additions for new features - more 8250 device support added - fpga/dfl update and additions - imx serial driver updates - fsl_lpuart updates - other tiny fixes and updates for serial drivers All of these have been in linux-next for a while with no reported problems" * tag 'tty-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (143 commits) tty: n_gsm: add keep alive support serial: imx: remove a redundant check dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties soc: qcom: geni-se: Move qcom-geni-se.h to linux/soc/qcom/geni-se.h tty: n_gsm: add TIOCMIWAIT support tty: n_gsm: add RING/CD control support tty: n_gsm: mark unusable ioctl structure fields accordingly serial: imx: get rid of registers shadowing serial: imx: refine local variables in rxint() serial: imx: stop using USR2 in FIFO reading loop serial: imx: remove redundant USR2 read from FIFO reading loop serial: imx: do not break from FIFO reading loop prematurely serial: imx: do not sysrq broken chars serial: imx: work-around for hardware RX flood serial: imx: factor-out common code to imx_uart_soft_reset() serial: 8250_pci1xxxx: Add power management functions to quad-uart driver serial: 8250_pci1xxxx: Add RS485 support to quad-uart driver serial: 8250_pci1xxxx: Add driver for quad-uart support serial: 8250_pci: Add serial8250_pci_setup_port definition in 8250_pcilib.c tty: pcn_uart: fix memory leak with using debugfs_lookup() ...
2023-02-24spi: tegra210-quad: Fix validate combined sequenceKrishna Yarlagadda1-1/+1
Check for non dma transfers that do not fit in FIFO has issue and skips combined sequence for Tegra234 & Tegra241 which does not have GPCDMA. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/20230224164034.56933-1-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-23spi: tegra210-quad: set half duplex flagKrishna Yarlagadda1-0/+1
Tegra QSPI controller only supports half duplex transfers. Set half duplex constrain flag. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/20230223162635.19747-3-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-23spi: spi-sn-f-ospi: fix duplicate flag while assigning to mode_bitsDhruva Gole1-1/+1
Replace the SPI_TX_OCTAL flag that appeared two time with SPI_RX_OCTAL in the chain of '|' operators while assigning to mode_bits Fixes: 1b74dd64c861 ("spi: Add Socionext F_OSPI SPI flash controller driver") Reported-by: David Binderman <dcb314@hotmail.com> Link: https://lore.kernel.org/all/DB6P189MB0568F3BE9384315F5C8C1A3E9CA49@DB6P189MB0568.EURP189.PROD.OUTLOOK.COM/ Cc: stable@vger.kernel.org Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230223095202.924626-1-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-23spi: cadence-quadspi: Fix cancel the indirect read maskHongbin Ji1-1/+1
This is to cancel the indirect read transfer process, so should be use CQSPI_REG_INDIRECTRD_CANCEL_MASK Signed-off-by: Hongbin Ji <jhb_ee@163.com> Link: https://lore.kernel.org/r/20230222092128.4237-1-jhb_ee@163.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-22Merge tag 'spi-v6.3' of ↵Linus Torvalds25-436/+1728
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "This has been a fairly quiet release for SPI, though it is likely that the next release will have some big changes as there's some preparatory work for multiple chip select support gone in - the rest of the code is on the list but will need to be rebased onto -rc1. Otherwise there's a couple of new tunables for chip select timings, some new devices and smaller device specific updates and fixes. - Support for configuring the hold and minimum inactive times for chip selects. - Beginnings of support for supporting devices which have multiple chip selects on a single device. - Support for newer Broadcom HSSPI and Intel controllers, Silicon Labs EM3581 and SI3210" * tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (67 commits) spi: dt-bindings: qcom,spi-qcom-qspi: document OPP and power-domains spi: spidev: drop the incorrect notice from Kconfig spi: bcm63xx-hsspi: fix error code in probe spi: bcmbca-hsspi: Fix error code in probe() function spi: synquacer: Fix timeout handling in synquacer_spi_transfer_one() spi: intel: Check number of chip selects after reading the descriptor spi: xilinx: add force_irq for QSPI mode spi: spi-st-ssc: convert to DT schema spi: Reorder fields in 'struct spi_transfer' spi: cadence-quadspi: use STIG mode for small reads spi: cadence-quadspi: setup ADDR Bits in cmd reads spi: cadence-quadspi: Add flag for direct mode writes spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion MAINTAINERS: Remove file reference for Broadcom Broadband SoC HS SPI driver entry spi: bcm63xx-hsspi: bcmbca-hsspi: fix _be16 type usage MAINTAINERS: Add entry for Broadcom Broadband SoC HS SPI drivers spi: bcmbca-hsspi: Add driver for newer HSSPI controller spi: bcm63xx-hsspi: Disable spi mem dual io read op support spi: spi-mem: Allow controller supporting mem_ops without exec_op spi: bcm63xx-hsspi: Add prepend mode support ...
2023-02-21Merge tag 'arm-boardfile-remove-6.3' of ↵Linus Torvalds6-1169/+1
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC boardfile updates from Arnd Bergmann "Unused boardfile removal for 6.3 This is a follow-up to the deprecation of most of the old-style board files that was merged in linux-6.0, removing them for good. This branch is almost exclusively dead code removal based on those annotations. Some device driver removals went through separate subsystem trees, but the majority is in the same branch, in order to better handle dependencies between the patches and avoid breaking bisection. Unfortunately that leads to merge conflicts against other changes in the subsystem trees, but they should all be trivial to resolve by removing the files. See commit 7d0d3fa7339e ("Merge tag 'arm-boardfiles-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") for the description of which machines were marked unused and are now removed. The only removals that got postponed are Terastation WXL (mv78xx0) and Jornada720 (StrongARM1100), which turned out to still have potential users" * tag 'arm-boardfile-remove-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (91 commits) mmc: omap: drop TPS65010 dependency ARM: pxa: restore mfp-pxa320.h usb: ohci-omap: avoid unused-variable warning ARM: debug: remove references in DEBUG_UART_8250_SHIFT to removed configs ARM: s3c: remove obsolete s3c-cpu-freq header MAINTAINERS: adjust SAMSUNG SOC CLOCK DRIVERS after s3c24xx support removal MAINTAINERS: update file entries after arm multi-platform rework and mach-pxa removal ARM: remove CONFIG_UNUSED_BOARD_FILES mfd: remove htc-pasic3 driver w1: remove ds1wm driver usb: remove ohci-tmio driver fbdev: remove w100fb driver fbdev: remove tmiofb driver mmc: remove tmio_mmc driver mfd: remove ucb1400 support mfd: remove toshiba tmio drivers rtc: remove v3020 driver power: remove pda_power supply driver ASoC: pxa: remove unused board support pcmcia: remove unused pxa/sa1100 drivers ...
2023-02-18Merge remote-tracking branch 'spi/for-6.3' into spi-nextMark Brown25-438/+1742
2023-02-16Merge tag 'spi-v6.2-rc8-abi' of ↵Linus Torvalds1-5/+18
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fix from Mark Brown: "One more last minute patch for v6.2 updating the parsing of the newly added spi-cs-setup-delay-ns. It's been pointed out that due to the way DT parsing works the change in property size is ABI visible so let's not let a release go out without it being fixed. The change got split from some earlier ABI related fixes to the property since the first version sent had a build error" * tag 'spi-v6.2-rc8-abi' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: Use a 32-bit DT property for spi-cs-setup-delay-ns
2023-02-16spi: spidev: drop the incorrect notice from KconfigBartosz Golaszewski1-3/+0
The spidev interface has been de-facto stable for many years. This notice has been unchanged since 2007 and is incorrect so remove it. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20230216123014.110541-1-brgl@bgdev.pl Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-16spi: bcm63xx-hsspi: fix error code in probeDan Carpenter1-1/+2
This code accidentally returns success instead of a negative error code. Fixes: 50a6620dd1fb ("spi: bcm63xx-hsspi: Add polling mode support") Signed-off-by: Dan Carpenter <error27@gmail.com> Reviewed-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/Y+zmoGH6LubPhiI0@kili Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-16spi: bcmbca-hsspi: Fix error code in probe() functionDan Carpenter1-1/+2
This code accidentally returns success instead of a negative error code. Fixes: a38a2233f23b ("spi: bcmbca-hsspi: Add driver for newer HSSPI controller") Signed-off-by: Dan Carpenter <error27@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/Y+zmrNJ9zjNQpzWq@kili Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-15spi: synquacer: Fix timeout handling in synquacer_spi_transfer_one()Christophe JAILLET1-4/+3
wait_for_completion_timeout() never returns a <0 value. It returns either on timeout or a positive value (at least 1, or number of jiffies left till timeout) So, fix the error handling path and return -ETIMEDOUT should a timeout occur. Fixes: b0823ee35cf9 ("spi: Add spi driver for Socionext SynQuacer platform") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/c2040bf3cfa201fd8890cfab14fa5a701ffeca14.1676466072.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-15spi: intel: Check number of chip selects after reading the descriptorMika Westerberg1-4/+4
The flash decriptor contains the number of flash components that we use to figure out how many flash chips there are connected. Therefore we need to read it first before deciding how many chip selects the controller has. Reported-by: Marcin Witkowski <marcin.witkowski@intel.com> Fixes: 3f03c618bebb ("spi: intel: Add support for second flash chip") Cc: stable@vger.kernel.org Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230215110040.42186-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14spi: xilinx: add force_irq for QSPI modeVadim Fedorenko1-2/+7
Xilinx PG158 page 80 [1] states that master transaction inhibit bit must be set to properly setup the transaction in QSPI mode. Add the force_irq flag to follow this sequence. [1] https://docs.xilinx.com/r/en-US/pg153-axi-quad-spi/Dual/Quad-SPI-Mode-Transactions Signed-off-by: Vadim Fedorenko <vadfed@meta.com> Link: https://lore.kernel.org/r/20230214135928.1253205-1-vadfed@meta.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14spi: STIG Mode Fixes for spi-cadence-qspi driverMark Brown1-4/+38
Merge series from Dhruva Gole <d-gole@ti.com>: * Reset the CMD_CTRL Register, without which read/writes in STIG mode were failing in some cases. The issue came to light while using STIG Mode for small reads. * Also add a flag that can allow us to do direct reads but distinguish direct writes, thus enabling us to disable writes in DAC mode in some cases that require it. (Like to write to some connected Flash registers) * Fix register reads in STIG mode and also use STIG mode while reading flash registers. Currently if you try to read a register while in STIG mode there is no support for ADDR and thus naturally a register never gets read from the flash. This patch series has been tested on a TI AM625-SK-EVM with both a quad spi nor flash (s25hs) and OSPI NOR Flash (s28hs). Output of ltp-ddt test, "DD_RW_ERASESIZE_UBIFS" run with s25hs512t flash: ... [ 2.334068] spi-nor spi0.0: s25hs512t (65536 Kbytes) [ 2.339185] 7 fixed-partitions partitions found on MTD device fc40000.spi.0 [ 2.346158] Creating 7 MTD partitions on "fc40000.spi.0": [ 2.351555] 0x000000000000-0x000000080000 : "ospi.tiboot3" [ 2.358344] 0x000000080000-0x000000280000 : "ospi.tispl" [ 2.364788] 0x000000280000-0x000000680000 : "ospi.u-boot" [ 2.371311] 0x000000680000-0x0000006c0000 : "ospi.env" [ 2.377519] 0x0000006c0000-0x000000700000 : "ospi.env.backup" [ 2.384419] 0x000000800000-0x000003fc0000 : "ospi.rootfs" [ 2.390890] 0x000003fc0000-0x000004000000 : "ospi.phypattern" ..snip.. Test Start Time: Wed Jan 11 21:14:31 2023 ----------------------------------------- Testcase Result Exit Value -------- ------ ---------- OSPI_S_FUNC_DD_RW_ERASESIZE_UBIFS PASS 0 ----------------------------------------------- Total Tests: 1 Total Skipped Tests: 0 Total Failures: 0 Kernel Version: 6.2.0-rc1-00040-g700d796a94e0-dirty Machine Architecture: aarch64 Hostname: am62xx-evm
2023-02-14spi: Reorder fields in 'struct spi_transfer'Christophe JAILLET1-1/+1
Group some variables based on their sizes to reduce hole and avoid padding. On x86_64, this shrinks the size from 144 to 128 bytes. Turn 'timestamped' into a bitfield so that it can be easily merged with some other bifields and move 'error'. This should have no real impact on memory allocation because 'struct spi_transfer' is mostly used on stack, but it can save a few cycles when the structure is initialized or copied. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/93a051da85a895bc6003aedfb00a13e1c2fc6338.1676370870.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14spi: cadence-quadspi: use STIG mode for small readsDhruva Gole1-1/+7
Fix the issue where some flash chips like cypress S25HS256T return the value of the same register over and over in DAC mode. For example in the TI K3-AM62x Processors refer [0] Technical Reference Manual there is a layer of digital logic in front of the QSPI/OSPI Drive when used in DAC mode. This is part of the Flash Subsystem (FSS) which provides access to external Flash devices. The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit mode enabled by default. Thus, by default controller operates in 32 bit mode causing it to always align all data to 4 bytes from a 4byte aligned address. In some flash chips like cypress for example if we try to read some regs in DAC mode then it keeps sending the value of the first register that was requested and inorder to read the next reg, we have to stop and re-initiate a new transaction. This causes wrong register values to be read than what is desired when registers are read in DAC mode. Hence if the data.nbytes is very less then prefer STIG mode for such small reads. [0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-5-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14spi: cadence-quadspi: setup ADDR Bits in cmd readsDhruva Gole1-0/+11
Setup the Addr bit field while issuing register reads in STIG mode. This is needed for example flashes like cypress define in their transaction table that to read any register there is 1 cmd byte and a few more address bytes trailing the cmd byte. Absence of addr bytes will obviously fail to read correct data from flash register that maybe requested by flash driver because the controller doesn't even specify which address of the flash register the read is being requested from. Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-4-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14spi: cadence-quadspi: Add flag for direct mode writesDhruva Gole1-2/+11
Create new flag inorder to avoid playing with use_direct_mode flag currently being used throughout the driver. Disable DAC write if auto polling is disabled or CQSPI_DISABLE_DAC_MODE is set. Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-3-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-14spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completionDhruva Gole1-1/+9
If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause issues in future command reads. This issue came to light when some flash reads in STIG mode were coming back dirty. Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-2-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-13spi: bcm63xx-hsspi: bcmbca-hsspi: fix _be16 type usageWilliam Zhang2-6/+10
sparse tool report warnings: drivers/spi/spi-bcm63xx-hsspi.c:197:31: sparse: sparse: cast from restricted __be16. The controller requires big endian 16 bit data. Define an intermediate u16 value and use __be16 piointer dereferncing for the data to avoid directly casting to u16 and sparse warning. Fixes: 85a84a616999 ("spi: bcm63xx-hsspi: Endianness fix for ARM based SoC") Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202302110438.sQwQnU54-lkp@intel.com/ Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230211032759.72967-1-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-11spi: bcmbca-hsspi: Add driver for newer HSSPI controllerWilliam Zhang3-0/+661
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-11spi: bcm63xx-hsspi: Disable spi mem dual io read op supportWilliam Zhang1-0/+23
In general the controller supports SPI dual mode operation but the particular SPI flash dual io read op switches from single mode in cmd phase to dual mode in address and data phase. This is not compatible with prepend operation where cmd and address are sent out through the prepend buffer and they must use same the number of io pins. This patch disables these SPI flash dual io read ops through the mem_ops supports_op interface. This makes sure the SPI flash driver selects the compatible read ops at run time. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-14-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-11spi: spi-mem: Allow controller supporting mem_ops without exec_opWilliam Zhang2-8/+7
Currently exec_op is always required if controller driver provides mem_ops. But some controller such as bcm63xx-hsspi may only need to implement other operation like supports_op and use the default execution operation. This patch removes this restriction. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-13-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-11spi: bcm63xx-hsspi: Add prepend mode supportWilliam Zhang1-37/+324
Due to the controller limitation to keep the chip select low during the bus idle time between the transfer, a dummy cs workaround was used when this driver was first upstreamed to the kernel. It basically picks the dummy cs as !actual_cs so typically dummy cs is 1 when most of the case only cs 0 is used in the board design. Then invert the polarity of both cs and tell the controller to start the transfers using dummy cs. Assuming both cs are active low before the inversion, effectively this keeps dummy cs high and actual cs low during the transfer and workaround the issue. This workaround implies that dummy cs 1 pin has to be set to chip selection function in the pinmux when the transfer clock is above 25MHz. The old chips likely have default pinmux set to chip select on the dummy cs pin so it works but this is not case for the new Broadband BCA chips and this workaround stop working. This is specifically an issue to support SPI NAND and SPI NOR flash because these flash devices can typically run at or above 100MHz. This patch utilizes the prepend feature of the controller to combine the multiple transfers in the same message to a single transfer when possible. This way there is no need to keep clock low between transfers and solve the issue without any hardware requirement. Multiple transfers within a SPI message may be combined into one transfer if the following are all true: * One or more half duplex write transfer in single bit mode * Optional full duplex read/write at the end * No delay and cs_change between transfers Most of the SPI device meets this requirements such as SPI NOR, SPI NAND flash, Broadcom SPI voice card and etc. For any SPI message that does not meet the above requirement to combine the transfers, we switch to original dummy cs mode but limit the clock rate to the safe 25MHz. This is the default auto transfer mode and it makes sure all the SPI message can be supported automatically under the hood. This patch also adds the driver sysfs node xfer_mode to provide the option for overriding the default auto mode and force it to dummy cs or prepend mode. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-12-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-11spi: bcm63xx-hsspi: Fix multi-bit mode settingWilliam Zhang1-4/+9
Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues. This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width. Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-11spi: bcm63xx-hsspi: Handle cs_change correctlyWilliam Zhang1-10/+23
The kernel SPI interface includes the cs_change flag that alters how the CS behaves. If we're in the middle of transfers, it tells us to unselect the CS momentarily since the target device requires that. If we're at the end of a transfer, it tells us to keep the CS selected, perhaps because the next transfer is likely targeted to the same device. We implement this scheme in the HSSPI driver in this change. Prior to this change, the CS would toggle momentarily if cs_change was set for the last transfer. This can be ignored by some or most devices, but the Microchip TPM2 device does not ignore it. With the change, the behavior is corrected and the 'glitch' is eliminated. Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-10-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-11spi: export spi_transfer_cs_change_delay_exec functionWilliam Zhang1-0/+7
For SPI controller that implements transfer_one_message, it needs to insert the delay that required by cs change event between the transfers. Add a wrapper for the local function _spi_transfer_cs_change_delay_exec and export it for SPI controller driver to use. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230209200246.141520-9-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-10spi: intel: Update help text of PCI and Platform driversMauro Lima1-10/+10
Modern intel hardware uses controllers that work in hardware sequencing mode. In this mode, the controller exposes a subset of operations, like read, write and erase, making it easier and less error-prone for use. On the other hand, most of the controllers handled by the platform driver use software sequencing that exposes the entire set of operations i.e. exposes the low level SPI-NOR opcodes to the software for use. Update PCI and Platform help text with this information. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230210164158.211065-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-09Add MediaTek MT7986 SPI NAND supportMark Brown1-2/+39
Merge series from Xiangsheng Hou <xiangsheng.hou@mediatek.com>: This patch series split from bellow series which pick-up spi relevant patches https://lore.kernel.org/all/20230130030656.12127-1-xiangsheng.hou@mediatek.com. This series add MediaTek MT7986 SPI NAND controller support, add read latch latency, smaple delay adjust and add optional nfi_hclk.
2023-02-09spi: mtk-snfi: Add snfi sample delay and read latency adjustmentXiangsheng Hou1-0/+20
Add snfi sample delay and read latency adjustment which can get from dts property. Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230201020921.26712-5-xiangsheng.hou@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-09spi: mtk-snfi: Add optional nfi_hclk which is needed for MT7986Xiangsheng Hou1-0/+18
Add optional nfi_hclk which is needed for MT7986. Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230201020921.26712-3-xiangsheng.hou@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-09spi: mtk-snfi: Change default page format to setup default settingXiangsheng Hou1-2/+1
Change default page format to setup default setting since the sector size 1024 on MT7986 will lead to probe fail. Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com> Link: https://lore.kernel.org/r/20230201020921.26712-2-xiangsheng.hou@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-09spi: bcm63xx-hsspi: Add polling mode supportWilliam Zhang1-11/+98
Polling mode provides better throughput in general by avoiding the interrupt overhead as the maximum data size one interrupt can handle is only 512 bytes. So switch to polling mode as the default mode but add a driver sysfs option wait_mode to allow user manually changing the mode at run time between interrupt and polling. Also add driver banner message when the driver is loaded successfully. When test on a Broadcom BCM47622(ARM A7 dual core) reference board with WINBOND W25N01GV SPI NAND chip at 100MHz SPI clock using the MTD speed test suite, it shows about 15% improvement on the write and 30% on the read: ** Interrupt mode ** mtd_speedtest: MTD device: 0 count: 16 mtd_speedtest: MTD device size 134217728, eraseblock size 131072, page size 2048, count of eraseblocks 1024, pages per eraseblock 64, OOB size 64 mtd_test: scanning for bad eraseblocks mtd_test: scanned 16 eraseblocks, 0 are bad mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 3072 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 6690 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 3066 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 6762 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 3071 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 6772 KiB/s ** Polling mode ** mtd_speedtest: MTD device: 0 count: 16 mtd_speedtest: MTD device size 134217728, eraseblock size 131072, page size 2048, count of eraseblocks 1024, pages per eraseblock 64, OOB size 64 mtd_test: scanning for bad eraseblocks mtd_test: scanned 16 eraseblocks, 0 are bad mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 3542 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 8825 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 3563 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 8787 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 3572 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 8806 KiB/s Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230207065826.285013-8-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-09spi: bcm63xx-hsspi: Endianness fix for ARM based SoCWilliam Zhang1-1/+1
HSSPI controller uses big endian for the opcode in the message to the controller ping pong buffer. Use cpu_to_be16 to properly handle the endianness for both big and little endian host. Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20230207065826.285013-7-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-09spi: bcm63xx-hsspi: Add new compatible string supportWilliam Zhang1-0/+1
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support this new binding. Signed-off-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20230207065826.285013-6-william.zhang@broadcom.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-09soc: qcom: geni-se: Move qcom-geni-se.h to linux/soc/qcom/geni-se.hElliot Berman1-1/+1
Move include/linux/qcom-geni-se.h to include/linux/soc/qcom/geni-se.h. This removes 1 of a few remaining Qualcomm-specific headers into a more approciate subdirectory under include/. Signed-off-by: Elliot Berman <quic_eberman@quicinc.com> Acked-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com> Link: https://lore.kernel.org/r/20230203210133.3552796-1-quic_eberman@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-02-07spi: intel: Remove DANGEROUS tag from pci driverMauro Lima1-7/+8
Modern CPUs exposes this controller as PCI device that only uses hardware sequencing capabilities which is safer than software sequencing. Leave the platform driver as *DANGEROUS* and update help text since most of these controllers are using software sequencing. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230206183143.75274-2-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-06spi: spidev: Fix double unlock in spidev_sync()Dan Carpenter1-2/+0
This unlocks twice due to a merge issue. Fixes: 35bba23e6732 ("Merge remote-tracking branch 'spi/for-6.2' into spi-6.2") Signed-off-by: Dan Carpenter <error27@gmail.com> Link: https://lore.kernel.org/r/Y+ETCk7XKfAy8yWQ@kili Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-06spi: Merge fixesMark Brown4-32/+44
The automated merge for the spidev locking fixes is going wrong and merging the unlock twice.
2023-02-02spi: intel: Add support for controllersMauro Lima1-0/+3
Add Device IDs to the module table for the following controllers: - 9da4 Cannon Lake 300 Series On-Package - a2a4 200 Series/Z370 Chipset Family SPI Controller - 9d24 Intel® 200 Series Chipset Family (Including Intel® X299), Intel® Z370 Intel® H310C,B365, also Intel® B460 and H410 Chipset Platform Controller Hub Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230201205455.550308-3-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-02spi: intel: Fix device private data and PR_NUM for Broxton controllersMauro Lima2-6/+6
Some private data fields have to change from bxt_info to cnl_info. Here is the list of Device IDs with the respective documentation taken for validation: 0xa0a4 - Intel® 500 Series Chipset Family On-Package PCH 0x02a4 - Intel® 400 Series Chipset Family On-Package PCH 0x06a4 - Intel® 400 Series Chipset Family Platform Controller Hub 0x34a4 - Intel® 495 Chipset Family On-Package 0xa3a4 - Intel® B460 and H410 Chipset According to documentation Broxton controller type has five PR registers. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230201205455.550308-2-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-01spi: Abstract access to chip selectsMark Brown1-23/+22
Merge series from Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>: In preparation for supporting devices with multiple chip selects add an interface for accessing the chip selects via a function.
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-10 17:44:05 +0300