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2018-07-30drm: drm_printer: Add printer for devcoredumpJordan Crouse1-0/+74
Add a drm printer suitable for use with the read callback for devcoredump or other suitable buffer based output format that isn't otherwise covered by seq_file. v2: Add improved documentation per Daniel Vetter Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-30include: Move ascii85 functions from i915 to linux/ascii85.hJordan Crouse1-30/+4
The i915 DRM driver very cleverly used ascii85 encoding for their GPU state file. Move the encode functions to a general header file to support other drivers that might be interested in the same functionality. v4: Make the return value const char * as suggested by Chris Wilson v3: Fix error_puts -> err_puts pointed out by the 01.org bot v2: Update API to be cleaner for the caller as suggested by Chris Wilson Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: rework vblank event handling in dpu_crtcRajesh Yadav1-1/+14
The vblank on/off calls were missing in dpu_crtc leading to "driver forgot to call drm_crtc_vblank_off()" warning while entering suspend state. Also handle the state update completion event for a crtc being disabled in current atomic commit. This patch depends on https://www.spinics.net/lists/dri-devel/msg182402.html Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Add SDM845 DPU supportJeykumar Sankaran64-15/+31913
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Add pm_suspend/resume callbacks to msm_kmsJeykumar Sankaran2-0/+13
Used by the dpu driver for custom suspend/resume. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Add .commit() callback to msm_kms functionsJeykumar Sankaran2-0/+6
Called right before wait_for_commit_done() to perform kickoff for active crtcs. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: #define MAX_<OBJECT> in msm_drv.hJeykumar Sankaran1-5/+11
dpu uses these elsewhere in the driver (in addition to increasing MAX_PLANES, that'll come later), so pull them out into #define. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul pulled this out of the dpu megapatch] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Use labels for unwinding in the error pathJeykumar Sankaran1-22/+22
This simplifies cleanup, to make sure nothing drops out in case of error. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul split out of dpu megapatch and renamed labels] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: #define MDP version numbersJeykumar Sankaran1-4/+7
Useful for incoming DPU support Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> [seanpaul split this from the dpu megapatch] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Clean up dangling atomic_wqSean Paul2-5/+0
I missed this during the atomic conversion Changes in v3: - None Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factorAbhinav Kumar1-2/+5
Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Converted pclk_rate to u32 (Archit) - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <sibis@codeaurora.org> Cc: Archit Taneja <architt@codeaurora.org> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: enable zpos normalizationJeykumar Sankaran1-0/+3
Enable drm core zpos normalization for planes. Changes in v3: - None Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm/mdp5: subclass msm_mdss for mdp5Rajesh Yadav3-84/+109
SoCs having mdp5 or dpu have identical tree like device hierarchy where MDSS top level wrapper manages common power resources for all child devices. Subclass msm_mdss so that msm_mdss includes common defines and mdp5/dpu mdss derivations to include any extensions. Add mdss helper interface (msm_mdss_funcs) to msm_mdss base for mdp5/dpu mdss specific implementation calls. This change subclasses msm_mdss for mdp5, dpu specific changes will be done separately. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> [seanpaul rebased on msm-next and resolved conflicts] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm: Move wait_for_vblanks into mdp complete_commit() hooksSean Paul3-2/+4
DPU doesn't use this, so push it into the mdp drivers. Changes in v3: - None Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm/dsi: set encoder mode for DRM bridge explicitlyAbhinav Kumar1-2/+4
Currently, DRM bridge for DPU relies on the default video mode setting to set the encoder mode. Add an explicit call to set the encoder mode for bridges. Changes in v3: - None Reviewed-by: Archit Taneja <architt@codeauorora.org> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm/dsi: initialize postdiv_lock before use for 10nm pllRajesh Yadav1-0/+2
postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm/dsi: Use one connector for dual DSI modeChandan Uddaraju3-86/+30
Current DSI driver uses two connectors for dual DSI case even though we only have one panel. Fix this by implementing one connector/bridge for dual DSI use case. Use master DSI controllers to register one connector/bridge. Changes in v3: - None Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> [seanpaul removed unused local var causing a build warning] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-26drm/msm/dsi: adjust dsi timing for dual dsi modeChandan Uddaraju4-20/+64
For dual dsi mode, the horizontal timing needs to be divided by half since both the dsi controllers will be driving this panel. Adjust the pixel clock and DSI timing accordingly. Changes in v3: - Added Archit's R-b - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm: Add support for pps and compression mode command packetvkorjani1-0/+2
After enabling DSC we need to send compression mode command packet and pps data packet, for which 2 new data types are added 07h Compression Mode Data Type Write , short write, 2 parameters 0Ah PPS Long Write (word count determines number of bytes) This patch adds support to send these packets. Cc: David Airlie <airlied@linux.ie> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Cc: linux-fbdev@vger.kernel.org Changes in v3: - None Signed-off-by: vkorjani <vikas.korjani@intel.com> [seanpaul removed pps_write_buffer fn, added types to packet_format helpers] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm/msm/mdp5: negative x/y in cursor moveCarsten Behling1-8/+43
modesetting X11 driver may provide negative x/y cordinates in mdp5_crtc_cursor_move call when rotation is enabled. Cursor buffer can overlap down to its negative width/height. ROI has to be recalculated for negative x/y indicating using the lower/right corner of the cursor buffer and hotspot must be set in MDP5_LM_CURSOR_XY_SRC_Y MDP5_LM_CURSOR_XY_SRC_X. Signed-off-by: Carsten Behling <carsten.behling@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm/msm/dsi: replace version checks with helper functionsSibi Sankar1-212/+29
Replace version checks with the helper functions bound to cfg_handler for DSI v2, DSI 6G 1.x and DSI 6G v2.0+ controllers Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm/msm/dsi: add implementation for helper functionsSibi Sankar3-11/+278
Add dsi host helper function implementation for DSI v2 DSI 6G 1.x and DSI 6G v2.0+ controllers Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm/msm/dsi: add dsi host helper functions supportSibi Sankar2-0/+13
Add dsi host helper functions support for DSI v2 and DSI 6G 1.x controllers that are under version checks Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm/msm/mdp5: fix missing CTL flushRob Clark1-1/+11
f9cb8d8d836e fixed various race conditions with CTL flush, in particular flushing and sending the START signal before encoder state was updated. But it did this a little too well in some cases that don't trigger encoder->enable(), and CTL[n].FLUSH would never be set. When page flips happen it would paper over the bug, since the first plag flip would flush out the state to the hardware. The issue could be reproduced with, for example, modetest (without the '-v' argument). Fixes: f9cb8d8d836e drm/msm/mdp5: rework CTL START signal handling Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2018-07-25drm/msm/gpu: Increase the pm runtime autosuspend for 5xxJordan Crouse3-2/+15
Experimentation shows that resuming power quickly after suspending ends up forcing a system hang for unknown reasons on 5xx targets. To avoid cycling the power too much (especially during init) turn up the autosuspend time for a5xx to 250ms and use pm_runtime_put_autosuspend() when applicable. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm/msm/adreno: Add power management functions for system sleepDaniel Mack1-0/+1
When a msm8016 based system is woken up from suspend, the firmware in the adreno device hangs. [ 83.903416] qcom-iommu-ctx 1f09000.iommu-ctx: Unhandled context fault: fsr=0x202, iova=0x0000000000000000, fsynr=0x2, cb=1 [ 85.853633] msm 1a00000.mdss: A306: hangcheck detected gpu lockup rb 0! [ 85.853661] msm 1a00000.mdss: A306: completed fence: 370 [ 85.859073] msm 1a00000.mdss: A306: submitted fence: 372 [ 85.865113] msm 1a00000.mdss: A306: hangcheck recover! Fix this by adding pm_runtime_force_suspend/pm_runtime_force_resume as sleep ops. Signed-off-by: Daniel Mack <daniel@zonque.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-25drm/msm: call drm_atomic_helper_suspend() and drm_atomic_helper_resume()Daniel Mack2-0/+10
To make suspend and resume work on msm8916 platforms, call into the generic helpers and preserve the state across suspends. Signed-off-by: Daniel Mack <daniel@zonque.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-07-20Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie186-2268/+3620
into drm-next More features for 4.19: - Map processes to vmids for debugging GPUVM faults - Raven gfxoff fixes - Initial gfxoff support for vega12 - Use defines for interrupt sources rather than magic numbers - DC aux fixes - Finish DC logging TODO - Add more DC debugfs interfaces for conformance testing - Add CRC support for DCN - Scheduler rework in preparation for load balancing - Unify common smu9 code - Clean up UVD instancing support - ttm cleanups - Misc fixes and cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180719194001.3488-1-alexander.deucher@amd.com
2018-07-20Merge tag 'drm-intel-next-2018-07-19' of ↵Dave Airlie57-1008/+2136
git://anongit.freedesktop.org/drm/drm-intel into drm-next On GEM side: - GuC related fixes (Chris, Michal) - GTT read-only pages support (Jon, Chris) - More selftests fixes (Chris) - More GPU reset improvements (Chris) - Flush caches after GGTT writes (Chris) - Handle recursive shrinker for vma->last_active allocation (Chris) - Other execlists fixes (Chris) On Display side: - GLK HDMI fix (Clint) - Rework and cleanup around HPD pin (Ville) - Preparation work for Display Stream Compression support coming on ICL (Anusha) - Nuke LVDS lid notification (Ville) - Assume eDP is always connected (Ville) - Kill intel panel detection (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Fri 20 Jul 2018 01:51:45 AM AEST # gpg: using RSA key FA625F640EEB13CA # gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" # gpg: aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C E2A3 FA62 5F64 0EEB 13CA # Conflicts: # drivers/gpu/drm/i915/intel_lrc.c Link: https://patchwork.freedesktop.org/patch/msgid/20180719171257.GA12199@intel.com
2018-07-20Merge tag 'drm-misc-next-2018-07-18' of ↵Dave Airlie153-1150/+1790
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 4.19: Core Changes: - add support for DisplayPort CEC-Tunneling-over-AUX (Hans Verkuil) - more doc updates (Daniel Vetter) - fourcc: Add is_yuv field to drm_format_info (Ayan Kumar Halder) - dma-buf: correctly place BUG_ON (Michel Dänzer) Driver Changes: - more vkms support(Rodrigo Siqueira) - many fixes and small improments to all drivers Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180718200826.GA20165@juma
2018-07-20Merge branch 'linux-4.19' of git://github.com/skeggsb/linux into drm-nextDave Airlie26-58/+161
misc fixes and cleanups for next. Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv55CfRonQ0bo2XiitkCiWTjKwhsP=+ZFhoa-BaJ72Ryew@mail.gmail.com
2018-07-19drm/amdgpu: clean up UVD instance handling v2Christian König2-67/+64
The whole handle, filp and entity handling is superfluous here. We should have reviewed that more thoughtfully. It looks like somebody just made the code instance aware without knowing the background. v2: fix one more missed case in amdgpu_uvd_suspend Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-19drm/amdgpu: remove superflous UVD encode entityChristian König3-27/+0
Not sure what that was every used for, but now it is completely unused. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-19drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86Michel Dänzer26-64/+56
Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an opportunity for display with Raven Ridge accidentally not working. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-19drm/amd/powerplay: fixed uninitialized valueEvan Quan1-1/+1
The 'result' is not initialized correctly. It causes the API return an error code even on success. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-07-19drm/amdgpu/powerplay: use irq source defines for smu7 sourcesAlex Deucher1-3/+4
Use the newly added irq source defines rather than magic numbers for smu7 thermal interrupts. Rewiewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-19drm/i915: Update DRIVER_DATE to 20180719Rodrigo Vivi1-2/+2
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-07-19drm/i915: Remove intel_panel_detect()Ville Syrjälä4-26/+0
With neither LVDS or eDP no longer using intel_panel_detect() we can kill it, and the accompanying modparam. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180717174216.22252-3-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-07-19drm/i915: Assume eDP is always connectedVille Syrjälä1-9/+2
We never registered any kind of lid notifier for eDP, so looking at the lid status is pretty much bonkers. Let's just consider eDP always connected instead. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180717174216.22252-2-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-07-19drm/i915: Nuke the LVDS lid notifierVille Syrjälä3-152/+2
We broke the LVDS notifier resume thing in (presumably) commit e2c8b8701e2d ("drm/i915: Use atomic helpers for suspend, v2.") as we no longer duplicate the current state in the LVDS notifier and thus we never resume it properly either. Instead of trying to fix it again let's just kill off the lid notifier entirely. None of the machines tested thus far have apparently needed it. Originally the lid notifier was added to work around cases where the VBIOS was clobbering some of the hardware state behind the driver's back, mostly on Thinkpads. We now have a few report of Thinkpads working just fine without the notifier. So maybe it was misdiagnosed originally, or something else has changed (ACPI video stuff perhaps?). If we do end up finding a machine where the VBIOS is still causing problems I would suggest that we first try setting various bits in the VBIOS scratch registers. There are several to choose from that may instruct the VBIOS to steer clear. With the notifier gone we'll also stop looking at the panel status in ->detect(). v2: Nuke enum modeset_restore (Rodrigo) Cc: stable@vger.kernel.org Cc: Wolfgang Draxinger <wdraxinger.maillist@draxit.de> Cc: Vito Caputo <vcaputo@pengaru.com> Cc: kitsunyan <kitsunyan@airmail.cc> Cc: Joonas Saarinen <jza@saunalahti.fi> Tested-by: Vito Caputo <vcaputo@pengaru.com> # Thinkapd X61s Tested-by: kitsunyan <kitsunyan@airmail.cc> # ThinkPad X200 Tested-by: Joonas Saarinen <jza@saunalahti.fi> # Fujitsu Siemens U9210 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105902 References: https://lists.freedesktop.org/archives/intel-gfx/2018-June/169315.html References: https://bugs.freedesktop.org/show_bug.cgi?id=21230 Fixes: e2c8b8701e2d ("drm/i915: Use atomic helpers for suspend, v2.") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180717174216.22252-1-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-07-19drm/i915/execlists: Move the assertion we have the rpm wakeref downChris Wilson1-14/+11
There's a race between idling the engine and finishing off the last tasklet (as we may kick the tasklets after declaring an individual engine idle). However, since we do not need to access the device until we try to submit to the ELSP register (processing the CSB just requires normal CPU access to the HWSP, and when idle we should not need to submit!) we can defer the assertion unto that point. The assertion is still useful as it does verify that we do hold the longterm GT wakeref taken from request allocation until request completion. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107274 Fixes: 9512f985c32d ("drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180719075029.28643-1-chris@chris-wilson.co.uk
2018-07-19drm/i915: Handle recursive shrinker for vma->last_active allocationChris Wilson1-0/+8
If we call into the shrinker for direct relcaim inside kmalloc, it will retire the requests. If we retire the vma->last_active while processing a new i915_vma_move_to_active() we can upset the delicate bookkeeping required for the cache. After the possible invocation of the shrinker, we need to double check the vma->last_active is still valid. Fixes: 8b293eb53a7d ("drm/i915: Track the last-active inside the i915_vma") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105600#c39 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180719072206.16015-1-chris@chris-wilson.co.uk
2018-07-19drm/i915/guc: Keep guc submission permanently engagedChris Wilson3-16/+31
We make a decision at module load whether to use the GuC backend or not, but lose that setup across set-wedge. Currently, the guc doesn't override the engine->set_default_submission hook letting execlists sneak back in temporarily on unwedging leading to an unbalanced park/unpark. v2: Remove comment about switching back temporarily to execlists on guc_submission_disable(). We currently only call disable on shutdown, and plan to also call disable before suspend and reset, in which case we will either restore guc submission or mark the driver as wedged, making the reset back to execlists pointless. v3: Move reset.prepare across Fixes: 63572937cebf ("drm/i915/execlists: Flush pending preemption events during reset") Testcase: igt/drv_module_reload/basic-reload-inject Testcase: igt/gem_eio Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180717202932.1423-1-chris@chris-wilson.co.uk
2018-07-19drm/nouveau/kms/nv50-: allocate push buffers in vidmem on pascalBen Skeggs1-2/+27
Workaround for issues seen on systems with large amounts of RAM, caused by display not supporting the same physical address limits as the other parts of the GPU. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-19i915/dp/dsc: Add Rate Control Range Parameter RegistersAnusha Srivatsa1-0/+104
RC model has these parameters that correspond with each of 15 ranges of RC buffer threshold value in the RC model. The three elements are range_min_qp, range_max_qp and range_bpg_offset. Add the Rate Control range values for eDP/MIPI and DP case. The actual values are calculated usung a helper function. This patch adds the shifts to registers where the value will be written during atomic commit. v2: - Use _MMIO_PIPE() instead of _MMIO(_PICK()) (Manasi) - Combine shifts (Manasi) Cc: Jose Souza <jose.souza@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-4-git-send-email-anusha.srivatsa@intel.com
2018-07-19i915/dp/dsc: Add Rate Control Buffer Threshold RegistersAnusha Srivatsa1-0/+51
Add register defines and shifts that control the RC buffer threshold between encoder and decoder for eDP/MIPI and DP cases. The actual values are calculated usung a helper function. This patch adds the shifts to registers where the value will be written during atomic commit. v2: - Use _MMIO_PIPE() instead of _MMIO_(_PICK()) (Manasi) - Combine shifts (Manasi) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-3-git-send-email-anusha.srivatsa@intel.com
2018-07-19i915/dp/dsc: Add DSC PPS register definitionsAnusha Srivatsa1-0/+255
Display Stream Compression(DSC) has a set of Picture Parameter Set(PPS) components that the encoder must communicate to the decoder. This patch adds register definitions to the PPS parameters for eDP/MIPI case and Display Port. v2: - Use _MMIO_PIPE instead of _MMIO(_PICK()). (Manasi) - Use DSC constants as arguments. (Manasi) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-2-git-send-email-anusha.srivatsa@intel.com
2018-07-19drm/i915/icl: Add VIDEO_DIP registersAnusha Srivatsa1-0/+23
The Picture Parameter Set metadata for DSC has to be sent to the panel through secondary data packets. Add the error correction registers, data registers and control registers for the same. The control registers for transcoders A and B are already defined and will be reused for Icelake purpose. This patch adds Control register for EDP and transcoder C apart from adding the PPS data and error registers. v2: reuse MMIO_TRANS2 for _PPS_DATA and _PPS_ECC. The _MMIO_TRANS2(pipe, reg) macro definition takes care of the eDp case Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-1-git-send-email-anusha.srivatsa@intel.com
2018-07-19drm/amdgpu/pm: Remove VLA usageKees Cook1-58/+42
In the quest to remove all stack VLA usage from the kernel[1], this uses the maximum sane buffer size and removes copy/paste code. [1] https://lkml.kernel.org/r/CA+55aFzCG-zNmZwX4A2FQpadafLfEzK6CC=qPXydAacU1RqZWA@mail.gmail.com Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-19drm/amdgpu: simplify the bo reference on amdgpu_bo_updateHuang Rui1-4/+3
BO ptr already be initialized at definition, we needn't use the complicated reference. v2: fix typo at subject line Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-14 10:03:19 +0300