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2021-02-21Merge tag 'arm-drivers-v5.12' of ↵Linus Torvalds3-0/+37
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "Updates for SoC specific drivers include a few subsystems that have their own maintainers but send them through the soc tree: SCMI firmware: - add support for a completion interrupt Reset controllers: - new driver for BCM4908 - new devm_reset_control_get_optional_exclusive_released() function Memory controllers: - Renesas RZ/G2 support - Tegra124 interconnect support - Allow more drivers to be loadable modules TEE/optee firmware: - minor code cleanup The other half of this is SoC specific drivers that do not belong into any other subsystem, most of them living in drivers/soc: - Allwinner/sunxi power management work - Allwinner H616 support - ASpeed AST2600 system identification support - AT91 SAMA7G5 SoC ID driver - AT91 SoC driver cleanups - Broadcom BCM4908 power management bus support - Marvell mbus cleanups - Mediatek MT8167 power domain support - Qualcomm socinfo driver support for PMIC - Qualcomm SoC identification for many more products - TI Keystone driver cleanups for PRUSS and elsewhere" * tag 'arm-drivers-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (89 commits) soc: aspeed: socinfo: Add new systems soc: aspeed: snoop: Add clock control logic memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE memory: samsung: exynos5422-dmc: Correct function names in kerneldoc memory: ti-emif-pm: Drop of_match_ptr from of_device_id table optee: simplify i2c access drivers: soc: atmel: fix type for same7 tee: optee: remove need_resched() before cond_resched() soc: qcom: ocmem: don't return NULL in of_get_ocmem optee: sync OP-TEE headers tee: optee: fix 'physical' typos drivers: optee: use flexible-array member instead of zero-length array tee: fix some comment typos in header files soc: ti: k3-ringacc: Use of_device_get_match_data() soc: ti: pruss: Refactor the CFG sub-module init soc: mediatek: pm-domains: Don't print an error if child domain is deferred soc: mediatek: pm-domains: Add domain regulator supply dt-bindings: power: Add domain regulator supply soc: mediatek: cmdq: Remove cmdq_pkt_flush() soc: mediatek: pm-domains: Add support for mt8167 ...
2021-02-21Merge tag 'arm-dt-v5.12' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC devicetree updates from Arnd Bergmann: "After the last release contained a surprising amount of new 32-bit machines, this time two thirds of the code changes are for 64-bit. The usual updates to existing files include: - Device tree compiler warning fixes for Berlin, Renesas, SoCFPGA, nomadik, stm32, Allwinner, TI Keystone - Support for additional devices on existing machines on Renesas, SoCFPGA, at91, hisilicon, OMAP, Tegra, TI K3, Allwinner, Broadcom, ux500, Mediatek, Marvell Armada, Marvell MMP, ZynqMP, AMLogic, Qualcomm, i.MX, Layerscape, Actions, ASpeed, Toshiba - Cleanups and minor fixes for Renesas, at91, mstar, ux500, Samsung, stm32, Tegra, Broadcom, Mediatek, Marvell MMP, AMLogic, Qualcomm, i.MX, Rockchip, ASpeed, Zynq Only three new SoCs this time, but a number of boards across: Renesas: - Two Beacon EmbeddedWorks boards (RZ/G2H and RZ/G2N based) Intel SoCFPGA: - eASIC N5X board (N5X) ST-Ericsson Ux500: - Samsung GT-I9070 (Janice) phone (u8500) TI OMAP: - MYIR Tech Limited development board (AM335X) Allwinner/sunxi: - SL631 Action Camera (V3) - PineTab Early Adopter tablet (A64) Broadcom: - BCM4906 networking chip - Netgear R8000P router (BCM4906) AMLogic: - Hardkernel ODROID-HC4 development board (SM1) - Beelink GS-King-X TV Box (S922X) Qualcomm: - Snapdragon 888 / SM8350 high-end phone SoC - Qualcomm SDX55 5G modem as standalone SoC - Snapdragon MTP reference board (SM8350) - Snapdragon MTP reference board (SDX55) - Sony Kitakami phones: Xperia Z3+/Z4/Z5 (APQ8094) - Alcatel Idol 3 phone (MSM8916) - ASUS Zenfone 2 Laser phone (MSM8916) - BQ Aquaris X5 aka Longcheer L8910 phone (MSM8916) - OnePlus6 phone (SDM845) - OnePlus6T phone (SDM845) - Alfa Network AP120C-AC access point (IPQ4018) NXP i.MX6 (32-bit): - Plymovent BAS base system controller for filter systems (imx6dl) - Protonic MVT industrial touchscreen terminals (imx6dl) - Protonic PRTI6G reference board (imx6ul) - Kverneland UT1, UT1Q, UT1P, TGO agricultural terminals (imx6q/dl/qp) NXP i.MX8 (64-bit) - Beacon i.MX8M Nano development kit (imx8mn) - Boundary Devices i.MX8MM Nitrogen SBC (imx8mm) - Gateworks Venice i.MX 8M Mini Development Kits (imx8mm) - phyBOARD-Pollux-i.MX8MP (imx8mp) - Purism Librem5 Evergreen phone (imx8mp) - Kontron SMARC-sAL28 system-on-module(imx8mp) Rockchip: - NanoPi M4B Single-board computer (RK3399) - Radxa Rock Pi E router SBC (RK3328) ASpeed: - Ampere Mt. Jade, a BMC for an x86 server (AST2500) - IBM Everest, a BMC for a Power10 server (AST2600) - Supermicro x11spi, a BMC for an ARM server (AST2500) Zynq: - Ebang EBAZ4205, FPGA board (Zynq-7000) - ZynqMP zcu104 revC reference platform (ZynqMP)" * tag 'arm-dt-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (584 commits) ARM: dts: aspeed: align GPIO hog names with dtschema ARM: dts: aspeed: fix PCA95xx GPIO expander properties on Portwell dt-bindings: spi: zynq: Convert Zynq QSPI binding to yaml arm: dts: visconti: Add DT support for Toshiba Visconti5 GPIO driver ARM: dts: aspeed: ast2600evb: Add enable ehci and uhci ARM: dts: aspeed: mowgli: Add i2c rtc device ARM: dts: aspeed: amd-ethanolx: Enable secondary LPC snooping address dt-bindings: arm: xilinx: Add missing Zturn boards ARM: dts: ebaz4205: add pinctrl entries for switches ARM: dts: add Ebang EBAZ4205 device tree dt-bindings: arm: add Ebang EBAZ4205 board dt-bindings: add ebang vendor prefix ARM: dts: aspeed: Add Everest BMC machine ARM: dts: aspeed: inspur-fp5280g2: Add ipsps1 driver ARM: dts: aspeed: inspur-fp5280g2: Add GPIO line names ARM: dts: aspeed: Add Supermicro x11spi BMC machine ARM: dts: aspeed: g220a: Fix some gpio ARM: dts: aspeed: g220a: Enable ipmb ARM: dts: aspeed: rainier: Add eMMC clock phase compensation ARM: dts: aspeed: Add LCLK to lpc-snoop ...
2021-02-17Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' ↵Stephen Boyd8-0/+1014
into clk-next - PLL support on MStar/SigmaStar ARMv7 SoCs - CPU clks for Qualcomm SDX55 - GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs - GCC clks for Qualcomm SM8350 - Video clk fixups on Qualcomm SM8250 - GPU clks for Qualcomm SDM660/SDM630 - Improvements for multimedia clks on Qualcomm MSM8998 - Fix many warnings with W=1 enabled builds under drivers/clk/ * clk-socfpga: clk: socfpga: agilex: add clock driver for eASIC N5X platform dt-bindings: documentation: add clock bindings information for eASIC N5X * clk-mstar: clk: mstar: msc313-mpll: Fix format specifier clk: mstar: Allow MStar clk drivers to be compile tested clk: mstar: MStar/SigmaStar MPLL driver clk: fixed: add devm helper for clk_hw_register_fixed_factor() dt-bindings: clk: mstar msc313 mpll binding description dt-bindings: clk: mstar msc313 mpll binding header * clk-qcom: (42 commits) clk: qcom: Add Global Clock controller (GCC) driver for SC7280 dt-bindings: clock: Add SC7280 GCC clock binding clk: qcom: rpmh: Add support for RPMH clocks on SC7280 dt-bindings: clock: Add RPMHCC bindings for SC7280 clk: qcom: gcc-sm8350: add gdsc dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc clk: qcom: gdsc: Implement NO_RET_PERIPH flag clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLs clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as critical ... * clk-warnings: (27 commits) clk: zynq: clkc: Remove various instances of an unused variable 'clk' clk: versatile: clk-icst: Fix worthy struct documentation block clk: ti: gate: Fix possible doc-rot in 'omap36xx_gate_clk_enable_with_hsdiv_restore' clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw param clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially filled one clk: st: clkgen-pll: Demote unpopulated kernel-doc header clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc' clk: socfpga: clk-pll: Remove unused variable 'rc' clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used clk: bcm: clk-iproc-pll: Demote kernel-doc abuse clk: zynqmp: divider: Add missing description for 'max_div' clk: spear: Move prototype to accessible header clk: qcom: clk-rpm: Remove a bunch of superfluous code clk: clk-xgene: Add description for 'mask' and fix formatting for 'flags' clk: qcom: mmcc-msm8974: Remove unused static const tables 'mmcc_xo_mmpll0_1_2_gpll0{map}' clk: clk-npcm7xx: Remove unused static const tables 'npcm7xx_gates' and 'npcm7xx_divs_fx' clk: clk-fixed-mmio: Demote obvious kernel-doc abuse clk: qcom: gcc-ipq4019: Remove unused variable 'ret' ...
2021-02-17Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into ↵Stephen Boyd6-6/+34
clk-next * clk-mediatek: clk: mediatek: mux: Update parent at enable time clk: mediatek: mux: Drop unused clock ops clk: mediatek: Select all the MT8183 clocks by default * clk-imx: dt-bindings: clock: imx: Switch to my personal address MAINTAINERS: Add section for NXP i.MX clock drivers clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header clk: imx8mn: add clkout1/2 support clk: imx8mm: add clkout1/2 support clk: imx8mq: add PLL monitor output clk: imx: clk-imx31: Remove unused static const table 'uart_clks' clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks * clk-amlogic: clk: meson: axg: Remove MIPI enable clock gate clk: meson-axg: remove CLKID_MIPI_ENABLE dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: clk-pll: make "ret" a signed integer clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL * clk-at91: clk: at91: Fix the declaration of the clocks
2021-02-17Merge branch 'clk-unused' into clk-nextStephen Boyd1-180/+0
- Remove efm32 clk driver - Remove tango4 clk driver - Remove zte zx clk driver - Remove sirf prima2/atlast clk drivers - Remove u300 clk driver * clk-unused: clk: remove u300 driver clk: remove sirf prima2/atlas drivers clk: remove zte zx driver clk: remove tango4 driver clk: Drop unused efm32gg driver
2021-02-17Merge branches 'clk-doc', 'clk-renesas', 'clk-allwinner', 'clk-rockchip' and ↵Stephen Boyd6-0/+206
'clk-xilinx' into clk-next - Convert Xilinx VCU clk driver to a proper clk provider driver - Expose Xilinx ZynqMP clk driver to more platforms * clk-doc: linux/clk.h: use correct kernel-doc notation for 2 functions * clk-renesas: (21 commits) clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation clk: renesas: r8a779a0: Add RAVB clocks clk: renesas: r8a779a0: Add I2C clocks dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H clk: renesas: r8a779a0: Add SYS-DMAC clocks clk: renesas: r8a779a0: Add SDHI support clk: renesas: rcar-gen3: Factor out CPG library clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock clk: renesas: r8a779a0: Add MSIOF clocks clk: renesas: r8a779a0: Add PFC/GPIO clocks clk: renesas: r8a779a0: Fix parent of CBFUSA clock clk: renesas: r8a779a0: Remove non-existent S2 clock clk: renesas: r8a779a0: Add HSCIF support clk: renesas: r8a779a0: Add RWDT clocks clk: renesas: r8a779a0: Add VSPX clock support clk: renesas: r8a779a0: Add VSPD clock support clk: renesas: r8a779a0: Add FCPVD clock support clk: renesas: r8a77995: Add TMU clocks clk: renesas: r8a77990: Add TMU clocks clk: renesas: r8a77965: Add TMU clocks ... * clk-allwinner: clk: sunxi-ng: Add support for the Allwinner H616 CCU clk: sunxi-ng: Add support for the Allwinner H616 R-CCU dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: h6: Fix clock divider range on some clocks clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers clk: sunxi-ng: h6: Fix CEC clock clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset * clk-rockchip: clk: rockchip: fix DPHY gate locations on rk3368 clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368 clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 clk: rockchip: Demote non-conformant kernel-doc header in half-divider clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls clk: rockchip: Remove unused/undocumented struct members from clk-cpu clk: rockchip: Demote non-conformant kernel-doc headers in main clock code * clk-xilinx: clk: xilinx: move xlnx_vcu clock driver from soc soc: xilinx: vcu: fix alignment to open parenthesis soc: xilinx: vcu: fix repeated word the in comment soc: xilinx: vcu: use bitfields for register definition soc: xilinx: vcu: remove calculation of PLL configuration soc: xilinx: vcu: make the PLL configurable soc: xilinx: vcu: make pll post divider explicit soc: xilinx: vcu: implement clock provider for output clocks soc: xilinx: vcu: register PLL as fixed rate clock soc: xilinx: vcu: implement PLL disable soc: xilinx: vcu: add helpers for configuring PLL soc: xilinx: vcu: add helper to wait for PLL locked soc: xilinx: vcu: drop coreclk from struct xlnx_vcu clk: divider: fix initialization with parent_hw ARM: dts: vcu: define indexes for output clocks clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support clk: clk-axiclkgen: add ZynqMP PFD and VCO limits clk: axi-clkgen: replace ARCH dependencies with driver deps
2021-02-14dt-bindings: clock: Add SC7280 GCC clock bindingTaniya Das1-0/+226
Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SC7280 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1612981579-17391-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: gcc-sm8350: add gdscVinod Koul1-0/+12
Add the GDSC found in GCC for SM8350 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210210161649.431741-1-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driverAngeloGioacchino Del Regno1-0/+28
The GPUCC manages the clocks for the Adreno GPU found on the SDM630, SDM636, SDM660 SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-9-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driverMartin Botka1-0/+162
Add a driver for the multimedia clock controller found on SDM660 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Martin Botka <martin.botka@somainline.org> Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> [angelogioacchino.delregno@somainline.org: Cleaned up SDM630 clock fixups] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-4-angelogioacchino.delregno@somainline.org [sboyd@kernel.org: Silence NULL pointer sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-14dt-bindings: clk: mstar msc313 mpll binding headerDaniel Palmer1-0/+19
Simple header to document the relationship between the MPLL outputs and which divider they come from. Output 0 is missing because it should not be consumed. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210211052206.2955988-2-daniel@0x0f.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-12Merge branches 'arm/renesas', 'arm/smmu', 'x86/amd', 'x86/vt-d' and 'core' ↵Joerg Roedel8-17/+275
into next
2021-02-10Merge tag 'qcom-drivers-for-5.12' of ↵Arnd Bergmann1-0/+9
git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for 5.12 The socinfo driver gains support for dumping information about the platform's PMICs, as well as new definitions for a number of platforms. The LLCC driver gains SM8250 support, AOSS QMP gains SM8350 support and the RPMPD driver gains support for MSM8994 power domains. In addition to this it contains a few minor fixes in the ocmem, rpmh and llcc drivers. * tag 'qcom-drivers-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: ocmem: don't return NULL in of_get_ocmem soc: qcom: socinfo: Remove unwanted le32_to_cpu() soc: qcom: aoss: Add SM8350 compatible drivers: soc: qcom: rpmpd: Add msm8994 RPM Power Domains soc: qcom: socinfo: Fix an off by one in qcom_show_pmic_model() soc: qcom: socinfo: Fix off-by-one array index bounds check soc: qcom: socinfo: Add MDM9607 IDs soc: qcom: socinfo: Add SoC IDs for APQ/MSM8998 soc: qcom: socinfo: Add SoC IDs for 630 family soc: qcom: socinfo: Open read access to all for debugfs soc: qcom: socinfo: add info from PMIC models array soc: qcom: socinfo: add several PMIC IDs soc: qcom: socinfo: add qrb5165 SoC ID soc: qcom: rpmh: Remove serialization of TCS commands soc: qcom: smem: use %*ph to print small buffer dt-bindings: soc: qcom: convert qcom,smem bindings to yaml drivers: qcom: rpmh-rsc: Do not read back the register write on trigger soc: qcom: llcc-qcom: Add support for SM8250 SoC soc: qcom: llcc-qcom: Extract major hardware version dt-bindings: msm: Add LLCC for SM8250 Link: https://lore.kernel.org/r/20210204052258.388890-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-09clk: meson-axg: remove CLKID_MIPI_ENABLERemi Pommarel1-1/+0
CLKID_MIPI_ENABLE is not handled by the AXG clock driver anymore but by the MIPI/PCIe PHY driver. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2021-02-09dt-bindings: connector: Add SVDM VDO propertiesKyle Tso1-1/+310
Add bindings of VDO properties of USB PD SVDM so that they can be used in device tree. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Kyle Tso <kyletso@google.com> Link: https://lore.kernel.org/r/20210205033415.3320439-7-kyletso@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-09clk: remove zte zx driverArnd Bergmann1-180/+0
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120131026.1721788-3-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-09ARM: dts: vcu: define indexes for output clocksMichael Tretter1-0/+15
The VCU System-Level Control has 4 output clocks. Define indexes for these clocks to allow to reference them in the device tree. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-2-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08dt-bindings: clock: gcc-msm8998: Add HMSS_GPLL0_CLK_SRC definitionAngeloGioacchino Del Regno1-0/+1
Add new clock definition to gcc-msm8998 dt-bindings Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-4-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08dt-bindings: clocks: gcc-msm8998: Add GCC_MMSS_GPLL0_CLK definitionAngeloGioacchino Del Regno1-0/+1
Add new clock definition to gcc-msm8998 dt-bindings. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-2-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08dt-bindings: clock: Add missing SM8250 videoc clock indicesBryan O'Donoghue1-0/+2
Two indexes need to be added to videocc-sm8250.h for venus to function properly. Rather than adding the missing indexes when used we add them separately here to keep checkpatch.pl happy. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210204150120.1521959-2-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08dt-bindings: clock: Add SM8350 GCC clock bindingsVinod Koul1-0/+254
Add device tree bindings for global clock controller on SM8350 SoCs. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210127070811.152690-5-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08dt-bindings: clock: Add SC8180x GCC bindingBjorn Andersson1-0/+309
Add devicetree binding for the global clock controller found in the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210126043155.1847823-1-bjorn.andersson@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-07dt-binding: mt8192: add toprgu reset-controller head fileCrystal Guo1-0/+30
add toprgu reset-controller head file for MT8192 platform Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20201014131936.20584-4-crystal.guo@mediatek.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2021-02-06clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368Heiko Stuebner1-0/+1
Needed to provide clocks for cameras. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210205110502.1850669-3-heiko@sntech.de
2021-02-06clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368Heiko Stuebner1-0/+2
Needed by the mipi dphys. The naming follows the clock names in the manual. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210205110502.1850669-1-heiko@sntech.de
2021-02-03Merge tag 'v5.11-next-soc' of ↵Arnd Bergmann1-0/+17
git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers pm-domains: - add support for MT8167 - add support for regulator needed by a PM domain - make error message in deferred probe case better cmdq-helper: - remove arch specific flush function, use mailbox rx_callback instead * tag 'v5.11-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: pm-domains: Don't print an error if child domain is deferred soc: mediatek: pm-domains: Add domain regulator supply dt-bindings: power: Add domain regulator supply soc: mediatek: cmdq: Remove cmdq_pkt_flush() soc: mediatek: pm-domains: Add support for mt8167 dt-bindings: power: Add MT8167 power domains Link: https://lore.kernel.org/r/5faa52c2-0ddb-b809-7444-ce6f6ff6d8ad@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-02-01Merge branch 'icc-sdx55' into icc-nextGeorgi Djakov1-0/+76
Add interconnect driver support for SDX55 platform for scaling the bandwidth requirements over RPMh. * icc-sdx55 dt-bindings: interconnect: Add Qualcomm SDX55 DT bindings interconnect: qcom: Add SDX55 interconnect provider driver Link: https://lore.kernel.org/r/20210121053254.8355-1-manivannan.sadhasivam@linaro.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2021-02-01dt-bindings: mediatek: Add binding for mt8192 IOMMUYong Wu1-0/+243
This patch adds decriptions for mt8192 IOMMU and SMI. mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation table format. The M4U-SMI HW diagram is as below: EMI | M4U | ------------ SMI Common ------------ | +-------+------+------+----------------------+-------+ | | | | ...... | | | | | | | | larb0 larb1 larb2 larb4 ...... larb19 larb20 disp0 disp1 mdp vdec IPE IPE All the connections are HW fixed, SW can NOT adjust it. mt8192 M4U support 0~16GB iova range. we preassign different engines into different iova ranges: domain-id module iova-range larbs 0 disp 0 ~ 4G larb0/1 1 vcodec 4G ~ 8G larb4/5/7 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 The iova range for CCU0/1(camera control unit) is HW requirement. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-6-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
2021-02-01dt-bindings: memory: mediatek: Rename header guard for SMI header fileYong Wu6-12/+12
Only rename the header guard for all the SoC larb port header file. No funtional change. Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-5-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
2021-02-01dt-bindings: memory: mediatek: Extend LARB_NR_MAX to 32Yong Wu1-2/+2
Extend the max larb number definition as mt8192 has larb_nr over 16. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-4-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
2021-02-01dt-bindings: memory: mediatek: Add a common memory header fileYong Wu6-5/+20
Put all the macros about smi larb/port togethers. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Link: https://lore.kernel.org/r/20210111111914.22211-3-yong.wu@mediatek.com Signed-off-by: Will Deacon <will@kernel.org>
2021-01-31dt-bindings: power: Add MT8167 power domainsFabien Parent1-0/+17
Add power domains dt-bindings for MT8167. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201209133238.384030-1-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-01-30clk: imx8mn: add clkout1/2 supportLucas Stach1-1/+8
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30clk: imx8mm: add clkout1/2 supportLucas Stach1-1/+9
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-30clk: imx8mq: add PLL monitor outputLucas Stach1-1/+15
The PLL monitor is mentioned as a debug feature in the reference manual, but there are some boards that use this clock output as a reference clock for board level components. Add support for those clocks in the clock driver, so this clock output can be used properly. Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the description in the reference manual. The order in this patch has been empirically validated. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-28clk: sunxi-ng: Add support for the Allwinner H616 CCUAndre Przywara2-0/+185
While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com
2021-01-27dt-bindings: interconnect: Add Qualcomm SDX55 DT bindingsManivannan Sadhasivam1-0/+76
The Qualcomm SDX55 platform has several bus fabrics that could be controlled and tuned dynamically over RPMh according to the bandwidth demand. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210121053254.8355-2-manivannan.sadhasivam@linaro.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2021-01-27dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PMSowjanya Komatineni1-1/+1
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode. This patch adds clock ID for this to dt-binding. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-01-25drivers: soc: qcom: rpmpd: Add msm8994 RPM Power DomainsKonrad Dybcio1-0/+9
MSM8994 uses similar to MSM8996, legacy-style voltage control, but does not include a VDD_SC_CX line. This setup is also correct for MSM8992. Do note that there exist some boards that use a tertiary PMIC (most likely pm8004), where SMPB on VDDGFX becomes SMPC. I cannot test this configuration though. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210118161943.105733-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-20ASoC: dt-bindings: lpass: Fix and common up lpass dai idsSrinivas Kandagatla3-8/+20
Existing header file design of having separate SoC specific header files for the common lpass driver has mutiple issues. This design is prone to break as an when new SoC header is added as the common DAI ids of other SoCs will be overwritten by the new ones. One of them surfaced by recent patch that adds support to sc7180, this one totally broke LPASS drivers on other Qualcomm SoCs. Before this gets worst, fix this by having a common header qcom,lpass.h. This should fix the issue and any new DAI ids should be added to the common header. This will be more sustainable then the existing design! Fixes: 12fbfc4cabec6595 ("ASoC: Add sc7180-lpass binding header hdmi define") Reported-by: Jun Nie <jun.nie@linaro.org> Reported-by: Stephan Gerhold <stephan@gerhold.net> Tested-by: Srinivasa Rao <srivasam@codeaurora.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210119171527.32145-2-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-15dt-bindings: pinctrl: Document canaan,k210-fpioa bindingsDamien Le Moal1-0/+276
Document the device tree bindings for the Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA) pinctrl driver in Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml. The new header file include/dt-bindings/pinctrl/k210-fpioa.h is added to define all 256 possible pin functions of the SoC IO pins, as well as macros simplifying the definition of pin functions in a device tree. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-01-15dt-bindings: reset: Document canaan,k210-rst bindingsDamien Le Moal1-0/+42
Document the device tree bindings for the Canaan Kendryte K210 SoC reset controller driver in Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml. The header file include/dt-bindings/reset/k210-rst.h is added to define all possible reset lines of the SoC. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-01-13dt-bindings: power: document Broadcom's PMB bindingRafał Miłecki1-0/+11
Broadcom's PMB is power controller used for disabling and enabling SoC devices. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-01-06clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and resetSamuel Holland2-0/+3
While no information about the H6 RSB controller is included in the datasheet or manual, the vendor BSP and power management blob both reference the RSB clock parent and register address. These values were verified by experimentation. Since this clock/reset are added late, the specifier is added at the end to maintain the existing DT binding. The code is kept in register order. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2021-01-05dt-bindings: interconnect: Add Qualcomm MSM8939 DT bindingsJun Nie1-0/+105
The Qualcomm MSM8939 platform has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201204075345.5161-5-jun.nie@linaro.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2021-01-05clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocksLiu Ying1-0/+2
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-04dt-bindings: clock: meson8b: remove non-existing clock macrosMartin Blumenstingl1-2/+0
CLKID_UNUSED and CLKID_XTAL aren't valid clocks. Remove them since there are no consumers of this anymore. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201221183624.932649-3-martin.blumenstingl@googlemail.com
2020-12-21Merge tag 'clk-for-linus' of ↵Linus Torvalds10-11/+368
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework got some nice improvements this time around. We gained the ability to get struct clk pointers from a struct clk_hw so that clk providers can consume the clks they provide, if they need to do something like that. This has been a long missing part of the clk provider API that will help us move away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are added for the clk_set_rate() "range" functions, similar to the tracepoints we already have for clk_set_rate() and we added a column to debugfs to help developers understand the hardware enable state of clks in case firmware or bootloader state is different than what is expected. Overall the core changes are mostly improving the clk driver writing experience. At the driver level, we have the usual collection of driver updates and new drivers for new SoCs. This time around the Qualcomm folks introduced a good handful of clk drivers for various parts of three or four SoCs. The SiFive folks added a new clk driver for their FU740 SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that for various new features. One last thing to note in the driver area is that the i.MX driver has gained a new binding to support SCU clks after being on the list for many months. It uses a two cell binding which is sort of rare in clk DT bindings. Beyond that we have the usual set of driver fixes and tweaks that come from more testing and finding out that some configuration was wrong or that a driver could support being built as a module. Summary: Core: - Add some trace points for clk_set_rate() "range" functions - Add hardware enable information to clk_summary debugfs - Replace clk-provider.h with of_clk.h when possible - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw New Drivers: - Bindings for Canaan K210 SoC clks - Support for SiFive FU740 PRCI - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs Updates: - DVFS support for AT91 clk driver - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors in Renesas clk drivers - One more conversion of DT bindings to json-schema - Make i.MX clk-gate2 driver more flexible - New two cell binding for i.MX SCU clks - Drop of_match_ptr() in i.MX8 clk drivers - Add arch dependencies for Rockchip clk drivers - Fix i2s on Rockchip rk3066 - Add MIPI DSI clks on Amlogic axg and g12 SoCs - Support modular builds of Amlogic clk drivers - Fix an Amlogic Video PLL clock dependency - Samsung Kconfig dependencies updates for better compile test coverage - Refactoring of the Samsung PLL clocks driver - Small Tegra driver cleanups - Minor fixes to Ingenic and VC5 clk drivers - Cleanup patches to remove unused variables and plug memory leaks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" clk: ingenic: Fix divider calculation with div tables clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 clk: si5351: Wait for bit clear after PLL reset clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error ...
2020-12-21Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and ↵Stephen Boyd1-11/+45
'clk-marvell' into clk-next - Bindings for Canaan K210 SoC clks * clk-ingenic: clk: ingenic: Fix divider calculation with div tables * clk-vc5: clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" * clk-cleanup: clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: bcm: dvp: Add MODULE_DEVICE_TABLE() clk: bcm: dvp: drop a variable that is assigned to only * clk-canaan: dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix * clk-marvell: clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
2020-12-21Merge branches 'clk-ti', 'clk-analog', 'clk-trace', 'clk-at91' and ↵Stephen Boyd1-0/+11
'clk-silabs' into clk-next - Add some trace points for clk_set_rate() "range" functions - DVFS support for AT91 clk driver * clk-ti: clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs clk: ti: Fix memleak in ti_fapll_synth_setup * clk-analog: clk: axi-clkgen: move the OF table at the bottom of the file clk: axi-clkgen: wrap limits in a struct and keep copy on the state object dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format * clk-trace: clk: Trace clk_set_rate() "range" functions * clk-at91: clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error * clk-silabs: clk: si5351: Wait for bit clear after PLL reset
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-25 19:17:09 +0300