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path: root/include/linux/clk-provider.h
AgeCommit message (Expand)AuthorFilesLines
2015-08-25clk: Constify clk_hw argument to provider APIsStephen Boyd1-7/+7
2015-08-25clk: Remove unused provider APIsStephen Boyd1-6/+0
2015-08-25clk: Add clk_hw_*() APIs for use by clk providersStephen Boyd1-0/+9
2015-07-28clk: gpio: Mark parent_names array constStephen Boyd1-1/+1
2015-07-28clk: allow a clk divider with max divisor when zeroJim Quinlan1-0/+4
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-1/+1
2015-07-28clk: Allow providers to configure min/max ratesStephen Boyd1-0/+2
2015-07-28Merge branch 'clk-determine-rate-struct' into clk-nextStephen Boyd1-20/+29
2015-07-28clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-20/+29
2015-07-20clk: Remove clk.h from clk-provider.hStephen Boyd1-1/+1
2015-07-07clk: add gpio controlled clock multiplexerSergej Sawazki1-0/+17
2015-06-20Merge tag 'tegra-for-4.2-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Michael Turquette1-0/+1
2015-06-20Merge branch 'clk-exynos-cpu-clk' into clk-nextMichael Turquette1-0/+1
2015-06-20clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock supportBartlomiej Zolnierkiewicz1-0/+1
2015-06-11clk: fixed: Add comment to clk_fixed_set_rateDaniel Thompson1-1/+1
2015-06-06clk: of: helper for filling parent clock array and return num of parentsDinh Nguyen1-0/+2
2015-05-13clk: Expose clk_hw_reparent() to providersTomeu Vizoso1-0/+1
2015-05-06clk: make strings in parent name arrays constSascha Hauer1-4/+6
2015-04-11clk: clk-gpio-gate: Fix active lowMartin Fuzzey1-1/+1
2015-02-18clk: Add __clk_hw_set_clk helper functionJavier Martinez Canillas1-0/+6
2015-02-03clk: Add rate constraints to clocksTomeu Vizoso1-3/+14
2015-02-03clk: Make clk API return per-user struct clk instancesTomeu Vizoso1-5/+7
2015-01-27clk: divider: Make generic for usage elsewhereStephen Boyd1-0/+11
2015-01-27clk: Add __clk_mux_determine_rate_closestStephen Boyd1-1/+7
2015-01-18clk: Add clk_unregister_{divider, gate, mux} to close memory leakKrzysztof Kozlowski1-0/+4
2014-12-04clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso1-2/+2
2014-12-04clk: change clk_debugfs_add_file to take a struct clk_hwTomeu Vizoso1-1/+1
2014-12-04clk: Don't expose __clk_get_accuracyTomeu Vizoso1-1/+0
2014-12-04clk: Remove unused function __clk_get_prepare_countTomeu Vizoso1-1/+0
2014-11-17clk-divider: Fix READ_ONLY when divider > 1James Hogan1-1/+0
2014-09-27Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kerne...Mike Turquette1-0/+11
2014-09-27clk: Add a function to retrieve phaseMaxime Ripard1-0/+5
2014-09-27clk: Include of.h in clock-provider.hMaxime Ripard1-0/+1
2014-09-27clk: introduce clk_set_phase function & callbackMike Turquette1-0/+5
2014-09-27clk: add gpio gated clockJyri Sarha1-0/+22
2014-07-03clk: define and export clk_debugs_add_filePeter De Schrijver1-0/+5
2014-06-08Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds1-57/+70
2014-06-04Merge tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-4/+1
2014-05-24clk: divider: add CLK_DIVIDER_READ_ONLY flagHeiko Stuebner1-0/+4
2014-05-20of: consolidate linker section OF match table declarationsRob Herring1-4/+1
2014-05-20clk: new basic clk type for fractional dividerHeikki Krogerus1-0/+31
2014-05-13clk: Improve clk_ops documentationGeert Uytterhoeven1-19/+25
2014-05-13clk: Fixup spacing in commentsGeert Uytterhoeven1-44/+44
2014-04-30clk: divider: Add round to closest dividerMaxime COQUELIN1-0/+3
2014-03-25clk: support hardware-specific debugfs entriesAlex Elder1-0/+8
2014-01-31Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/pow...Linus Torvalds1-0/+16
2014-01-29Merge remote-tracking branch 'agust/next' into nextBenjamin Herrenschmidt1-0/+16
2014-01-18CLK: ti: add init support for clock IP blocksTero Kristo1-0/+2
2014-01-17clk: Add set_rate_and_parent() opStephen Boyd1-0/+15
2014-01-12clk: mpc512x: introduce COMMON_CLK for MPC512x (disabled)Gerhard Sittig1-0/+16