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path: root/sound/soc/codecs/nau8540.h
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2017-11-16ASoC: nau8540: improve FLL performanceJohn Hsu1-0/+5
Add these parameters to improve the FLL performance. The comments show as follows: (1)ICTRL_LATCH: FLL DSP speed capability control When FLL running at high frequency with long decimal number, DSP needs to operate at high speed. FLL DSP can optimize between performance and power consumption by ICTRL_LATCH.(111 has highest power consumption.) The default setting can be used to reduce power. (2)CUTOFF500: loop filter cutoff frequency at 500Khz It will give the best FLL performance but highest power consumption to enable the cutoff frequency. FLL Loop Filter enable to reduce FLL output noise, especially,(DCO frequency)/(FLL input reference frequency) is not a integer. (3)GAIN_ERR: FLL gain error correction threshold setting The threshold is comparison between DCO and target frequency. The value 1111 has the most sensitive threshold, that is, 1111 can have the most accurate DCO to target frequency. However, the gain error setting conditionally and inversely depends on FLL input reference clock rate. Higher FLL reference input frequency can only set lower gain error, such as 0000 for input reference from MCLK=12.288Mhz. On the other side, if FLL reference input is from Frame Sync, 48KHz, higher error gain can apply such as 1111. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-07ASoC: nau8540: fix the record pop noiseJohn Hsu1-0/+2
When the record starts, the driver turns on MICBIAS and the voltage is pulled up for an instant. If the receiver starts to capture the signal between the instant, there is an pop noise in the stream beginning. To avoid the pop noise, the driver makes a delay in the sequence. After MICBIAS powered up, the driver waits 300 ms for the voltage going down. Then turns on the ADC output, and sends signal to receiver. The pop noise can be erased. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-07ASoC: nau8540: PGA short to groundJohn Hsu1-0/+12
Change channel PGA input mode selection for better recording quality. The patch shorts the inputs to ground with 12kOhm differentially terminated. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-07ASoC: nau8540: reset state machine for channel phase syncJohn Hsu1-0/+1
The four channel ADCs in NAU85L40 have difference control registers, it is hard to synchronous these four channels without correct sequence. The phase difference will not be a constant and not to conjecture easily. It may be 2.55 degree, or more ,or less. Intended to prevent phase difference of channels, the solution as follows: (1)Channel_Sync need to be enabled. (2)Do soft reset without affecting register when recording done. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-04-18ASoC: nau8540: fix tab conversion problemJohn Hsu1-155/+155
Fix the tab converting to space problem. Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-02-04ASoC: nau8540: new codec driverJohn Hsu1-0/+222
Add codec driver of NAU85L40 Signed-off-by: John Hsu <KCHSU0@nuvoton.com> Signed-off-by: Mark Brown <broonie@kernel.org>