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path: root/sound/soc/codecs/tlv320aic32x4-clk.c
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2023-08-14ASoC: tlv320aic32x4: Fix the divide by zeroGuiting Shen1-5/+11
2023-06-13ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_dete...Stephen Boyd1-5/+1
2023-06-09ASoC: tlv320aic32x4: div: Switch to determine_rateMaxime Ripard1-6/+7
2023-06-09ASoC: tlv320aic32x4: pll: Switch to determine_rateMaxime Ripard1-7/+12
2023-06-09ASoC: tlv320aic32x4: Add a determine_rate hookMaxime Ripard1-0/+1
2020-09-22ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilizationMiquel Raynal1-1/+8
2019-05-02ASoC: tlv320aic32x4: Fix potential uninitialized variableAnnaliese McDermond1-1/+1
2019-04-08ASoC: tlv320aic32x4: Fix spacingAnnaliese McDermond1-2/+2
2019-03-25ASoC: tlv320aic32x4: Model BDIV divider in CCFAnnaliese McDermond1-0/+36
2019-03-25ASoC: tlv320aic32x4: Model DAC/ADC dividers in CCFAnnaliese McDermond1-0/+90
2019-03-25ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCFAnnaliese McDermond1-0/+34
2019-03-25ASoC: tlv320aic32x4: Model PLL in CCFAnnaliese McDermond1-0/+323