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path: root/tools/testing/cxl/test/cxl.c
AgeCommit message (Expand)AuthorFilesLines
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams1-0/+46
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams1-3/+7
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams1-7/+16
2022-07-10tools/testing/cxl: Fix decoder default stateDan Williams1-1/+0
2022-07-10tools/testing/cxl: Add partition supportDan Williams1-39/+1
2022-07-10tools/testing/cxl: Expand CFMWS windowsDan Williams1-5/+5
2022-07-10tools/testing/cxl: Move cxl_test resources to the top of memoryDan Williams1-1/+2
2022-07-10cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams1-1/+1
2022-02-09tools/testing/cxl: Add a physical_node linkDan Williams1-2/+19
2022-02-09tools/testing/cxl: Enumerate mock decodersDan Williams1-20/+98
2022-02-09tools/testing/cxl: Mock one level of switchesDan Williams1-41/+97
2022-02-09tools/testing/cxl: Fix root port to host bridge assignmentDan Williams1-1/+1
2022-02-09cxl/memdev: Add numa_node attributeDan Williams1-0/+1
2022-02-09cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams1-9/+5
2022-02-09cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky1-2/+0
2022-02-09cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams1-0/+29
2022-02-09cxl/core: Generalize dport enumeration in the coreDan Williams1-21/+46
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams1-22/+46
2021-09-22tools/testing/cxl: Introduce a mock memory device + driverDan Williams1-1/+68
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams1-0/+509