From 34059321f4cf541d69e733cd02882d62c489bb77 Mon Sep 17 00:00:00 2001 From: Yongzhen Zhang Date: Fri, 15 Mar 2024 10:29:23 +0800 Subject: MIPS: BCM47XX: include header for bcm47xx_prom_highmem_init() prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bcm47xx_prom_highmem_init() is a global function declared in arch/mips/bcm47xx/bcm47xx_private.h, but this header is not included before the definition, causing a error: arch/mips/bcm47xx/prom.c:134:13: error: no previous prototype for ‘bcm47xx_prom_highmem_init’ [-Werror=missing-prototypes] 134 | void __init bcm47xx_prom_highmem_init(void) | ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Yongzhen Zhang Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/bcm47xx/prom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 99a1ba5394e0..7344a5eb990e 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -35,6 +35,7 @@ #include #include #include +#include "bcm47xx_private.h" static char bcm47xx_system_type[20] = "Broadcom BCM47XX"; -- cgit v1.2.3 From d18419cd66835c29ac732624324b99b43f4cff1c Mon Sep 17 00:00:00 2001 From: Yongzhen Zhang Date: Fri, 15 Mar 2024 10:52:35 +0800 Subject: MIPS: BCM47XX: Declare early_tlb_init() static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit early_tlb_init() was local to file but not declared static, leading to error: arch/mips/bcm47xx/prom.c:126:6: error: no previous prototype for ‘early_tlb_init’ [-Werror=missing-prototypes] 126 | void early_tlb_init(void) | ^~~~~~~~~~~~~~ Signed-off-by: Yongzhen Zhang Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/bcm47xx/prom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 7344a5eb990e..58fb7c2dc3b8 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -124,7 +124,7 @@ void __init prom_init(void) /* Stripped version of tlb_init, with the call to build_tlb_refill_handler * dropped. Calling it at this stage causes a hang. */ -void early_tlb_init(void) +static void early_tlb_init(void) { write_c0_pagemask(PM_DEFAULT_MASK); write_c0_wired(0); -- cgit v1.2.3 From b796d046433b2042577d8d6c9a5d366e39095c30 Mon Sep 17 00:00:00 2001 From: Yongzhen Zhang Date: Fri, 15 Mar 2024 12:10:43 +0800 Subject: MIPS: RB532: Declare prom_setup_cmdline() and rb532_gpio_init() static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit early_tlb_init() and rb532_gpio_init() were local to file but not declared static, leading to error: arch/mips/rb532/prom.c:49:13: error: no previous prototype for ‘prom_setup_cmdline’ [-Werror=missing-prototypes] 49 | void __init prom_setup_cmdline(void) | ^~~~~~~~~~~~~~~~~~ arch/mips/rb532/gpio.c:200:12: error: no previous prototype for ‘rb532_gpio_init’ [-Werror=missing-prototypes] 200 | int __init rb532_gpio_init(void) | ^~~~~~~~~~~~~~~ Signed-off-by: Yongzhen Zhang Signed-off-by: Thomas Bogendoerfer --- arch/mips/rb532/gpio.c | 2 +- arch/mips/rb532/prom.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 29c21b9d42da..ea6ebfea4a67 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -197,7 +197,7 @@ void rb532_gpio_set_func(unsigned gpio) } EXPORT_SYMBOL(rb532_gpio_set_func); -int __init rb532_gpio_init(void) +static int __init rb532_gpio_init(void) { struct resource *r; diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c index b11693715547..b88e89ec5894 100644 --- a/arch/mips/rb532/prom.c +++ b/arch/mips/rb532/prom.c @@ -46,7 +46,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag) return simple_strtoul(num, 0, 10); } -void __init prom_setup_cmdline(void) +static void __init prom_setup_cmdline(void) { static char cmd_line[COMMAND_LINE_SIZE] __initdata; char *cp, *board; -- cgit v1.2.3 From a1b7508cef6208ad06377d2aa05b0f89f7d6b516 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 26 Mar 2024 11:41:45 +0000 Subject: MIPS: Guard some macros with __ASSEMBLY__ in asm.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are some assembly macros with very generic naming being defined asm.h. They are clashing with other macros from C code. Guard them with __ASSEMBLY__ to prevent futher clashes. Reported-by: Geert Uytterhoeven Link: https://lore.kernel.org/linux-mips/8d78894-dd89-9f4d-52bb-1b873c50be9c@linux-m68k.org/ Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/asm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 2e99450f4228..87ff609b53fe 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -37,6 +37,7 @@ #define CFI_SECTIONS #endif +#ifdef __ASSEMBLY__ /* * LEAF - declare leaf routine */ @@ -122,6 +123,8 @@ symbol = value #define ASM_PRINT(string) #endif +#endif /* __ASSEMBLY__ */ + /* * Stack alignment */ -- cgit v1.2.3 From 29b83a64df3b42c88c0338696feb6fdcd7f1f3b7 Mon Sep 17 00:00:00 2001 From: Songyang Li Date: Wed, 20 Mar 2024 23:22:00 +0800 Subject: MIPS: Octeon: Add PCIe link status check The standard PCIe configuration read-write interface is used to access the configuration space of the peripheral PCIe devices of the mips processor after the PCIe link surprise down, it can generate kernel panic caused by "Data bus error". So it is necessary to add PCIe link status check for system protection. When the PCIe link is down or in training, assigning a value of 0 to the configuration address can prevent read-write behavior to the configuration space of peripheral PCIe devices, thereby preventing kernel panic. Signed-off-by: Songyang Li Signed-off-by: Thomas Bogendoerfer --- arch/mips/pci/pcie-octeon.c | 6 ++++++ 1 file changed, 6 insertions(+) mode change 100644 => 100755 arch/mips/pci/pcie-octeon.c diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c old mode 100644 new mode 100755 index 2583e318e8c6..b080c7c6cc46 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -230,12 +230,18 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, { union cvmx_pcie_address pcie_addr; union cvmx_pciercx_cfg006 pciercx_cfg006; + union cvmx_pciercx_cfg032 pciercx_cfg032; pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port)); if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0)) return 0; + pciercx_cfg032.u32 = + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port)); + if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)) + return 0; + pcie_addr.u64 = 0; pcie_addr.config.upper = 2; pcie_addr.config.io = 1; -- cgit v1.2.3 From f3cac4f8a93bf7f97ba1d4c2eee916fcd1e8885b Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 3 Apr 2024 14:26:33 -0700 Subject: MIPS: Add prototypes for plat_post_relocation() and relocate_kernel() When building malta_defconfig with CONFIG_RELOCATABLE=y, there are two warnings due to missing prototypes for functions only used when that configuration is enabled: arch/mips/kernel/relocate.c:42:12: warning: no previous prototype for 'plat_post_relocation' [-Wmissing-prototypes] 42 | int __weak plat_post_relocation(long offset) | ^~~~~~~~~~~~~~~~~~~~ arch/mips/kernel/relocate.c:324:14: warning: no previous prototype for 'relocate_kernel' [-Wmissing-prototypes] 324 | void *__init relocate_kernel(void) | ^~~~~~~~~~~~~~~ While relocate_kernel() is only called from assembly, it makes sense to keep the prototypes together in C to fix the warnings. Add them to silence the warnings. Signed-off-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/setup.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index 4dce41138bad..d8077136372c 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -2,6 +2,7 @@ #ifndef _MIPS_SETUP_H #define _MIPS_SETUP_H +#include #include #include @@ -29,4 +30,9 @@ extern void per_cpu_trap_init(bool); extern void cpu_cache_init(void); extern void tlb_init(void); +#ifdef CONFIG_RELOCATABLE +extern void * __init relocate_kernel(void); +extern int plat_post_relocation(long); +#endif + #endif /* __SETUP_H */ -- cgit v1.2.3 From 3eee9ac24cef892e6883b3669544c6101b70c91e Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:29 +0200 Subject: mips: dts: ralink: mt7621: reorder cpu node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder cpu node attributes to fit the DTS Coding Style. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 6e95e6f19a6a..73dad64e11fe 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -14,15 +14,15 @@ #size-cells = <0>; cpu@0 { - device_type = "cpu"; compatible = "mips,mips1004Kc"; reg = <0>; + device_type = "cpu"; }; cpu@1 { - device_type = "cpu"; compatible = "mips,mips1004Kc"; reg = <1>; + device_type = "cpu"; }; }; -- cgit v1.2.3 From 09e8ff7576ae9dd4996172d3bf18975c73f3dc77 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:30 +0200 Subject: mips: dts: ralink: mt7621: reorder cpuintc node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the CPU Interrupt Controller node's attributes to follow what the DTS Coding Style dictates. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 73dad64e11fe..ec87e46ba6de 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -27,10 +27,12 @@ }; cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; #interrupt-cells = <1>; + interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; }; mmc_fixed_3v3: regulator-3v3 { -- cgit v1.2.3 From df91c0da8096f61543837bc5d033dfdfd5d1c23d Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:31 +0200 Subject: mips: dts: ralink: mt7621: reorder mmc regulator attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the attributes of MMC fixed voltage regulator nodes for the sake of compliance with the DTS style guide. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index ec87e46ba6de..696460b2dca7 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -37,20 +37,24 @@ mmc_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "mmc_power"; }; mmc_fixed_1v8_io: regulator-1v8 { compatible = "regulator-fixed"; - regulator-name = "mmc_io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "mmc_io"; }; palmbus: palmbus@1e000000 { -- cgit v1.2.3 From 9938cd312b8f1922b76e9d48a13425d56b597580 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:32 +0200 Subject: mips: dts: ralink: mt7621: reorder sysc node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the attributes of the sysc node so that the ralink prefixed attribute is placed after those which lack prefixes. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 696460b2dca7..d1d4399d730c 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -68,12 +68,15 @@ sysc: syscon@0 { compatible = "mediatek,mt7621-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; #reset-cells = <1>; - ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", "250m", "270m"; + + ralink,memctl = <&memc>; }; wdt: watchdog@100 { -- cgit v1.2.3 From 9a4ba656343d4a34626cf0c222ecb6bac8dd1490 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:33 +0200 Subject: mips: dts: ralink: mt7621: reorder gpio node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Shuffle the attributes of the gpio node to appease the DTS style guide. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index d1d4399d730c..99d47f286769 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -86,13 +86,16 @@ }; gpio: gpio@600 { + compatible = "mediatek,mt7621-gpio"; + reg = <0x600 0x100>; + #gpio-cells = <2>; #interrupt-cells = <2>; - compatible = "mediatek,mt7621-gpio"; + gpio-controller; gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; - reg = <0x600 0x100>; interrupt-parent = <&gic>; interrupts = ; }; -- cgit v1.2.3 From 9d64db86d129067690aaa5fe6a4572515e98fe53 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:34 +0200 Subject: mips: dts: ralink: mt7621: reorder i2c node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rearrange the order of the i2c node's attributes so that they are inline with the DTS style guide. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 99d47f286769..87a3bcbc0ea5 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -104,18 +104,19 @@ compatible = "mediatek,mt7621-i2c"; reg = <0x900 0x100>; - clocks = <&sysc MT7621_CLK_I2C>; - clock-names = "i2c"; - resets = <&sysc MT7621_RST_I2C>; - reset-names = "i2c"; - #address-cells = <1>; #size-cells = <0>; - status = "disabled"; + clocks = <&sysc MT7621_CLK_I2C>; + clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c_pins>; + + resets = <&sysc MT7621_RST_I2C>; + reset-names = "i2c"; + + status = "disabled"; }; memc: memory-controller@5000 { -- cgit v1.2.3 From f5a0fc0a95a0cdbce0aa81431e924a08cec01bc9 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:35 +0200 Subject: mips: dts: ralink: mt7621: reorder spi0 node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the attributes of the SPI controller node so that they're aligned with the DTS style guide. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 87a3bcbc0ea5..60dfbae53712 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -183,22 +183,22 @@ }; spi0: spi@b00 { - status = "disabled"; - compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysc MT7621_CLK_SPI>; - clock-names = "spi"; - - resets = <&sysc MT7621_RST_SPI>; - reset-names = "spi"; - #address-cells = <1>; #size-cells = <0>; + clock-names = "spi"; + clocks = <&sysc MT7621_CLK_SPI>; + pinctrl-names = "default"; pinctrl-0 = <&spi_pins>; + + reset-names = "spi"; + resets = <&sysc MT7621_RST_SPI>; + + status = "disabled"; }; }; -- cgit v1.2.3 From 384f8ef478eb34ce25aab8164ee83f48221a4fff Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:36 +0200 Subject: mips: dts: ralink: mt7621: move pinctrl and sort its children MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the pinctrl node prior to the nodes that feature unit addresses. Sort pinctrl's child nodes into alphabetical order. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 172 +++++++++++++++++----------------- 1 file changed, 86 insertions(+), 86 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 60dfbae53712..b28aee1e4ca3 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -57,6 +57,92 @@ regulator-name = "mmc_io"; }; + pinctrl: pinctrl { + compatible = "ralink,mt7621-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + + mdio_pins: mdio0-pins { + pinmux { + groups = "mdio"; + function = "mdio"; + }; + }; + + nand_pins: nand0-pins { + sdhci-pinmux { + groups = "sdhci"; + function = "nand2"; + }; + + spi-pinmux { + groups = "spi"; + function = "nand1"; + }; + }; + + pcie_pins: pcie0-pins { + pinmux { + groups = "pcie"; + function = "gpio"; + }; + }; + + rgmii1_pins: rgmii1-pins { + pinmux { + groups = "rgmii1"; + function = "rgmii1"; + }; + }; + + rgmii2_pins: rgmii2-pins { + pinmux { + groups = "rgmii2"; + function = "rgmii2"; + }; + }; + + sdhci_pins: sdhci0-pins { + pinmux { + groups = "sdhci"; + function = "sdhci"; + }; + }; + + spi_pins: spi0-pins { + pinmux { + groups = "spi"; + function = "spi"; + }; + }; + + uart1_pins: uart1-pins { + pinmux { + groups = "uart1"; + function = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + pinmux { + groups = "uart2"; + function = "uart2"; + }; + }; + + uart3_pins: uart3-pins { + pinmux { + groups = "uart3"; + function = "uart3"; + }; + }; + }; + palmbus: palmbus@1e000000 { compatible = "palmbus"; reg = <0x1e000000 0x100000>; @@ -202,92 +288,6 @@ }; }; - pinctrl: pinctrl { - compatible = "ralink,mt7621-pinctrl"; - - i2c_pins: i2c0-pins { - pinmux { - groups = "i2c"; - function = "i2c"; - }; - }; - - spi_pins: spi0-pins { - pinmux { - groups = "spi"; - function = "spi"; - }; - }; - - uart1_pins: uart1-pins { - pinmux { - groups = "uart1"; - function = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - pinmux { - groups = "uart2"; - function = "uart2"; - }; - }; - - uart3_pins: uart3-pins { - pinmux { - groups = "uart3"; - function = "uart3"; - }; - }; - - rgmii1_pins: rgmii1-pins { - pinmux { - groups = "rgmii1"; - function = "rgmii1"; - }; - }; - - rgmii2_pins: rgmii2-pins { - pinmux { - groups = "rgmii2"; - function = "rgmii2"; - }; - }; - - mdio_pins: mdio0-pins { - pinmux { - groups = "mdio"; - function = "mdio"; - }; - }; - - pcie_pins: pcie0-pins { - pinmux { - groups = "pcie"; - function = "gpio"; - }; - }; - - nand_pins: nand0-pins { - spi-pinmux { - groups = "spi"; - function = "nand1"; - }; - - sdhci-pinmux { - groups = "sdhci"; - function = "nand2"; - }; - }; - - sdhci_pins: sdhci0-pins { - pinmux { - groups = "sdhci"; - function = "sdhci"; - }; - }; - }; - mmc: mmc@1e130000 { status = "disabled"; -- cgit v1.2.3 From 297fa85fbe96a442aa2c1f0eb062f84e59aa6d6b Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:37 +0200 Subject: mips: dts: ralink: mt7621: reorder mmc node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Shuffle the attributes of the MMC node to meet the guidelines provided by the DTS style guide. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index b28aee1e4ca3..1fbe345bd239 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -289,29 +289,33 @@ }; mmc: mmc@1e130000 { - status = "disabled"; - compatible = "mediatek,mt7620-mmc"; reg = <0x1e130000 0x4000>; bus-width = <4>; - max-frequency = <48000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&mmc_fixed_3v3>; - vqmmc-supply = <&mmc_fixed_1v8_io>; - disable-wp; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&sdhci_pins>; - pinctrl-1 = <&sdhci_pins>; + cap-mmc-highspeed; + cap-sd-highspeed; clocks = <&sysc MT7621_CLK_SHXC>, <&sysc MT7621_CLK_50M>; clock-names = "source", "hclk"; + disable-wp; + interrupt-parent = <&gic>; interrupts = ; + + max-frequency = <48000000>; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sdhci_pins>; + pinctrl-1 = <&sdhci_pins>; + + vmmc-supply = <&mmc_fixed_3v3>; + vqmmc-supply = <&mmc_fixed_1v8_io>; + + status = "disabled"; }; usb: usb@1e1c0000 { -- cgit v1.2.3 From a76a20f9e133dcd70d1cedd2705c58dbee33bb36 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:38 +0200 Subject: mips: dts: ralink: mt7621: reorder gic node attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the attributes of the Global Interrupt Controller node to fit DTS style guidelines. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 1fbe345bd239..8aa9eba686d5 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -338,15 +338,15 @@ compatible = "mti,gic"; reg = <0x1fbc0000 0x2000>; - interrupt-controller; #interrupt-cells = <3>; + interrupt-controller; mti,reserved-cpu-vectors = <7>; timer { compatible = "mti,gic-timer"; - interrupts = ; clocks = <&sysc MT7621_CLK_CPU>; + interrupts = ; }; }; -- cgit v1.2.3 From 6f04e524442ed4e258ae9c3e68eddf9c901e438c Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:39 +0200 Subject: mips: dts: ralink: mt7621: reorder ethernet node attributes and kids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rearrange attributes and descendents declared under the ethernet node, recursively, to follow the DTS style guide. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 88 +++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 40 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 8aa9eba686d5..f6418201bc10 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -364,46 +364,22 @@ compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; - clock-names = "fe", "ethif"; - #address-cells = <1>; #size-cells = <0>; - resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; - reset-names = "fe", "eth"; + clock-names = "fe", "ethif"; + clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; interrupt-parent = <&gic>; interrupts = ; - mediatek,ethsys = <&sysc>; - pinctrl-names = "default"; pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "trgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "rgmii"; + reset-names = "fe", "eth"; + resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; + mediatek,ethsys = <&sysc>; mdio: mdio-bus { #address-cells = <1>; @@ -412,73 +388,105 @@ switch0: switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; - mediatek,mcm; - resets = <&sysc MT7621_RST_MCM>; - reset-names = "mcm"; - interrupt-controller; + #interrupt-cells = <1>; + interrupt-controller; interrupts = ; + reset-names = "mcm"; + resets = <&sysc MT7621_RST_MCM>; + + mediatek,mcm; + ports { #address-cells = <1>; #size-cells = <0>; port@0 { - status = "disabled"; reg = <0>; label = "swp0"; + status = "disabled"; }; port@1 { - status = "disabled"; reg = <1>; label = "swp1"; + status = "disabled"; }; port@2 { - status = "disabled"; reg = <2>; label = "swp2"; + status = "disabled"; }; port@3 { - status = "disabled"; reg = <3>; label = "swp3"; + status = "disabled"; }; port@4 { - status = "disabled"; reg = <4>; label = "swp4"; + status = "disabled"; }; port@5 { reg = <5>; + ethernet = <&gmac1>; phy-mode = "rgmii"; fixed-link { - speed = <1000>; full-duplex; pause; + speed = <1000>; }; }; port@6 { reg = <6>; + ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { - speed = <1000>; full-duplex; pause; + speed = <1000>; }; }; }; }; }; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "trgmii"; + + fixed-link { + full-duplex; + pause; + speed = <1000>; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + + phy-mode = "rgmii"; + + fixed-link { + full-duplex; + pause; + speed = <1000>; + }; + }; + }; pcie: pcie@1e140000 { -- cgit v1.2.3 From fdcb4f10723b5730842bc4419be635065f8e608b Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:40 +0200 Subject: mips: dts: ralink: mt7621: reorder pcie node attributes and children MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the attributes and child nodes of the PCIe Controller node to meet the DTS style guidelines. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 68 ++++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 25 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index f6418201bc10..aa06d12acacc 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -495,70 +495,88 @@ <0x1e142000 0x100>, /* pcie port 0 RC control registers */ <0x1e143000 0x100>, /* pcie port 1 RC control registers */ <0x1e144000 0x100>; /* pcie port 2 RC control registers */ + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ + #address-cells = <3>; + #interrupt-cells = <1>; #size-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - device_type = "pci"; - ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ - <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ - - #interrupt-cells = <1>; - interrupt-map-mask = <0xF800 0 0 0>; - interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + status = "disabled"; + pcie@0,0 { reg = <0x0000 0 0 0 0>; + ranges; + #address-cells = <3>; + #interrupt-cells = <1>; #size-cells = <2>; + + clocks = <&sysc MT7621_CLK_PCIE0>; + device_type = "pci"; - #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; - resets = <&sysc MT7621_RST_PCIE0>; - clocks = <&sysc MT7621_CLK_PCIE0>; - phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; - ranges; + phys = <&pcie0_phy 1>; + + resets = <&sysc MT7621_RST_PCIE0>; }; pcie@1,0 { reg = <0x0800 0 0 0 0>; + ranges; + #address-cells = <3>; + #interrupt-cells = <1>; #size-cells = <2>; + + clocks = <&sysc MT7621_CLK_PCIE1>; + device_type = "pci"; - #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; - resets = <&sysc MT7621_RST_PCIE1>; - clocks = <&sysc MT7621_CLK_PCIE1>; - phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; - ranges; + phys = <&pcie0_phy 1>; + + resets = <&sysc MT7621_RST_PCIE1>; }; pcie@2,0 { reg = <0x1000 0 0 0 0>; + ranges; + #address-cells = <3>; + #interrupt-cells = <1>; #size-cells = <2>; + + clocks = <&sysc MT7621_CLK_PCIE2>; + device_type = "pci"; - #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - resets = <&sysc MT7621_RST_PCIE2>; - clocks = <&sysc MT7621_CLK_PCIE2>; - phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; - ranges; + phys = <&pcie2_phy 0>; + + resets = <&sysc MT7621_RST_PCIE2>; }; }; -- cgit v1.2.3 From de56f781e5483fb3b3527aa280df2434f0cb2ace Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:41 +0200 Subject: mips: dts: ralink: mt7621: reorder pci?_phy attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the attributes of the PCIe PHY nodes node to match what the DTS style guide recommends. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index aa06d12acacc..284811f32929 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -583,14 +583,18 @@ pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + + clocks = <&sysc MT7621_CLK_XTAL>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; - clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + + clocks = <&sysc MT7621_CLK_XTAL>; }; }; -- cgit v1.2.3 From b8f8e5a691ba75051a841e68ace5817d5c368fd9 Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Sat, 16 Mar 2024 06:54:42 +0200 Subject: mips: dts: ralink: mt7621: reorder the attributes of the root node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the compatible attribute of the DTS root node to first place. Signed-off-by: Justin Swartz Reviewed-by: Arınç ÜNAL Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/boot/dts/ralink/mt7621.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 284811f32929..0704eab4a80b 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -5,9 +5,10 @@ #include / { + compatible = "mediatek,mt7621-soc"; + #address-cells = <1>; #size-cells = <1>; - compatible = "mediatek,mt7621-soc"; cpus { #address-cells = <1>; -- cgit v1.2.3 From 40e20fbccfb722f219ab8d3ff1edde99e4a7c46c Mon Sep 17 00:00:00 2001 From: Yury Norov Date: Sat, 13 Apr 2024 11:49:13 -0700 Subject: MIPS: SGI-IP27: micro-optimize arch_init_irq() The function sets adjasted groups of bits in hub_irq_map by using for-loops. There's a bitmap_set() function dedicated to do this. Because [0, CPU_CALL_B_IRQ] and [NI_BRDCAST_ERR_A, MSC_PANIC_INTR] ranges belong to the same machine word, bitmap_set() would boil down to an inline wrapper in both cases, avoiding generating a loop, whth the associate overhead. Signed-off-by: Yury Norov Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip27/ip27-irq.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 8f5299b269e7..dcb14a234b1c 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -286,11 +286,8 @@ void __init arch_init_irq(void) * Mark these as reserved right away so they won't be used accidentally * later. */ - for (i = 0; i <= CPU_CALL_B_IRQ; i++) - set_bit(i, hub_irq_map); - - for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) - set_bit(i, hub_irq_map); + bitmap_set(hub_irq_map, 0, CPU_CALL_B_IRQ + 1); + bitmap_set(hub_irq_map, NI_BRDCAST_ERR_A, MSC_PANIC_INTR - NI_BRDCAST_ERR_A + 1); fn = irq_domain_alloc_named_fwnode("HUB"); WARN_ON(fn == NULL); -- cgit v1.2.3 From 156e6498fc61157a8779a0920008cfdfa55c4a8b Mon Sep 17 00:00:00 2001 From: Yury Norov Date: Mon, 22 Apr 2024 15:52:12 -0700 Subject: MIPS: SGI-IP27: fix -Wunused-variable in arch_init_irq() Commit 40e20fbccfb722f21 (MIPS: SGI-IP27: micro-optimize arch_init_irq()) replaced a for-loop iteration with bitmap_set() calls, but didn't remove an iteration variable. Fixes: 40e20fbccfb722f21 (MIPS: SGI-IP27: micro-optimize arch_init_irq()) Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202404161933.izfqZ32k-lkp@intel.com/ Signed-off-by: Yury Norov Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip27/ip27-irq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index dcb14a234b1c..d8acdf0439d2 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -277,7 +277,6 @@ void __init arch_init_irq(void) { struct irq_domain *domain; struct fwnode_handle *fn; - int i; mips_cpu_irq_init(); -- cgit v1.2.3 From bfe4ab93c80cc5689ab5a891e61013dfec48f56e Mon Sep 17 00:00:00 2001 From: Yury Norov Date: Tue, 16 Apr 2024 10:37:11 -0700 Subject: MIPS: SGI-IP27: use WARN_ON() output WARN_ON() propagates the result of conditional expression, and it can be used to return early in the following expression in the arch_init_irq(). This is a no-op cleanup, except that compiler may optimize the error paths better because WARN_ON() implies 'unlikely()'. Signed-off-by: Yury Norov Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip27/ip27-irq.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index d8acdf0439d2..00e63e9ef61d 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c @@ -289,13 +289,12 @@ void __init arch_init_irq(void) bitmap_set(hub_irq_map, NI_BRDCAST_ERR_A, MSC_PANIC_INTR - NI_BRDCAST_ERR_A + 1); fn = irq_domain_alloc_named_fwnode("HUB"); - WARN_ON(fn == NULL); - if (!fn) + if (WARN_ON(fn == NULL)) return; + domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT, &hub_domain_ops, NULL); - WARN_ON(domain == NULL); - if (!domain) + if (WARN_ON(domain == NULL)) return; irq_set_default_host(domain); -- cgit v1.2.3 From 07e6a6d7f1d9fa4685003a195032698ba99577bb Mon Sep 17 00:00:00 2001 From: Siarhei Volkau Date: Tue, 30 Apr 2024 18:45:58 +0300 Subject: MIPS: Take in account load hazards for HI/LO restoring MIPS CPUs usually have 1 to 4 cycles load hazards, thus doing load and right after move to HI/LO will usually stall the pipeline for significant amount of time. Let's take it into account and separate loads and mthi/lo in instruction sequence. The patch uses t6 and t7 registers as temporaries in addition to t8. The patch tries to deal with SmartMIPS, but I know little about and haven't tested it. Changes in v2: - clear separation of actions for SmartMIPS and pre-MIPSR6. Signed-off-by: Siarhei Volkau Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/stackframe.h | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index a8705aef47e1..a13431379073 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -308,17 +308,12 @@ jal octeon_mult_restore #endif #ifdef CONFIG_CPU_HAS_SMARTMIPS - LONG_L $24, PT_ACX(sp) - mtlhx $24 - LONG_L $24, PT_HI(sp) - mtlhx $24 + LONG_L $14, PT_ACX(sp) LONG_L $24, PT_LO(sp) - mtlhx $24 + LONG_L $15, PT_HI(sp) #elif !defined(CONFIG_CPU_MIPSR6) LONG_L $24, PT_LO(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - mthi $24 + LONG_L $15, PT_HI(sp) #endif #ifdef CONFIG_32BIT cfi_ld $8, PT_R8, \docfi @@ -327,6 +322,14 @@ cfi_ld $10, PT_R10, \docfi cfi_ld $11, PT_R11, \docfi cfi_ld $12, PT_R12, \docfi +#ifdef CONFIG_CPU_HAS_SMARTMIPS + mtlhx $14 + mtlhx $15 + mtlhx $24 +#elif !defined(CONFIG_CPU_MIPSR6) + mtlo $24 + mthi $15 +#endif cfi_ld $13, PT_R13, \docfi cfi_ld $14, PT_R14, \docfi cfi_ld $15, PT_R15, \docfi -- cgit v1.2.3