From 19f969c0c7388a729ec209ff74590c65a1957aab Mon Sep 17 00:00:00 2001 From: Leonard Göhrs Date: Fri, 10 Mar 2023 10:26:50 +0100 Subject: ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15xx-osd32 SoM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To support the detach feature, add a new mailbox channel to inform the remote processor on a detach. This signal allows the remote processor firmware to stop IPC communication and to reinitialize the resources for a re-attach. See 6257dfc1c412dcdbd76ca5fa92c8444222dbe5b0 for a patch that does the same for stm32mp15x-dkx boards. Signed-off-by: Leonard Göhrs Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 935b7084b5a2..a43965c86fe8 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -210,8 +210,8 @@ &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; -- cgit v1.2.3 From 0fbb60def782c40ac6338e4fed6898b690be50b0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 22:44:52 +0200 Subject: ARM: dts: stm32: drop invalid simple-panel compatible on stm32mp157c-lxa "simple-panel" compatible is not documented and nothing in Linux kernel binds to it. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index cb00ce7cec8b..407ed3952f75 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -73,7 +73,7 @@ }; panel: panel { - compatible = "edt,etm0700g0edh6", "simple-panel"; + compatible = "edt,etm0700g0edh6"; backlight = <&backlight>; enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; power-supply = <®_3v3>; -- cgit v1.2.3 From 1b9f0ec81af0012aae30aa3b4c711ad71d42e246 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Mon, 20 Mar 2023 18:03:31 +0100 Subject: ARM: dts: stm32: fix spi1 pin assignment on stm32mp15 Bank A and B IOs can't be handled by the pin controller 'Z'. This patch assign spi1 pin definition to the correct controller. Fixes: 9ad65d245b7b ("ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group") Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index a9d2bec99014..e15a3b2a9b39 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1880,6 +1880,21 @@ }; }; + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = , /* SPI2_SCK */ @@ -2448,19 +2463,4 @@ bias-disable; }; }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI1_MISO */ - bias-disable; - }; - }; }; -- cgit v1.2.3 From 76afff432f262712044864e3835841b1b41835a9 Mon Sep 17 00:00:00 2001 From: Roan van Dijk Date: Tue, 28 Mar 2023 11:33:11 +0200 Subject: ARM: stm32: add support for STM32MP151 This patch adds initial support of STM32MP151 microprocessor (MPU) based on Arm Cortex-A7. New Cortex-A infrastructure (gic, timer,...) are selected if ARCH_MULTI_V7 is defined. Signed-off-by: David Jander Signed-off-by: Roan van Dijk Signed-off-by: Alexandre Torgue --- arch/arm/mach-stm32/board-dt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c index 2ccaa11aaa56..5dcc4ddd1a56 100644 --- a/arch/arm/mach-stm32/board-dt.c +++ b/arch/arm/mach-stm32/board-dt.c @@ -21,6 +21,7 @@ static const char *const stm32_compat[] __initconst = { "st,stm32mp131", "st,stm32mp133", "st,stm32mp135", + "st,stm32mp151", "st,stm32mp157", NULL }; -- cgit v1.2.3 From dcbce56cac2676a6ca1ca33f352c8d46dd9626d6 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:18 +0200 Subject: ARM: dts: stm32: fix slew-rate of USART2 on stm32mp15xx-dkx On stm32mp15xx-dkx boards: - Fix slew-rate of USART 2 to 0 like other USARTs, because frequency of USART pins doesn't exceed 10Mhz. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index e15a3b2a9b39..e86d989dd351 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2178,7 +2178,7 @@ ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins2 { pinmux = , /* USART2_RX */ @@ -2196,7 +2196,7 @@ pinmux = ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins3 { pinmux = ; /* USART2_RX */ -- cgit v1.2.3 From abf52335762e7048e9fa5bc6f4c56a3e63b5bc80 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:19 +0200 Subject: ARM: dts: stm32: clean uart aliases on stm32mp15xx-dkx boards Remove duplicates and clean uart aliases. Uart aliases and uart pins should be declared and associated to uart instance at the same time. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1.dts | 3 --- arch/arm/boot/dts/stm32mp157c-dk2.dts | 3 --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 6 ++++++ 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 4c8be9c8eb20..0da3667ab1e0 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -17,9 +17,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; }; chosen { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 2bc92ef3aeb9..ab13e340f4ef 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -18,9 +18,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; serial3 = &usart2; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 11370ae0d868..ded5ab9a4798 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -8,6 +8,12 @@ #include / { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; -- cgit v1.2.3 From 92fd4848a181e1d8c118106d222d01a5172325d0 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:20 +0200 Subject: ARM: dts: stm32: clean uart aliases on stm32mp15xx-exx boards Remove duplicates and clean uart aliases. Uart aliases and uart pins should be declared and associated to uart instance at the same time. Put also aliases node above chosen node as same as stm32mp157c-dk2.dts. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 8 ++++---- arch/arm/boot/dts/stm32mp157c-ev1.dts | 9 ++++----- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index b1eb688a278a..2dfde6292668 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -16,6 +16,10 @@ model = "STMicroelectronics STM32MP157C eval daughter"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + aliases { + serial0 = &uart4; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -72,10 +76,6 @@ }; }; - aliases { - serial0 = &uart4; - }; - sd_switch: regulator-sd_switch { compatible = "regulator-gpio"; regulator-name = "sd_switch"; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 542226cfcfdf..ba8e9d9a42fa 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -14,16 +14,15 @@ model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { - serial0 = &uart4; serial1 = &usart3; ethernet0 = ðernet0; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + clocks { clk_ext_camera: clk-ext-camera { #clock-cells = <0>; -- cgit v1.2.3 From c1689f854cb9daa5f2ea098462107969452b0492 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:21 +0200 Subject: ARM: dts: stm32: add uart nodes on stm32mp13 Update device-tree stm32mp131.dtsi to add some uart features. On uart 1, 2, 3, 5, 6, 7, 8 nodes, add compabible, exti interrupts, clock, reset properties, dma config. On uart 4 node, only add dma configuration and use exti interrupt. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 97 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 5949473cbbfd..9ea61687f023 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -397,12 +397,42 @@ status = "disabled"; }; + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x5>, + <&dmamux1 46 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; - interrupts = ; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; resets = <&rcc UART4_R>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x5>, + <&dmamux1 64 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x5>, + <&dmamux1 66 0x400 0x1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -442,6 +472,32 @@ status = "disabled"; }; + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x5>, + <&dmamux1 80 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x5>, + <&dmamux1 82 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timers1: timer@44000000 { #address-cells = <1>; #size-cells = <0>; @@ -524,6 +580,19 @@ }; }; + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x5>, + <&dmamux1 72 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s1: audio-controller@44004000 { compatible = "st,stm32h7-i2s"; reg = <0x44004000 0x400>; @@ -748,6 +817,32 @@ status = "disabled"; }; + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s4: audio-controller@4c002000 { compatible = "st,stm32h7-i2s"; reg = <0x4c002000 0x400>; -- cgit v1.2.3 From 8d696053f308cb5b242fb5b7f66500310b3087a1 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:22 +0200 Subject: ARM: dts: stm32: add pins for usart2/1/4/8 in stm32mp13-pinctrl Add pins for uart4, uart8, usart1 and usart2 in stm32mp13-pinctrl.dtsi Theses pins have three states: default, sleep and idle. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 129 +++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index b2dce3a29f39..27e0c3826789 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -258,4 +258,133 @@ bias-disable; }; }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = ; /* UART8_TX */ + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = , /* UART8_TX */ + ; /* UART8_RX */ + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_TX */ + , /* USART1_RTS */ + , /* USART1_CTS_NSS */ + ; /* USART1_RX */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; }; -- cgit v1.2.3 From 623ac593a360f5c5fe34a002d006844f087549ce Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:23 +0200 Subject: ARM: dts: stm32: add uart nodes and uart aliases on stm32mp135f-dk Update device-tree stm32mp135f-dk.dts to add usart1, uart8, usart2 and uart aliases. - Usart2 is used to interface a BT device, enable it by default. - Usart1 and uart8 are available on expansion connector. They are kept disabled. So, the pins are kept in analog state to lower power consumption by default or can be used as GPIO. - Uart4 is used for console. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 42 +++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index c40686cb2b9a..f0900ca672b5 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -19,6 +19,13 @@ aliases { serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; memory@c0000000 { @@ -267,8 +274,41 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + pinctrl-2 = <&usart2_idle_pins_a>; + uart-has-rtscts; status = "okay"; }; -- cgit v1.2.3 From 3c3e8a92ae57e5d5cc03abdf15970432d80ac4a5 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 3 Apr 2023 09:54:15 +0200 Subject: ARM: dts: stm32: YAML validation fails for STM32MP15 ST Boards "make dtbs_check" gives following output : stm32mp157x-xxx.dt.yaml: gpu@59000000: 'contiguous-area' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml Solve this trouble for STM32MPU Boards : - stm32mp157c-ed1 - stm32mp157x-dkx Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 9 --------- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 9 --------- 2 files changed, 18 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 2dfde6292668..8beb901be506 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -69,11 +69,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@e8000000 { - reg = <0xe8000000 0x8000000>; - no-map; - }; }; sd_switch: regulator-sd_switch { @@ -140,10 +135,6 @@ status = "okay"; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index ded5ab9a4798..cefeeb00fc22 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -59,11 +59,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; }; led { @@ -157,10 +152,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; -- cgit v1.2.3 From 84a34e1862aae43e4dcdfb743a7dd3ade1fe4a3c Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 3 Apr 2023 09:58:31 +0200 Subject: ARM: dts: stm32: YAML validation fails for Odyssey Boards "make dtbs_check" gives following output : stm32mp157c-odyssey.dt.yaml: gpu@59000000: 'contiguous-area' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi index 2d9461006810..e22871dc580c 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -62,11 +62,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; }; led { @@ -80,11 +75,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; - status = "okay"; -}; - &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; -- cgit v1.2.3 From fc8d2b21bc5d5d7a6eadaa8c2a5d2e6856689480 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 3 Apr 2023 10:01:06 +0200 Subject: ARM: dts: stm32: YAML validation fails for Argon Boards "make dtbs_check" gives following output : stm32mp157c-emstamp-argon.dtb: gpu@59000000: 'contiguous-area' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index 7d11c50b9e40..b01470a9a3d5 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -68,11 +68,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@dc000000 { - reg = <0xdc000000 0x4000000>; - no-map; - }; }; led: gpio_leds { @@ -183,10 +178,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; -- cgit v1.2.3 From 645a603783633a9d6e2bbaaa98d4cac847d97b2c Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Tue, 28 Mar 2023 19:07:11 +0200 Subject: ARM: dts: stm32: add FMC support on STM32MP13x SoC family Add FMC support on STM32MP13x SoC family. Signed-off-by: Christophe Kerello Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 9ea61687f023..7ea1fe0cd070 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -1232,6 +1232,39 @@ dma-requests = <48>; }; + fmc: memory-controller@58002000 { + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + #address-cells = <2>; + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + nand-controller@4,0 { + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, + <&mdma 24 0x2 0x12000a08 0x0 0x0>, + <&mdma 25 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x20253180>; -- cgit v1.2.3 From 8768487fc6cc5ed13705978057f1cfa3e1ce1e4c Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 31 Mar 2023 09:19:07 +0200 Subject: ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family Add QSPI support on STM32MP13x SoC family Signed-off-by: Patrice Chotard Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 7ea1fe0cd070..d163c267e34c 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -1265,6 +1265,21 @@ }; }; + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, + <&mdma 26 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x20253180>; -- cgit v1.2.3 From 49f1d0b65f87692a11386a8b8cd3a4aa3a1d0daa Mon Sep 17 00:00:00 2001 From: Roan van Dijk Date: Thu, 30 Mar 2023 11:16:13 +0200 Subject: ARM: stm32: add initial documentation for STM32MP151 This patch adds initial documentation of STM32MP151 microprocessor (MPU) based on Arm Cortex-A7. Signed-off-by: Roan van Dijk Signed-off-by: Alexandre Torgue --- Documentation/arm/index.rst | 1 + Documentation/arm/stm32/stm32mp151-overview.rst | 36 +++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 Documentation/arm/stm32/stm32mp151-overview.rst diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index ae42fe886f0d..056ac11372af 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -58,6 +58,7 @@ SoC-specific documents stm32/stm32f769-overview stm32/stm32f429-overview stm32/stm32mp13-overview + stm32/stm32mp151-overview stm32/stm32mp157-overview stm32/stm32-dma-mdma-chaining diff --git a/Documentation/arm/stm32/stm32mp151-overview.rst b/Documentation/arm/stm32/stm32mp151-overview.rst new file mode 100644 index 000000000000..f42a2ac309c0 --- /dev/null +++ b/Documentation/arm/stm32/stm32mp151-overview.rst @@ -0,0 +1,36 @@ +=================== +STM32MP151 Overview +=================== + +Introduction +------------ + +The STM32MP151 is a Cortex-A MPU aimed at various applications. +It features: + +- Single Cortex-A7 application core +- Standard memories interface support +- Standard connectivity, widely inherited from the STM32 MCU family +- Comprehensive security support + +More details: + +- Cortex-A7 core running up to @800MHz +- FMC controller to connect SDRAM, NOR and NAND memories +- QSPI +- SD/MMC/SDIO support +- Ethernet controller +- ADC/DAC +- USB EHCI/OHCI controllers +- USB OTG +- I2C, SPI busses support +- Several general purpose timers +- Serial Audio interface +- LCD-TFT controller +- DCMIPP +- SPDIFRX +- DFSDM + +:Authors: + +- Roan van Dijk -- cgit v1.2.3