From 1ce7587e507e1762df1dadc22affcd41376040d5 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 30 Jan 2024 09:50:32 +0800 Subject: riscv: dts: add reset generator for Sophgo SG2042 SoC Add reset generator node to device tree for SG2042. Signed-off-by: Chen Wang Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/b2f5d7cd2d3fccfc00cf4563d2dd7363b0fa2fca.1706577450.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index ead1cc35d88b..eeb341e16bfd 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -6,6 +6,8 @@ /dts-v1/; #include +#include + #include "sg2042-cpus.dtsi" / { @@ -327,6 +329,12 @@ riscv,ndev = <224>; }; + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; + #reset-cells = <1>; + }; + uart0: serial@7040000000 { compatible = "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>; -- cgit v1.2.3 From 08573ba006ab7bc29c183e0b3c362a0b34f1d87b Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 30 Jan 2024 09:50:51 +0800 Subject: riscv: dts: add resets property for uart node Add resets property for uart0 for completeness, although it is deasserted by default. Signed-off-by: Chen Wang Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/807f75e433a0f900da40ebb6a448349c98580072.1706577450.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index eeb341e16bfd..81fda312f988 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -343,6 +343,7 @@ clock-frequency = <500000000>; reg-shift = <2>; reg-io-width = <4>; + resets = <&rstgen RST_UART0>; status = "disabled"; }; }; -- cgit v1.2.3 From 0f46e1339ef113f0dedf7ad376452cc722dbcfe6 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 30 Jan 2024 09:40:42 +0800 Subject: MAINTAINERS: Setup proper info for SOPHGO vendor support Add git tree that maintaines sophgo vendor code. Also replace Chao Wei with myself, since he does not have enough time. Since sophgo vendor code is maintained, remove itself from `RISC-V MISC SOC` Acked-by: Chao Wei Reviewed-by: Chen Wang Acked-by: Conor Dooley Link: https://lore.kernel.org/r/IA1PR20MB4953B158F6F575840F3D4267BB7D2@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- MAINTAINERS | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8999497011a2..e5e6cbb298c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18848,6 +18848,7 @@ F: Documentation/devicetree/bindings/riscv/ F: arch/riscv/boot/dts/ X: arch/riscv/boot/dts/allwinner/ X: arch/riscv/boot/dts/renesas/ +X: arch/riscv/boot/dts/sophgo/ RISC-V PMU DRIVERS M: Atish Patra @@ -20446,12 +20447,13 @@ F: drivers/char/sonypi.c F: drivers/platform/x86/sony-laptop.c F: include/linux/sony-laptop.h -SOPHGO DEVICETREES -M: Chao Wei +SOPHGO DEVICETREES and DRIVERS M: Chen Wang +M: Inochi Amaoto +T: git https://github.com/sophgo/linux.git S: Maintained -F: arch/riscv/boot/dts/sophgo/ -F: Documentation/devicetree/bindings/riscv/sophgo.yaml +N: sophgo +K: sophgo SOUND M: Jaroslav Kysela -- cgit v1.2.3