From 076fb0c4b6e1f6883477d1e4ee89464924e64737 Mon Sep 17 00:00:00 2001 From: Frank Rowand Date: Thu, 22 Jun 2017 09:15:39 -0700 Subject: of: update ePAPR references to point to Devicetree Specification The Devicetree Specification has superseded the ePAPR as the base specification for bindings. Update files in Documentation to reference the new document. First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt is generic, remove it. Some files are not updated because there is no hypervisor chapter in the Devicetree Specification: Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt Documenation/virtual/kvm/api.txt Documenation/virtual/kvm/ppc-pv.txt Signed-off-by: Frank Rowand Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/arm/l2c2x0.txt') diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index d9650c1788f4..fbe6cb21f4cf 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -4,8 +4,8 @@ ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ PL310 and variants) based level 2 cache controller. All these various implementations of the L2 cache controller have compatible programming models (Note 1). Some of the properties that are just prefixed "cache-*" are taken from section -3.7.3 of the ePAPR v1.1 specification which can be found at: -https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf +3.7.3 of the Devicetree Specification which can be found at: +https://www.devicetree.org/specifications/ The ARM L2 cache representation in the device tree should be done as follows: -- cgit v1.2.3