From 12bf2f9f7fdd3709b327fa1a62f63fa6100bc26f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Jan 2022 13:46:55 +0000 Subject: dt-bindings: dma: rz-dmac: Document RZ/V2L SoC Document RZ/V2L DMAC bindings. RZ/V2L DMAC is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,rz-dmac" will be used as a fallback. Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20220110134659.30424-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index 7a4f415d74dc..e353377084aa 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L DMA Controller +title: Renesas RZ/{G2L,V2L} DMA Controller maintainers: - Biju Das @@ -17,6 +17,7 @@ properties: items: - enum: - renesas,r9a07g044-dmac # RZ/G2{L,LC} + - renesas,r9a07g054-dmac # RZ/V2L - const: renesas,rz-dmac reg: -- cgit v1.2.3 From 614c8beca7cd6e7093385c88da800e258b7eb0ca Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 6 Feb 2022 20:03:08 +0000 Subject: dt-bindings: dma: rz-dmac: Document RZ/G2UL SoC Document RZ/G2UL DMAC bindings. RZ/G2UL DMAC is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,rz-dmac" will be used as a fallback. Signed-off-by: Biju Das Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220206200308.14315-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index e353377084aa..1e25c5b0fb4d 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/{G2L,V2L} DMA Controller +title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller maintainers: - Biju Das @@ -16,6 +16,7 @@ properties: compatible: items: - enum: + - renesas,r9a07g043-dmac # RZ/G2UL - renesas,r9a07g044-dmac # RZ/G2{L,LC} - renesas,r9a07g054-dmac # RZ/V2L - const: renesas,rz-dmac -- cgit v1.2.3 From 9c391cebedf59a13d2fb3176bc010edbffb317af Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 17 Feb 2022 10:52:42 +0100 Subject: dt-bindings: dma: Convert mtk-uart-apdma to DT schema Convert the MediaTek UART APDMA Controller binding to DT schema. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220217095242.13761-1-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/mediatek,uart-dma.yaml | 122 +++++++++++++++++++++ .../devicetree/bindings/dma/mtk-uart-apdma.txt | 56 ---------- 2 files changed, 122 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml delete mode 100644 Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml new file mode 100644 index 000000000000..54d68fc688b5 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek UART APDMA controller + +maintainers: + - Long Cheng + +description: | + The MediaTek UART APDMA controller provides DMA capabilities + for the UART peripheral bus. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2712-uart-dma + - mediatek,mt8516-uart-dma + - const: mediatek,mt6577-uart-dma + - enum: + - mediatek,mt6577-uart-dma + + reg: + minItems: 1 + maxItems: 16 + + interrupts: + description: | + TX, RX interrupt lines for each UART APDMA channel + minItems: 1 + maxItems: 16 + + clocks: + description: Must contain one entry for the APDMA main clock + maxItems: 1 + + clock-names: + const: apdma + + "#dma-cells": + const: 1 + description: | + The first cell specifies the UART APDMA channel number + + dma-requests: + description: | + Number of virtual channels of the UART APDMA controller + maximum: 16 + + mediatek,dma-33bits: + type: boolean + description: Enable 33-bits UART APDMA support + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +if: + not: + required: + - dma-requests +then: + properties: + interrupts: + maxItems: 8 + reg: + maxItems: 8 + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + apdma: dma-controller@11000400 { + compatible = "mediatek,mt2712-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000400 0 0x80>, + <0 0x11000480 0 0x80>, + <0 0x11000500 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>, + <0 0x11000680 0 0x80>, + <0 0x11000700 0 0x80>, + <0 0x11000780 0 0x80>, + <0 0x11000800 0 0x80>, + <0 0x11000880 0 0x80>, + <0 0x11000900 0 0x80>, + <0 0x11000980 0 0x80>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-requests = <12>; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + mediatek,dma-33bits; + #dma-cells = <1>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt deleted file mode 100644 index fef9c1eeb264..000000000000 --- a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Mediatek UART APDMA Controller - -Required properties: -- compatible should contain: - * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA - * "mediatek,mt6577-uart-dma" for MT6577 and all of the above - * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC - -- reg: The base address of the APDMA register bank. - -- interrupts: A single interrupt specifier. - One interrupt per dma-requests, or 8 if no dma-requests property is present - -- dma-requests: The number of DMA channels - -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: The APDMA clock for register accesses - -- mediatek,dma-33bits: Present if the DMA requires support - -Examples: - - apdma: dma-controller@11000400 { - compatible = "mediatek,mt2712-uart-dma", - "mediatek,mt6577-uart-dma"; - reg = <0 0x11000400 0 0x80>, - <0 0x11000480 0 0x80>, - <0 0x11000500 0 0x80>, - <0 0x11000580 0 0x80>, - <0 0x11000600 0 0x80>, - <0 0x11000680 0 0x80>, - <0 0x11000700 0 0x80>, - <0 0x11000780 0 0x80>, - <0 0x11000800 0 0x80>, - <0 0x11000880 0 0x80>, - <0 0x11000900 0 0x80>, - <0 0x11000980 0 0x80>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - dma-requests = <12>; - clocks = <&pericfg CLK_PERI_AP_DMA>; - clock-names = "apdma"; - mediatek,dma-33bits; - #dma-cells = <1>; - }; -- cgit v1.2.3