From 57f019864b634a3b38f8ab3ebf425695b0607c25 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 1 Dec 2022 16:41:52 -0500 Subject: drm/amdgpu: add GART, GPUVM, and GTT to glossary MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add definitions to clarify GPU virtual memory. v2: clarify the terms a bit more Reviewed-by: Christian König Reviewed-by: Luben Tuikov Suggested-by: Peter Maucher Signed-off-by: Alex Deucher Link: https://lore.kernel.org/r/20221201214153.8453-1-alexander.deucher@amd.com --- Documentation/gpu/amdgpu/amdgpu-glossary.rst | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'Documentation/gpu/amdgpu') diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index 326896e9800d..00a47ebb0b0f 100644 --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst @@ -30,12 +30,35 @@ we have a dedicated glossary for Display Core at EOP End Of Pipe/Pipeline + GART + Graphics Address Remapping Table. This is the name we use for the GPUVM + page table used by the GPU kernel driver. It remaps system resources + (memory or MMIO space) into the GPU's address space so the GPU can access + them. The name GART harkens back to the days of AGP when the platform + provided an MMU that the GPU could use to get a contiguous view of + scattered pages for DMA. The MMU has since moved on to the GPU, but the + name stuck. + GC Graphics and Compute GMC Graphic Memory Controller + GPUVM + GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple + virtual address spaces that can be in flight at any given time. These + allow the GPU to remap VRAM and system resources into GPU virtual address + spaces for use by the GPU kernel driver and applications using the GPU. + These provide memory protection for different applications using the GPU. + + GTT + Graphics Translation Tables. This is a memory pool managed through TTM + which provides access to system resources (memory or MMIO space) for + use by the GPU. These addresses can be mapped into the "GART" GPUVM page + table for use by the kernel driver or into per process GPUVM page tables + for application usage. + IH Interrupt Handler -- cgit v1.2.3