From 1aa63d4eb88167612be78e3b5a986b996544dca3 Mon Sep 17 00:00:00 2001 From: Zang Leigang Date: Thu, 16 Mar 2023 10:45:19 +0800 Subject: docs/zh_CN: fix a wrong format Add a missing markup for the code snippet at the end of lru_sort.rst Signed-off-by: Zang Leigang Reviewed-by: Alex Shi Link: https://lore.kernel.org/r/20230316024519.27992-1-zangleigang@hisilicon.com Signed-off-by: Jonathan Corbet --- Documentation/translations/zh_CN/admin-guide/mm/damon/lru_sort.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/translations/zh_CN') diff --git a/Documentation/translations/zh_CN/admin-guide/mm/damon/lru_sort.rst b/Documentation/translations/zh_CN/admin-guide/mm/damon/lru_sort.rst index 812ef315c8f6..03d33c710604 100644 --- a/Documentation/translations/zh_CN/admin-guide/mm/damon/lru_sort.rst +++ b/Documentation/translations/zh_CN/admin-guide/mm/damon/lru_sort.rst @@ -250,7 +250,7 @@ LRU的优先级的提升，同时降低那些超过120秒无人访问的内存 理被限制在最多1%的CPU以避免DAMON_LRU_SORT消费过多CPU时间。在系统空闲内存超过50% 时DAMON_LRU_SORT停止工作，并在低于40%时重新开始工作。如果DAMON_RECLAIM没有取得 进展且空闲内存低于20%，再次让DAMON_LRU_SORT停止工作，以此回退到以LRU链表为基础 -以页面为单位的内存回收上。 +以页面为单位的内存回收上。 :: # cd /sys/modules/damon_lru_sort/parameters # echo 500 > hot_thres_access_freq -- cgit v1.2.3 From 0c25e10091111cd4af2a979fbe77f438f1921788 Mon Sep 17 00:00:00 2001 From: Jonathan Corbet Date: Thu, 23 Mar 2023 15:08:04 -0600 Subject: docs: zh_CN: create the architecture-specific top-level directory This mirrors commit 4f1bb0386dfc ("docs: create a top-level arch/ directory"), creating a top-level directory to hold architecture-specific documentation. Acked-by: Alex Shi Reviewed-by: Yanteng Si Signed-off-by: Jonathan Corbet --- Documentation/translations/zh_CN/arch.rst | 29 ------------------------- Documentation/translations/zh_CN/arch/index.rst | 29 +++++++++++++++++++++++++ Documentation/translations/zh_CN/index.rst | 2 +- 3 files changed, 30 insertions(+), 30 deletions(-) delete mode 100644 Documentation/translations/zh_CN/arch.rst create mode 100644 Documentation/translations/zh_CN/arch/index.rst (limited to 'Documentation/translations/zh_CN') diff --git a/Documentation/translations/zh_CN/arch.rst b/Documentation/translations/zh_CN/arch.rst deleted file mode 100644 index 690e173d8b2a..000000000000 --- a/Documentation/translations/zh_CN/arch.rst +++ /dev/null @@ -1,29 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -处理器体系结构 -============== - -以下文档提供了具体架构实现的编程细节。 - -.. toctree:: - :maxdepth: 2 - - mips/index - arm64/index - riscv/index - openrisc/index - parisc/index - loongarch/index - -TODOList: - -* arm/index -* ia64/index -* m68k/index -* nios2/index -* powerpc/index -* s390/index -* sh/index -* sparc/index -* x86/index -* xtensa/index diff --git a/Documentation/translations/zh_CN/arch/index.rst b/Documentation/translations/zh_CN/arch/index.rst new file mode 100644 index 000000000000..aa53dcff268e --- /dev/null +++ b/Documentation/translations/zh_CN/arch/index.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0 + +处理器体系结构 +============== + +以下文档提供了具体架构实现的编程细节。 + +.. toctree:: + :maxdepth: 2 + + ../mips/index + ../arm64/index + ../riscv/index + ../openrisc/index + ../parisc/index + ../loongarch/index + +TODOList: + +* arm/index +* ia64/index +* m68k/index +* nios2/index +* powerpc/index +* s390/index +* sh/index +* sparc/index +* x86/index +* xtensa/index diff --git a/Documentation/translations/zh_CN/index.rst b/Documentation/translations/zh_CN/index.rst index 7c3216845b71..299704c0818d 100644 --- a/Documentation/translations/zh_CN/index.rst +++ b/Documentation/translations/zh_CN/index.rst @@ -120,7 +120,7 @@ TODOList: .. toctree:: :maxdepth: 2 - arch + arch/index 其他文档 -------- -- cgit v1.2.3 From 0e9ab8e4d44ae9d9aaf213bfd2c90bbe7289337b Mon Sep 17 00:00:00 2001 From: Jonathan Corbet Date: Thu, 23 Mar 2023 14:30:24 -0600 Subject: docs: move openrisc documentation under Documentation/arch/ Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Move Documentation/openrisc into arch/ and fix all in-tree references. Cc: Jonas Bonn Cc: Stefan Kristiansson Cc: Stafford Horne Acked-by: Alex Shi Reviewed-by: Yanteng Si Signed-off-by: Jonathan Corbet --- Documentation/arch/index.rst | 2 +- Documentation/arch/openrisc/features.rst | 3 + Documentation/arch/openrisc/index.rst | 20 ++++ Documentation/arch/openrisc/openrisc_port.rst | 121 ++++++++++++++++++++ Documentation/arch/openrisc/todo.rst | 15 +++ Documentation/openrisc/features.rst | 3 - Documentation/openrisc/index.rst | 20 ---- Documentation/openrisc/openrisc_port.rst | 121 -------------------- Documentation/openrisc/todo.rst | 15 --- Documentation/translations/zh_CN/arch/index.rst | 2 +- .../translations/zh_CN/arch/openrisc/index.rst | 32 ++++++ .../zh_CN/arch/openrisc/openrisc_port.rst | 127 +++++++++++++++++++++ .../translations/zh_CN/arch/openrisc/todo.rst | 23 ++++ .../translations/zh_CN/openrisc/index.rst | 32 ------ .../translations/zh_CN/openrisc/openrisc_port.rst | 127 --------------------- Documentation/translations/zh_CN/openrisc/todo.rst | 23 ---- MAINTAINERS | 2 +- 17 files changed, 344 insertions(+), 344 deletions(-) create mode 100644 Documentation/arch/openrisc/features.rst create mode 100644 Documentation/arch/openrisc/index.rst create mode 100644 Documentation/arch/openrisc/openrisc_port.rst create mode 100644 Documentation/arch/openrisc/todo.rst delete mode 100644 Documentation/openrisc/features.rst delete mode 100644 Documentation/openrisc/index.rst delete mode 100644 Documentation/openrisc/openrisc_port.rst delete mode 100644 Documentation/openrisc/todo.rst create mode 100644 Documentation/translations/zh_CN/arch/openrisc/index.rst create mode 100644 Documentation/translations/zh_CN/arch/openrisc/openrisc_port.rst create mode 100644 Documentation/translations/zh_CN/arch/openrisc/todo.rst delete mode 100644 Documentation/translations/zh_CN/openrisc/index.rst delete mode 100644 Documentation/translations/zh_CN/openrisc/openrisc_port.rst delete mode 100644 Documentation/translations/zh_CN/openrisc/todo.rst (limited to 'Documentation/translations/zh_CN') diff --git a/Documentation/arch/index.rst b/Documentation/arch/index.rst index 792f58e30f25..65945daa40fe 100644 --- a/Documentation/arch/index.rst +++ b/Documentation/arch/index.rst @@ -17,7 +17,7 @@ implementation. ../m68k/index ../mips/index ../nios2/index - ../openrisc/index + openrisc/index ../parisc/index ../powerpc/index ../riscv/index diff --git a/Documentation/arch/openrisc/features.rst b/Documentation/arch/openrisc/features.rst new file mode 100644 index 000000000000..3f7c40d219f2 --- /dev/null +++ b/Documentation/arch/openrisc/features.rst @@ -0,0 +1,3 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. kernel-feat:: $srctree/Documentation/features openrisc diff --git a/Documentation/arch/openrisc/index.rst b/Documentation/arch/openrisc/index.rst new file mode 100644 index 000000000000..6879f998b87a --- /dev/null +++ b/Documentation/arch/openrisc/index.rst @@ -0,0 +1,20 @@ +.. SPDX-License-Identifier: GPL-2.0 + +===================== +OpenRISC Architecture +===================== + +.. toctree:: + :maxdepth: 2 + + openrisc_port + todo + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/arch/openrisc/openrisc_port.rst b/Documentation/arch/openrisc/openrisc_port.rst new file mode 100644 index 000000000000..657ac4af7be6 --- /dev/null +++ b/Documentation/arch/openrisc/openrisc_port.rst @@ -0,0 +1,121 @@ +============== +OpenRISC Linux +============== + +This is a port of Linux to the OpenRISC class of microprocessors; the initial +target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). + +For information about OpenRISC processors and ongoing development: + + ======= ============================= + website https://openrisc.io + email openrisc@lists.librecores.org + ======= ============================= + +--------------------------------------------------------------------- + +Build instructions for OpenRISC toolchain and Linux +=================================================== + +In order to build and run Linux for OpenRISC, you'll need at least a basic +toolchain and, perhaps, the architectural simulator. Steps to get these bits +in place are outlined here. + +1) Toolchain + +Toolchain binaries can be obtained from openrisc.io or our github releases page. +Instructions for building the different toolchains can be found on openrisc.io +or Stafford's toolchain build and release scripts. + + ========== ================================================= + binaries https://github.com/openrisc/or1k-gcc/releases + toolchains https://openrisc.io/software + building https://github.com/stffrdhrn/or1k-toolchain-build + ========== ================================================= + +2) Building + +Build the Linux kernel as usual:: + + make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig + make ARCH=openrisc CROSS_COMPILE="or1k-linux-" + +3) Running on FPGA (optional) + +The OpenRISC community typically uses FuseSoC to manage building and programming +an SoC into an FPGA. The below is an example of programming a De0 Nano +development board with the OpenRISC SoC. During the build FPGA RTL is code +downloaded from the FuseSoC IP cores repository and built using the FPGA vendor +tools. Binaries are loaded onto the board with openocd. + +:: + + git clone https://github.com/olofk/fusesoc + cd fusesoc + sudo pip install -e . + + fusesoc init + fusesoc build de0_nano + fusesoc pgm de0_nano + + openocd -f interface/altera-usb-blaster.cfg \ + -f board/or1k_generic.cfg + + telnet localhost 4444 + > init + > halt; load_image vmlinux ; reset + +4) Running on a Simulator (optional) + +QEMU is a processor emulator which we recommend for simulating the OpenRISC +platform. Please follow the OpenRISC instructions on the QEMU website to get +Linux running on QEMU. You can build QEMU yourself, but your Linux distribution +likely provides binary packages to support OpenRISC. + + ============= ====================================================== + qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC + ============= ====================================================== + +--------------------------------------------------------------------- + +Terminology +=========== + +In the code, the following particles are used on symbols to limit the scope +to more or less specific processor implementations: + +========= ======================================= +openrisc: the OpenRISC class of processors +or1k: the OpenRISC 1000 family of processors +or1200: the OpenRISC 1200 processor +========= ======================================= + +--------------------------------------------------------------------- + +History +======== + +18-11-2003 Matjaz Breskvar (phoenix@bsemi.com) + initial port of linux to OpenRISC/or32 architecture. + all the core stuff is implemented and seams usable. + +08-12-2003 Matjaz Breskvar (phoenix@bsemi.com) + complete change of TLB miss handling. + rewrite of exceptions handling. + fully functional sash-3.6 in default initrd. + a much improved version with changes all around. + +10-04-2004 Matjaz Breskvar (phoenix@bsemi.com) + alot of bugfixes all over. + ethernet support, functional http and telnet servers. + running many standard linux apps. + +26-06-2004 Matjaz Breskvar (phoenix@bsemi.com) + port to 2.6.x + +30-11-2004 Matjaz Breskvar (phoenix@bsemi.com) + lots of bugfixes and enhancments. + added opencores framebuffer driver. + +09-10-2010 Jonas Bonn (jonas@southpole.se) + major rewrite to bring up to par with upstream Linux 2.6.36 diff --git a/Documentation/arch/openrisc/todo.rst b/Documentation/arch/openrisc/todo.rst new file mode 100644 index 000000000000..420b18b87eda --- /dev/null +++ b/Documentation/arch/openrisc/todo.rst @@ -0,0 +1,15 @@ +==== +TODO +==== + +The OpenRISC Linux port is fully functional and has been tracking upstream +since 2.6.35. There are, however, remaining items to be completed within +the coming months. Here's a list of known-to-be-less-than-stellar items +that are due for investigation shortly, i.e. our TODO list: + +- Implement the rest of the DMA API... dma_map_sg, etc. + +- Finish the renaming cleanup... there are references to or32 in the code + which was an older name for the architecture. The name we've settled on is + or1k and this change is slowly trickling through the stack. For the time + being, or32 is equivalent to or1k. diff --git a/Documentation/openrisc/features.rst b/Documentation/openrisc/features.rst deleted file mode 100644 index 3f7c40d219f2..000000000000 --- a/Documentation/openrisc/features.rst +++ /dev/null @@ -1,3 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. kernel-feat:: $srctree/Documentation/features openrisc diff --git a/Documentation/openrisc/index.rst b/Documentation/openrisc/index.rst deleted file mode 100644 index 6879f998b87a..000000000000 --- a/Documentation/openrisc/index.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -===================== -OpenRISC Architecture -===================== - -.. toctree:: - :maxdepth: 2 - - openrisc_port - todo - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/openrisc/openrisc_port.rst b/Documentation/openrisc/openrisc_port.rst deleted file mode 100644 index 657ac4af7be6..000000000000 --- a/Documentation/openrisc/openrisc_port.rst +++ /dev/null @@ -1,121 +0,0 @@ -============== -OpenRISC Linux -============== - -This is a port of Linux to the OpenRISC class of microprocessors; the initial -target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). - -For information about OpenRISC processors and ongoing development: - - ======= ============================= - website https://openrisc.io - email openrisc@lists.librecores.org - ======= ============================= - ---------------------------------------------------------------------- - -Build instructions for OpenRISC toolchain and Linux -=================================================== - -In order to build and run Linux for OpenRISC, you'll need at least a basic -toolchain and, perhaps, the architectural simulator. Steps to get these bits -in place are outlined here. - -1) Toolchain - -Toolchain binaries can be obtained from openrisc.io or our github releases page. -Instructions for building the different toolchains can be found on openrisc.io -or Stafford's toolchain build and release scripts. - - ========== ================================================= - binaries https://github.com/openrisc/or1k-gcc/releases - toolchains https://openrisc.io/software - building https://github.com/stffrdhrn/or1k-toolchain-build - ========== ================================================= - -2) Building - -Build the Linux kernel as usual:: - - make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig - make ARCH=openrisc CROSS_COMPILE="or1k-linux-" - -3) Running on FPGA (optional) - -The OpenRISC community typically uses FuseSoC to manage building and programming -an SoC into an FPGA. The below is an example of programming a De0 Nano -development board with the OpenRISC SoC. During the build FPGA RTL is code -downloaded from the FuseSoC IP cores repository and built using the FPGA vendor -tools. Binaries are loaded onto the board with openocd. - -:: - - git clone https://github.com/olofk/fusesoc - cd fusesoc - sudo pip install -e . - - fusesoc init - fusesoc build de0_nano - fusesoc pgm de0_nano - - openocd -f interface/altera-usb-blaster.cfg \ - -f board/or1k_generic.cfg - - telnet localhost 4444 - > init - > halt; load_image vmlinux ; reset - -4) Running on a Simulator (optional) - -QEMU is a processor emulator which we recommend for simulating the OpenRISC -platform. Please follow the OpenRISC instructions on the QEMU website to get -Linux running on QEMU. You can build QEMU yourself, but your Linux distribution -likely provides binary packages to support OpenRISC. - - ============= ====================================================== - qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC - ============= ====================================================== - ---------------------------------------------------------------------- - -Terminology -=========== - -In the code, the following particles are used on symbols to limit the scope -to more or less specific processor implementations: - -========= ======================================= -openrisc: the OpenRISC class of processors -or1k: the OpenRISC 1000 family of processors -or1200: the OpenRISC 1200 processor -========= ======================================= - ---------------------------------------------------------------------- - -History -======== - -18-11-2003 Matjaz Breskvar (phoenix@bsemi.com) - initial port of linux to OpenRISC/or32 architecture. - all the core stuff is implemented and seams usable. - -08-12-2003 Matjaz Breskvar (phoenix@bsemi.com) - complete change of TLB miss handling. - rewrite of exceptions handling. - fully functional sash-3.6 in default initrd. - a much improved version with changes all around. - -10-04-2004 Matjaz Breskvar (phoenix@bsemi.com) - alot of bugfixes all over. - ethernet support, functional http and telnet servers. - running many standard linux apps. - -26-06-2004 Matjaz Breskvar (phoenix@bsemi.com) - port to 2.6.x - -30-11-2004 Matjaz Breskvar (phoenix@bsemi.com) - lots of bugfixes and enhancments. - added opencores framebuffer driver. - -09-10-2010 Jonas Bonn (jonas@southpole.se) - major rewrite to bring up to par with upstream Linux 2.6.36 diff --git a/Documentation/openrisc/todo.rst b/Documentation/openrisc/todo.rst deleted file mode 100644 index 420b18b87eda..000000000000 --- a/Documentation/openrisc/todo.rst +++ /dev/null @@ -1,15 +0,0 @@ -==== -TODO -==== - -The OpenRISC Linux port is fully functional and has been tracking upstream -since 2.6.35. There are, however, remaining items to be completed within -the coming months. Here's a list of known-to-be-less-than-stellar items -that are due for investigation shortly, i.e. our TODO list: - -- Implement the rest of the DMA API... dma_map_sg, etc. - -- Finish the renaming cleanup... there are references to or32 in the code - which was an older name for the architecture. The name we've settled on is - or1k and this change is slowly trickling through the stack. For the time - being, or32 is equivalent to or1k. diff --git a/Documentation/translations/zh_CN/arch/index.rst b/Documentation/translations/zh_CN/arch/index.rst index aa53dcff268e..7e59af567331 100644 --- a/Documentation/translations/zh_CN/arch/index.rst +++ b/Documentation/translations/zh_CN/arch/index.rst @@ -11,7 +11,7 @@ ../mips/index ../arm64/index ../riscv/index - ../openrisc/index + openrisc/index ../parisc/index ../loongarch/index diff --git a/Documentation/translations/zh_CN/arch/openrisc/index.rst b/Documentation/translations/zh_CN/arch/openrisc/index.rst new file mode 100644 index 000000000000..da21f8ab894b --- /dev/null +++ b/Documentation/translations/zh_CN/arch/openrisc/index.rst @@ -0,0 +1,32 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/openrisc/index.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_openrisc_index: + +================= +OpenRISC 体系架构 +================= + +.. toctree:: + :maxdepth: 2 + + openrisc_port + todo + +Todolist: + features + + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/arch/openrisc/openrisc_port.rst b/Documentation/translations/zh_CN/arch/openrisc/openrisc_port.rst new file mode 100644 index 000000000000..cadc580fa23b --- /dev/null +++ b/Documentation/translations/zh_CN/arch/openrisc/openrisc_port.rst @@ -0,0 +1,127 @@ +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/openrisc/openrisc_port.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_openrisc_port: + +============== +OpenRISC Linux +============== + +这是Linux对OpenRISC类微处理器的移植；具体来说，最早移植目标是32位 +OpenRISC 1000系列（或1k）。 + +关于OpenRISC处理器和正在进行中的开发的信息: + + ======= ============================= + 网站 https://openrisc.io + 邮箱 openrisc@lists.librecores.org + ======= ============================= + +--------------------------------------------------------------------- + +OpenRISC工具链和Linux的构建指南 +=============================== + +为了构建和运行Linux for OpenRISC，你至少需要一个基本的工具链，或许 +还需要架构模拟器。 这里概述了准备就位这些部分的步骤。 + +1) 工具链 + +工具链二进制文件可以从openrisc.io或我们的github发布页面获得。不同 +工具链的构建指南可以在openrisc.io或Stafford的工具链构建和发布脚本 +中找到。 + + ====== ================================================= + 二进制 https://github.com/openrisc/or1k-gcc/releases + 工具链 https://openrisc.io/software + 构建 https://github.com/stffrdhrn/or1k-toolchain-build + ====== ================================================= + +2) 构建 + +像往常一样构建Linux内核:: + + make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig + make ARCH=openrisc CROSS_COMPILE="or1k-linux-" + +3) 在FPGA上运行（可选) + +OpenRISC社区通常使用FuseSoC来管理构建和编程SoC到FPGA中。 下面是用 +OpenRISC SoC对De0 Nano开发板进行编程的一个例子。 在构建过程中， +FPGA RTL是从FuseSoC IP核库中下载的代码，并使用FPGA供应商工具构建。 +二进制文件用openocd加载到电路板上。 + +:: + + git clone https://github.com/olofk/fusesoc + cd fusesoc + sudo pip install -e . + + fusesoc init + fusesoc build de0_nano + fusesoc pgm de0_nano + + openocd -f interface/altera-usb-blaster.cfg \ + -f board/or1k_generic.cfg + + telnet localhost 4444 + > init + > halt; load_image vmlinux ; reset + +4) 在模拟器上运行（可选） + +QEMU是一个处理器仿真器，我们推荐它来模拟OpenRISC平台。 请按照QEMU网 +站上的OpenRISC说明，让Linux在QEMU上运行。 你可以自己构建QEMU，但你的 +Linux发行版可能提供了支持OpenRISC的二进制包。 + + ============= ====================================================== + qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC + ============= ====================================================== + +--------------------------------------------------------------------- + +术语表 +====== + +代码中使用了以下符号约定以将范围限制在几个特定处理器实现上： + +========= ======================= +openrisc: OpenRISC类型处理器 +or1k: OpenRISC 1000系列处理器 +or1200: OpenRISC 1200处理器 +========= ======================= + +--------------------------------------------------------------------- + +历史 +==== + +2003-11-18 Matjaz Breskvar (phoenix@bsemi.com) + 将linux初步移植到OpenRISC或32架构。 + 所有的核心功能都实现了，并且可以使用。 + +2003-12-08 Matjaz Breskvar (phoenix@bsemi.com) + 彻底改变TLB失误处理。 + 重写异常处理。 + 在默认的initrd中实现了sash-3.6的所有功能。 + 大幅改进的版本。 + +2004-04-10 Matjaz Breskvar (phoenix@bsemi.com) + 大量的bug修复。 + 支持以太网，http和telnet服务器功能。 + 可以运行许多标准的linux应用程序。 + +2004-06-26 Matjaz Breskvar (phoenix@bsemi.com) + 移植到2.6.x。 + +2004-11-30 Matjaz Breskvar (phoenix@bsemi.com) + 大量的bug修复和增强功能。 + 增加了opencores framebuffer驱动。 + +2010-10-09 Jonas Bonn (jonas@southpole.se) + 重大重写，使其与上游的Linux 2.6.36看齐。 diff --git a/Documentation/translations/zh_CN/arch/openrisc/todo.rst b/Documentation/translations/zh_CN/arch/openrisc/todo.rst new file mode 100644 index 000000000000..1f6f95616633 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/openrisc/todo.rst @@ -0,0 +1,23 @@ +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/openrisc/todo.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_openrisc_todo.rst: + +======== +待办事项 +======== + +OpenRISC Linux的移植已经完全投入使用，并且从 2.6.35 开始就一直在上游同步。 +然而，还有一些剩余的项目需要在未来几个月内完成。 下面是一个即将进行调查的已知 +不尽完美的项目列表，即我们的待办事项列表。 + +- 实现其余的DMA API……dma_map_sg等。 + +- 完成重命名清理工作……代码中提到了or32，这是架构的一个老名字。 我们 + 已经确定的名字是or1k，这个改变正在以缓慢积累的方式进行。 目前，or32相当 + 于or1k。 diff --git a/Documentation/translations/zh_CN/openrisc/index.rst b/Documentation/translations/zh_CN/openrisc/index.rst deleted file mode 100644 index 9ad6cc600884..000000000000 --- a/Documentation/translations/zh_CN/openrisc/index.rst +++ /dev/null @@ -1,32 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/openrisc/index.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_openrisc_index: - -================= -OpenRISC 体系架构 -================= - -.. toctree:: - :maxdepth: 2 - - openrisc_port - todo - -Todolist: - features - - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/openrisc/openrisc_port.rst b/Documentation/translations/zh_CN/openrisc/openrisc_port.rst deleted file mode 100644 index b8a67670492d..000000000000 --- a/Documentation/translations/zh_CN/openrisc/openrisc_port.rst +++ /dev/null @@ -1,127 +0,0 @@ -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/openrisc/openrisc_port.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_openrisc_port: - -============== -OpenRISC Linux -============== - -这是Linux对OpenRISC类微处理器的移植；具体来说，最早移植目标是32位 -OpenRISC 1000系列（或1k）。 - -关于OpenRISC处理器和正在进行中的开发的信息: - - ======= ============================= - 网站 https://openrisc.io - 邮箱 openrisc@lists.librecores.org - ======= ============================= - ---------------------------------------------------------------------- - -OpenRISC工具链和Linux的构建指南 -=============================== - -为了构建和运行Linux for OpenRISC，你至少需要一个基本的工具链，或许 -还需要架构模拟器。 这里概述了准备就位这些部分的步骤。 - -1) 工具链 - -工具链二进制文件可以从openrisc.io或我们的github发布页面获得。不同 -工具链的构建指南可以在openrisc.io或Stafford的工具链构建和发布脚本 -中找到。 - - ====== ================================================= - 二进制 https://github.com/openrisc/or1k-gcc/releases - 工具链 https://openrisc.io/software - 构建 https://github.com/stffrdhrn/or1k-toolchain-build - ====== ================================================= - -2) 构建 - -像往常一样构建Linux内核:: - - make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig - make ARCH=openrisc CROSS_COMPILE="or1k-linux-" - -3) 在FPGA上运行（可选) - -OpenRISC社区通常使用FuseSoC来管理构建和编程SoC到FPGA中。 下面是用 -OpenRISC SoC对De0 Nano开发板进行编程的一个例子。 在构建过程中， -FPGA RTL是从FuseSoC IP核库中下载的代码，并使用FPGA供应商工具构建。 -二进制文件用openocd加载到电路板上。 - -:: - - git clone https://github.com/olofk/fusesoc - cd fusesoc - sudo pip install -e . - - fusesoc init - fusesoc build de0_nano - fusesoc pgm de0_nano - - openocd -f interface/altera-usb-blaster.cfg \ - -f board/or1k_generic.cfg - - telnet localhost 4444 - > init - > halt; load_image vmlinux ; reset - -4) 在模拟器上运行（可选） - -QEMU是一个处理器仿真器，我们推荐它来模拟OpenRISC平台。 请按照QEMU网 -站上的OpenRISC说明，让Linux在QEMU上运行。 你可以自己构建QEMU，但你的 -Linux发行版可能提供了支持OpenRISC的二进制包。 - - ============= ====================================================== - qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC - ============= ====================================================== - ---------------------------------------------------------------------- - -术语表 -====== - -代码中使用了以下符号约定以将范围限制在几个特定处理器实现上： - -========= ======================= -openrisc: OpenRISC类型处理器 -or1k: OpenRISC 1000系列处理器 -or1200: OpenRISC 1200处理器 -========= ======================= - ---------------------------------------------------------------------- - -历史 -==== - -2003-11-18 Matjaz Breskvar (phoenix@bsemi.com) - 将linux初步移植到OpenRISC或32架构。 - 所有的核心功能都实现了，并且可以使用。 - -2003-12-08 Matjaz Breskvar (phoenix@bsemi.com) - 彻底改变TLB失误处理。 - 重写异常处理。 - 在默认的initrd中实现了sash-3.6的所有功能。 - 大幅改进的版本。 - -2004-04-10 Matjaz Breskvar (phoenix@bsemi.com) - 大量的bug修复。 - 支持以太网，http和telnet服务器功能。 - 可以运行许多标准的linux应用程序。 - -2004-06-26 Matjaz Breskvar (phoenix@bsemi.com) - 移植到2.6.x。 - -2004-11-30 Matjaz Breskvar (phoenix@bsemi.com) - 大量的bug修复和增强功能。 - 增加了opencores framebuffer驱动。 - -2010-10-09 Jonas Bonn (jonas@southpole.se) - 重大重写，使其与上游的Linux 2.6.36看齐。 diff --git a/Documentation/translations/zh_CN/openrisc/todo.rst b/Documentation/translations/zh_CN/openrisc/todo.rst deleted file mode 100644 index 63c38717edb1..000000000000 --- a/Documentation/translations/zh_CN/openrisc/todo.rst +++ /dev/null @@ -1,23 +0,0 @@ -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/openrisc/todo.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_openrisc_todo.rst: - -======== -待办事项 -======== - -OpenRISC Linux的移植已经完全投入使用，并且从 2.6.35 开始就一直在上游同步。 -然而，还有一些剩余的项目需要在未来几个月内完成。 下面是一个即将进行调查的已知 -不尽完美的项目列表，即我们的待办事项列表。 - -- 实现其余的DMA API……dma_map_sg等。 - -- 完成重命名清理工作……代码中提到了or32，这是架构的一个老名字。 我们 - 已经确定的名字是or1k，这个改变正在以缓慢积累的方式进行。 目前，or32相当 - 于or1k。 diff --git a/MAINTAINERS b/MAINTAINERS index cf4eb913ea12..64ea94536f4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15638,7 +15638,7 @@ S: Maintained W: http://openrisc.io T: git https://github.com/openrisc/linux.git F: Documentation/devicetree/bindings/openrisc/ -F: Documentation/openrisc/ +F: Documentation/arch/openrisc/ F: arch/openrisc/ F: drivers/irqchip/irq-ompic.c F: drivers/irqchip/irq-or1k-* -- cgit v1.2.3 From 92b3de3f8ad7daddaf90ae7ce6162ca28db20370 Mon Sep 17 00:00:00 2001 From: Jonathan Corbet Date: Thu, 30 Mar 2023 13:28:50 -0600 Subject: docs: move parisc documentation under Documentation/arch/ Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Move Documentation/parisc into arch/ and fix all in-tree references. Cc: "James E.J. Bottomley" Cc: Helge Deller Cc: Alex Shi Reviewed-by: Yanteng Si Signed-off-by: Jonathan Corbet --- Documentation/arch/index.rst | 2 +- Documentation/arch/parisc/debugging.rst | 46 ++++++ Documentation/arch/parisc/features.rst | 3 + Documentation/arch/parisc/index.rst | 20 +++ Documentation/arch/parisc/registers.rst | 154 ++++++++++++++++++++ Documentation/parisc/debugging.rst | 46 ------ Documentation/parisc/features.rst | 3 - Documentation/parisc/index.rst | 20 --- Documentation/parisc/registers.rst | 154 -------------------- Documentation/translations/zh_CN/arch/index.rst | 2 +- .../translations/zh_CN/arch/parisc/debugging.rst | 45 ++++++ .../translations/zh_CN/arch/parisc/index.rst | 31 ++++ .../translations/zh_CN/arch/parisc/registers.rst | 156 +++++++++++++++++++++ .../translations/zh_CN/parisc/debugging.rst | 45 ------ Documentation/translations/zh_CN/parisc/index.rst | 31 ---- .../translations/zh_CN/parisc/registers.rst | 156 --------------------- MAINTAINERS | 2 +- 17 files changed, 458 insertions(+), 458 deletions(-) create mode 100644 Documentation/arch/parisc/debugging.rst create mode 100644 Documentation/arch/parisc/features.rst create mode 100644 Documentation/arch/parisc/index.rst create mode 100644 Documentation/arch/parisc/registers.rst delete mode 100644 Documentation/parisc/debugging.rst delete mode 100644 Documentation/parisc/features.rst delete mode 100644 Documentation/parisc/index.rst delete mode 100644 Documentation/parisc/registers.rst create mode 100644 Documentation/translations/zh_CN/arch/parisc/debugging.rst create mode 100644 Documentation/translations/zh_CN/arch/parisc/index.rst create mode 100644 Documentation/translations/zh_CN/arch/parisc/registers.rst delete mode 100644 Documentation/translations/zh_CN/parisc/debugging.rst delete mode 100644 Documentation/translations/zh_CN/parisc/index.rst delete mode 100644 Documentation/translations/zh_CN/parisc/registers.rst (limited to 'Documentation/translations/zh_CN') diff --git a/Documentation/arch/index.rst b/Documentation/arch/index.rst index 77e287c3eeb9..6839cd46850d 100644 --- a/Documentation/arch/index.rst +++ b/Documentation/arch/index.rst @@ -18,7 +18,7 @@ implementation. ../mips/index nios2/index openrisc/index - ../parisc/index + parisc/index ../powerpc/index ../riscv/index ../s390/index diff --git a/Documentation/arch/parisc/debugging.rst b/Documentation/arch/parisc/debugging.rst new file mode 100644 index 000000000000..de1b60402c5b --- /dev/null +++ b/Documentation/arch/parisc/debugging.rst @@ -0,0 +1,46 @@ +================= +PA-RISC Debugging +================= + +okay, here are some hints for debugging the lower-level parts of +linux/parisc. + + +1. Absolute addresses +===================== + +A lot of the assembly code currently runs in real mode, which means +absolute addresses are used instead of virtual addresses as in the +rest of the kernel. To translate an absolute address to a virtual +address you can lookup in System.map, add __PAGE_OFFSET (0x10000000 +currently). + + +2. HPMCs +======== + +When real-mode code tries to access non-existent memory, you'll get +an HPMC instead of a kernel oops. To debug an HPMC, try to find +the System Responder/Requestor addresses. The System Requestor +address should match (one of the) processor HPAs (high addresses in +the I/O range); the System Responder address is the address real-mode +code tried to access. + +Typical values for the System Responder address are addresses larger +than __PAGE_OFFSET (0x10000000) which mean a virtual address didn't +get translated to a physical address before real-mode code tried to +access it. + + +3. Q bit fun +============ + +Certain, very critical code has to clear the Q bit in the PSW. What +happens when the Q bit is cleared is the CPU does not update the +registers interruption handlers read to find out where the machine +was interrupted - so if you get an interruption between the instruction +that clears the Q bit and the RFI that sets it again you don't know +where exactly it happened. If you're lucky the IAOQ will point to the +instruction that cleared the Q bit, if you're not it points anywhere +at all. Usually Q bit problems will show themselves in unexplainable +system hangs or running off the end of physical memory. diff --git a/Documentation/arch/parisc/features.rst b/Documentation/arch/parisc/features.rst new file mode 100644 index 000000000000..501d7c450037 --- /dev/null +++ b/Documentation/arch/parisc/features.rst @@ -0,0 +1,3 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. kernel-feat:: $srctree/Documentation/features parisc diff --git a/Documentation/arch/parisc/index.rst b/Documentation/arch/parisc/index.rst new file mode 100644 index 000000000000..240685751825 --- /dev/null +++ b/Documentation/arch/parisc/index.rst @@ -0,0 +1,20 @@ +.. SPDX-License-Identifier: GPL-2.0 + +==================== +PA-RISC Architecture +==================== + +.. toctree:: + :maxdepth: 2 + + debugging + registers + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/arch/parisc/registers.rst b/Documentation/arch/parisc/registers.rst new file mode 100644 index 000000000000..59c8ecf3e856 --- /dev/null +++ b/Documentation/arch/parisc/registers.rst @@ -0,0 +1,154 @@ +================================ +Register Usage for Linux/PA-RISC +================================ + +[ an asterisk is used for planned usage which is currently unimplemented ] + +General Registers as specified by ABI +===================================== + +Control Registers +----------------- + +=============================== =============================================== +CR 0 (Recovery Counter) used for ptrace +CR 1-CR 7(undefined) unused +CR 8 (Protection ID) per-process value* +CR 9, 12, 13 (PIDS) unused +CR10 (CCR) lazy FPU saving* +CR11 as specified by ABI (SAR) +CR14 (interruption vector) initialized to fault_vector +CR15 (EIEM) initialized to all ones* +CR16 (Interval Timer) read for cycle count/write starts Interval Tmr +CR17-CR22 interruption parameters +CR19 Interrupt Instruction Register +CR20 Interrupt Space Register +CR21 Interrupt Offset Register +CR22 Interrupt PSW +CR23 (EIRR) read for pending interrupts/write clears bits +CR24 (TR 0) Kernel Space Page Directory Pointer +CR25 (TR 1) User Space Page Directory Pointer +CR26 (TR 2) not used +CR27 (TR 3) Thread descriptor pointer +CR28 (TR 4) not used +CR29 (TR 5) not used +CR30 (TR 6) current / 0 +CR31 (TR 7) Temporary register, used in various places +=============================== =============================================== + +Space Registers (kernel mode) +----------------------------- + +=============================== =============================================== +SR0 temporary space register +SR4-SR7 set to 0 +SR1 temporary space register +SR2 kernel should not clobber this +SR3 used for userspace accesses (current process) +=============================== =============================================== + +Space Registers (user mode) +--------------------------- + +=============================== =============================================== +SR0 temporary space register +SR1 temporary space register +SR2 holds space of linux gateway page +SR3 holds user address space value while in kernel +SR4-SR7 Defines short address space for user/kernel +=============================== =============================================== + + +Processor Status Word +--------------------- + +=============================== =============================================== +W (64-bit addresses) 0 +E (Little-endian) 0 +S (Secure Interval Timer) 0 +T (Taken Branch Trap) 0 +H (Higher-privilege trap) 0 +L (Lower-privilege trap) 0 +N (Nullify next instruction) used by C code +X (Data memory break disable) 0 +B (Taken Branch) used by C code +C (code address translation) 1, 0 while executing real-mode code +V (divide step correction) used by C code +M (HPMC mask) 0, 1 while executing HPMC handler* +C/B (carry/borrow bits) used by C code +O (ordered references) 1* +F (performance monitor) 0 +R (Recovery Counter trap) 0 +Q (collect interruption state) 1 (0 in code directly preceding an rfi) +P (Protection Identifiers) 1* +D (Data address translation) 1, 0 while executing real-mode code +I (external interrupt mask) used by cli()/sti() macros +=============================== =============================================== + +"Invisible" Registers +--------------------- + +=============================== =============================================== +PSW default W value 0 +PSW default E value 0 +Shadow Registers used by interruption handler code +TOC enable bit 1 +=============================== =============================================== + +------------------------------------------------------------------------- + +The PA-RISC architecture defines 7 registers as "shadow registers". +Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce +the state save and restore time by eliminating the need for general register +(GR) saves and restores in interruption handlers. +Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25. + +------------------------------------------------------------------------- + +Register usage notes, originally from John Marvin, with some additional +notes from Randolph Chung. + +For the general registers: + +r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of +course, you need to save them if you care about them, before calling +another procedure. Some of the above registers do have special meanings +that you should be aware of: + + r1: + The addil instruction is hardwired to place its result in r1, + so if you use that instruction be aware of that. + + r2: + This is the return pointer. In general you don't want to + use this, since you need the pointer to get back to your + caller. However, it is grouped with this set of registers + since the caller can't rely on the value being the same + when you return, i.e. you can copy r2 to another register + and return through that register after trashing r2, and + that should not cause a problem for the calling routine. + + r19-r22: + these are generally regarded as temporary registers. + Note that in 64 bit they are arg7-arg4. + + r23-r26: + these are arg3-arg0, i.e. you can use them if you + don't care about the values that were passed in anymore. + + r28,r29: + are ret0 and ret1. They are what you pass return values + in. r28 is the primary return. When returning small structures + r29 may also be used to pass data back to the caller. + + r30: + stack pointer + + r31: + the ble instruction puts the return pointer in here. + + + r3-r18,r27,r30 need to be saved and restored. r3-r18 are just + general purpose registers. r27 is the data pointer, and is + used to make references to global variables easier. r30 is + the stack pointer. diff --git a/Documentation/parisc/debugging.rst b/Documentation/parisc/debugging.rst deleted file mode 100644 index de1b60402c5b..000000000000 --- a/Documentation/parisc/debugging.rst +++ /dev/null @@ -1,46 +0,0 @@ -================= -PA-RISC Debugging -================= - -okay, here are some hints for debugging the lower-level parts of -linux/parisc. - - -1. Absolute addresses -===================== - -A lot of the assembly code currently runs in real mode, which means -absolute addresses are used instead of virtual addresses as in the -rest of the kernel. To translate an absolute address to a virtual -address you can lookup in System.map, add __PAGE_OFFSET (0x10000000 -currently). - - -2. HPMCs -======== - -When real-mode code tries to access non-existent memory, you'll get -an HPMC instead of a kernel oops. To debug an HPMC, try to find -the System Responder/Requestor addresses. The System Requestor -address should match (one of the) processor HPAs (high addresses in -the I/O range); the System Responder address is the address real-mode -code tried to access. - -Typical values for the System Responder address are addresses larger -than __PAGE_OFFSET (0x10000000) which mean a virtual address didn't -get translated to a physical address before real-mode code tried to -access it. - - -3. Q bit fun -============ - -Certain, very critical code has to clear the Q bit in the PSW. What -happens when the Q bit is cleared is the CPU does not update the -registers interruption handlers read to find out where the machine -was interrupted - so if you get an interruption between the instruction -that clears the Q bit and the RFI that sets it again you don't know -where exactly it happened. If you're lucky the IAOQ will point to the -instruction that cleared the Q bit, if you're not it points anywhere -at all. Usually Q bit problems will show themselves in unexplainable -system hangs or running off the end of physical memory. diff --git a/Documentation/parisc/features.rst b/Documentation/parisc/features.rst deleted file mode 100644 index 501d7c450037..000000000000 --- a/Documentation/parisc/features.rst +++ /dev/null @@ -1,3 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. kernel-feat:: $srctree/Documentation/features parisc diff --git a/Documentation/parisc/index.rst b/Documentation/parisc/index.rst deleted file mode 100644 index 240685751825..000000000000 --- a/Documentation/parisc/index.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -==================== -PA-RISC Architecture -==================== - -.. toctree:: - :maxdepth: 2 - - debugging - registers - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/parisc/registers.rst b/Documentation/parisc/registers.rst deleted file mode 100644 index 59c8ecf3e856..000000000000 --- a/Documentation/parisc/registers.rst +++ /dev/null @@ -1,154 +0,0 @@ -================================ -Register Usage for Linux/PA-RISC -================================ - -[ an asterisk is used for planned usage which is currently unimplemented ] - -General Registers as specified by ABI -===================================== - -Control Registers ------------------ - -=============================== =============================================== -CR 0 (Recovery Counter) used for ptrace -CR 1-CR 7(undefined) unused -CR 8 (Protection ID) per-process value* -CR 9, 12, 13 (PIDS) unused -CR10 (CCR) lazy FPU saving* -CR11 as specified by ABI (SAR) -CR14 (interruption vector) initialized to fault_vector -CR15 (EIEM) initialized to all ones* -CR16 (Interval Timer) read for cycle count/write starts Interval Tmr -CR17-CR22 interruption parameters -CR19 Interrupt Instruction Register -CR20 Interrupt Space Register -CR21 Interrupt Offset Register -CR22 Interrupt PSW -CR23 (EIRR) read for pending interrupts/write clears bits -CR24 (TR 0) Kernel Space Page Directory Pointer -CR25 (TR 1) User Space Page Directory Pointer -CR26 (TR 2) not used -CR27 (TR 3) Thread descriptor pointer -CR28 (TR 4) not used -CR29 (TR 5) not used -CR30 (TR 6) current / 0 -CR31 (TR 7) Temporary register, used in various places -=============================== =============================================== - -Space Registers (kernel mode) ------------------------------ - -=============================== =============================================== -SR0 temporary space register -SR4-SR7 set to 0 -SR1 temporary space register -SR2 kernel should not clobber this -SR3 used for userspace accesses (current process) -=============================== =============================================== - -Space Registers (user mode) ---------------------------- - -=============================== =============================================== -SR0 temporary space register -SR1 temporary space register -SR2 holds space of linux gateway page -SR3 holds user address space value while in kernel -SR4-SR7 Defines short address space for user/kernel -=============================== =============================================== - - -Processor Status Word ---------------------- - -=============================== =============================================== -W (64-bit addresses) 0 -E (Little-endian) 0 -S (Secure Interval Timer) 0 -T (Taken Branch Trap) 0 -H (Higher-privilege trap) 0 -L (Lower-privilege trap) 0 -N (Nullify next instruction) used by C code -X (Data memory break disable) 0 -B (Taken Branch) used by C code -C (code address translation) 1, 0 while executing real-mode code -V (divide step correction) used by C code -M (HPMC mask) 0, 1 while executing HPMC handler* -C/B (carry/borrow bits) used by C code -O (ordered references) 1* -F (performance monitor) 0 -R (Recovery Counter trap) 0 -Q (collect interruption state) 1 (0 in code directly preceding an rfi) -P (Protection Identifiers) 1* -D (Data address translation) 1, 0 while executing real-mode code -I (external interrupt mask) used by cli()/sti() macros -=============================== =============================================== - -"Invisible" Registers ---------------------- - -=============================== =============================================== -PSW default W value 0 -PSW default E value 0 -Shadow Registers used by interruption handler code -TOC enable bit 1 -=============================== =============================================== - -------------------------------------------------------------------------- - -The PA-RISC architecture defines 7 registers as "shadow registers". -Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce -the state save and restore time by eliminating the need for general register -(GR) saves and restores in interruption handlers. -Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25. - -------------------------------------------------------------------------- - -Register usage notes, originally from John Marvin, with some additional -notes from Randolph Chung. - -For the general registers: - -r1,r2,r19-r26,r28,r29 & r31 can be used without saving them first. And of -course, you need to save them if you care about them, before calling -another procedure. Some of the above registers do have special meanings -that you should be aware of: - - r1: - The addil instruction is hardwired to place its result in r1, - so if you use that instruction be aware of that. - - r2: - This is the return pointer. In general you don't want to - use this, since you need the pointer to get back to your - caller. However, it is grouped with this set of registers - since the caller can't rely on the value being the same - when you return, i.e. you can copy r2 to another register - and return through that register after trashing r2, and - that should not cause a problem for the calling routine. - - r19-r22: - these are generally regarded as temporary registers. - Note that in 64 bit they are arg7-arg4. - - r23-r26: - these are arg3-arg0, i.e. you can use them if you - don't care about the values that were passed in anymore. - - r28,r29: - are ret0 and ret1. They are what you pass return values - in. r28 is the primary return. When returning small structures - r29 may also be used to pass data back to the caller. - - r30: - stack pointer - - r31: - the ble instruction puts the return pointer in here. - - - r3-r18,r27,r30 need to be saved and restored. r3-r18 are just - general purpose registers. r27 is the data pointer, and is - used to make references to global variables easier. r30 is - the stack pointer. diff --git a/Documentation/translations/zh_CN/arch/index.rst b/Documentation/translations/zh_CN/arch/index.rst index 7e59af567331..908ea131bb1c 100644 --- a/Documentation/translations/zh_CN/arch/index.rst +++ b/Documentation/translations/zh_CN/arch/index.rst @@ -12,7 +12,7 @@ ../arm64/index ../riscv/index openrisc/index - ../parisc/index + parisc/index ../loongarch/index TODOList: diff --git a/Documentation/translations/zh_CN/arch/parisc/debugging.rst b/Documentation/translations/zh_CN/arch/parisc/debugging.rst new file mode 100644 index 000000000000..c6b9de6d3175 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/parisc/debugging.rst @@ -0,0 +1,45 @@ +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/parisc/debugging.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_parisc_debugging: + +================= +调试PA-RISC +================= + +好吧，这里有一些关于调试linux/parisc的较底层部分的信息。 + + +1. 绝对地址 +===================== + +很多汇编代码目前运行在实模式下，这意味着会使用绝对地址，而不是像内核其他 +部分那样使用虚拟地址。要将绝对地址转换为虚拟地址，你可以在System.map中查 +找，添加__PAGE_OFFSET（目前是0x10000000）。 + + +2. HPMCs +======== + +当实模式的代码试图访问不存在的内存时，会出现HPMC（high priority machine +check）而不是内核oops。若要调试HPMC，请尝试找到系统响应程序/请求程序地址。 +系统请求程序地址应该与（某）处理器的HPA（I/O范围内的高地址）相匹配；系统响应程 +序地址是实模式代码试图访问的地址。 + +系统响应程序地址的典型值是大于__PAGE_OFFSET （0x10000000）的地址，这意味着 +在实模式试图访问它之前，虚拟地址没有被翻译成物理地址。 + + +3. 有趣的Q位 +============ + +某些非常关键的代码必须清除PSW中的Q位。当Q位被清除时，CPU不会更新中断处理 +程序所读取的寄存器，以找出机器被中断的位置——所以如果你在清除Q位的指令和再 +次设置Q位的RFI之间遇到中断，你不知道它到底发生在哪里。如果你幸运的话，IAOQ +会指向清除Q位的指令，如果你不幸运的话，它会指向任何地方。通常Q位的问题会 +表现为无法解释的系统挂起或物理内存越界。 diff --git a/Documentation/translations/zh_CN/arch/parisc/index.rst b/Documentation/translations/zh_CN/arch/parisc/index.rst new file mode 100644 index 000000000000..9f69283bd1c9 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/parisc/index.rst @@ -0,0 +1,31 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/parisc/index.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_parisc_index: + +==================== +PA-RISC体系架构 +==================== + +.. toctree:: + :maxdepth: 2 + + debugging + registers + +Todolist: + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/arch/parisc/registers.rst b/Documentation/translations/zh_CN/arch/parisc/registers.rst new file mode 100644 index 000000000000..a55250afcc27 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/parisc/registers.rst @@ -0,0 +1,156 @@ +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/parisc/registers.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_parisc_registers: + +========================= +Linux/PA-RISC的寄存器用法 +========================= + +[ 用星号表示目前尚未实现的计划用途。 ] + +ABI约定的通用寄存器 +=================== + +控制寄存器 +---------- + +============================ ================================= +CR 0 (恢复计数器) 用于ptrace +CR 1-CR 7(无定义) 未使用 +CR 8 (Protection ID) 每进程值* +CR 9, 12, 13 (PIDS) 未使用 +CR10 (CCR) FPU延迟保存* +CR11 按照ABI的规定（SAR） +CR14 (中断向量) 初始化为 fault_vector +CR15 (EIEM) 所有位初始化为1* +CR16 (间隔计时器) 读取周期数/写入开始时间间隔计时器 +CR17-CR22 中断参数 +CR19 中断指令寄存器 +CR20 中断空间寄存器 +CR21 中断偏移量寄存器 +CR22 中断 PSW +CR23 (EIRR) 读取未决中断/写入清除位 +CR24 (TR 0) 内核空间页目录指针 +CR25 (TR 1) 用户空间页目录指针 +CR26 (TR 2) 不使用 +CR27 (TR 3) 线程描述符指针 +CR28 (TR 4) 不使用 +CR29 (TR 5) 不使用 +CR30 (TR 6) 当前 / 0 +CR31 (TR 7) 临时寄存器，在不同地方使用 +============================ ================================= + +空间寄存器（内核模式） +---------------------- + +======== ============================== +SR0 临时空间寄存器 +SR4-SR7 设置为0 +SR1 临时空间寄存器 +SR2 内核不应该破坏它 +SR3 用于用户空间访问（当前进程） +======== ============================== + +空间寄存器（用户模式） +---------------------- + +======== ============================ +SR0 临时空间寄存器 +SR1 临时空间寄存器 +SR2 保存Linux gateway page的空间 +SR3 在内核中保存用户地址空间的值 +SR4-SR7 定义了用户/内核的短地址空间 +======== ============================ + + +处理器状态字 +------------ + +====================== ================================================ +W （64位地址） 0 +E （小尾端） 0 +S （安全间隔计时器） 0 +T （产生分支陷阱） 0 +H （高特权级陷阱） 0 +L （低特权级陷阱） 0 +N （撤销下一条指令） 被C代码使用 +X （数据存储中断禁用） 0 +B （产生分支） 被C代码使用 +C （代码地址转译） 1, 在执行实模式代码时为0 +V （除法步长校正） 被C代码使用 +M （HPMC 掩码） 0, 在执行HPMC操作*时为1 +C/B （进/借 位） 被C代码使用 +O （有序引用） 1* +F （性能监视器） 0 +R （回收计数器陷阱） 0 +Q （收集中断状态） 1 （在rfi之前的代码中为0） +P （保护标识符） 1* +D （数据地址转译） 1, 在执行实模式代码时为0 +I （外部中断掩码） 由cli()/sti()宏使用。 +====================== ================================================ + +“隐形”寄存器（影子寄存器） +--------------------------- + +============= =================== +PSW W 默认值 0 +PSW E 默认值 0 +影子寄存器 被中断处理代码使用 +TOC启用位 1 +============= =================== + +---------------------------------------------------------- + +PA-RISC架构定义了7个寄存器作为“影子寄存器”。这些寄存器在 +RETURN FROM INTERRUPTION AND RESTORE指令中使用，通过消 +除中断处理程序中对一般寄存器（GR）的保存和恢复的需要来减 +少状态保存和恢复时间。影子寄存器是GRs 1, 8, 9, 16, 17, +24和25。 + +------------------------------------------------------------------------- + +寄存器使用说明，最初由John Marvin提供，并由Randolph Chung提供一些补充说明。 + +对于通用寄存器: + +r1,r2,r19-r26,r28,r29 & r31可以在不保存它们的情况下被使用。当然，如果你 +关心它们，在调用另一个程序之前，你也需要保存它们。上面的一些寄存器确实 +有特殊的含义，你应该注意一下: + + r1: + addil指令是硬性规定将其结果放在r1中，所以如果你使用这条指令要 + 注意这点。 + + r2: + 这就是返回指针。一般来说，你不想使用它，因为你需要这个指针来返 + 回给你的调用者。然而，它与这组寄存器组合在一起，因为调用者不能 + 依赖你返回时的值是相同的，也就是说，你可以将r2复制到另一个寄存 + 器，并在作废r2后通过该寄存器返回，这应该不会给调用程序带来问题。 + + r19-r22: + 这些通常被认为是临时寄存器。 + 请注意，在64位中它们是arg7-arg4。 + + r23-r26: + 这些是arg3-arg0，也就是说，如果你不再关心传入的值，你可以使用 + 它们。 + + r28,r29: + 这俩是ret0和ret1。它们是你传入返回值的地方。r28是主返回值。当返回 + 小结构体时，r29也可以用来将数据传回给调用程序。 + + r30: + 栈指针 + + r31: + ble指令将返回指针放在这里。 + + + r3-r18,r27,r30需要被保存和恢复。r3-r18只是一般用途的寄存器。 + r27是数据指针，用来使对全局变量的引用更容易。r30是栈指针。 diff --git a/Documentation/translations/zh_CN/parisc/debugging.rst b/Documentation/translations/zh_CN/parisc/debugging.rst deleted file mode 100644 index 68b73eb57105..000000000000 --- a/Documentation/translations/zh_CN/parisc/debugging.rst +++ /dev/null @@ -1,45 +0,0 @@ -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/parisc/debugging.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_parisc_debugging: - -================= -调试PA-RISC -================= - -好吧，这里有一些关于调试linux/parisc的较底层部分的信息。 - - -1. 绝对地址 -===================== - -很多汇编代码目前运行在实模式下，这意味着会使用绝对地址，而不是像内核其他 -部分那样使用虚拟地址。要将绝对地址转换为虚拟地址，你可以在System.map中查 -找，添加__PAGE_OFFSET（目前是0x10000000）。 - - -2. HPMCs -======== - -当实模式的代码试图访问不存在的内存时，会出现HPMC（high priority machine -check）而不是内核oops。若要调试HPMC，请尝试找到系统响应程序/请求程序地址。 -系统请求程序地址应该与（某）处理器的HPA（I/O范围内的高地址）相匹配；系统响应程 -序地址是实模式代码试图访问的地址。 - -系统响应程序地址的典型值是大于__PAGE_OFFSET （0x10000000）的地址，这意味着 -在实模式试图访问它之前，虚拟地址没有被翻译成物理地址。 - - -3. 有趣的Q位 -============ - -某些非常关键的代码必须清除PSW中的Q位。当Q位被清除时，CPU不会更新中断处理 -程序所读取的寄存器，以找出机器被中断的位置——所以如果你在清除Q位的指令和再 -次设置Q位的RFI之间遇到中断，你不知道它到底发生在哪里。如果你幸运的话，IAOQ -会指向清除Q位的指令，如果你不幸运的话，它会指向任何地方。通常Q位的问题会 -表现为无法解释的系统挂起或物理内存越界。 diff --git a/Documentation/translations/zh_CN/parisc/index.rst b/Documentation/translations/zh_CN/parisc/index.rst deleted file mode 100644 index 0cc553fc8272..000000000000 --- a/Documentation/translations/zh_CN/parisc/index.rst +++ /dev/null @@ -1,31 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/parisc/index.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_parisc_index: - -==================== -PA-RISC体系架构 -==================== - -.. toctree:: - :maxdepth: 2 - - debugging - registers - -Todolist: - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/parisc/registers.rst b/Documentation/translations/zh_CN/parisc/registers.rst deleted file mode 100644 index d2ab1874a602..000000000000 --- a/Documentation/translations/zh_CN/parisc/registers.rst +++ /dev/null @@ -1,156 +0,0 @@ -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/parisc/registers.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_parisc_registers: - -========================= -Linux/PA-RISC的寄存器用法 -========================= - -[ 用星号表示目前尚未实现的计划用途。 ] - -ABI约定的通用寄存器 -=================== - -控制寄存器 ----------- - -============================ ================================= -CR 0 (恢复计数器) 用于ptrace -CR 1-CR 7(无定义) 未使用 -CR 8 (Protection ID) 每进程值* -CR 9, 12, 13 (PIDS) 未使用 -CR10 (CCR) FPU延迟保存* -CR11 按照ABI的规定（SAR） -CR14 (中断向量) 初始化为 fault_vector -CR15 (EIEM) 所有位初始化为1* -CR16 (间隔计时器) 读取周期数/写入开始时间间隔计时器 -CR17-CR22 中断参数 -CR19 中断指令寄存器 -CR20 中断空间寄存器 -CR21 中断偏移量寄存器 -CR22 中断 PSW -CR23 (EIRR) 读取未决中断/写入清除位 -CR24 (TR 0) 内核空间页目录指针 -CR25 (TR 1) 用户空间页目录指针 -CR26 (TR 2) 不使用 -CR27 (TR 3) 线程描述符指针 -CR28 (TR 4) 不使用 -CR29 (TR 5) 不使用 -CR30 (TR 6) 当前 / 0 -CR31 (TR 7) 临时寄存器，在不同地方使用 -============================ ================================= - -空间寄存器（内核模式） ----------------------- - -======== ============================== -SR0 临时空间寄存器 -SR4-SR7 设置为0 -SR1 临时空间寄存器 -SR2 内核不应该破坏它 -SR3 用于用户空间访问（当前进程） -======== ============================== - -空间寄存器（用户模式） ----------------------- - -======== ============================ -SR0 临时空间寄存器 -SR1 临时空间寄存器 -SR2 保存Linux gateway page的空间 -SR3 在内核中保存用户地址空间的值 -SR4-SR7 定义了用户/内核的短地址空间 -======== ============================ - - -处理器状态字 ------------- - -====================== ================================================ -W （64位地址） 0 -E （小尾端） 0 -S （安全间隔计时器） 0 -T （产生分支陷阱） 0 -H （高特权级陷阱） 0 -L （低特权级陷阱） 0 -N （撤销下一条指令） 被C代码使用 -X （数据存储中断禁用） 0 -B （产生分支） 被C代码使用 -C （代码地址转译） 1, 在执行实模式代码时为0 -V （除法步长校正） 被C代码使用 -M （HPMC 掩码） 0, 在执行HPMC操作*时为1 -C/B （进/借 位） 被C代码使用 -O （有序引用） 1* -F （性能监视器） 0 -R （回收计数器陷阱） 0 -Q （收集中断状态） 1 （在rfi之前的代码中为0） -P （保护标识符） 1* -D （数据地址转译） 1, 在执行实模式代码时为0 -I （外部中断掩码） 由cli()/sti()宏使用。 -====================== ================================================ - -“隐形”寄存器（影子寄存器） ---------------------------- - -============= =================== -PSW W 默认值 0 -PSW E 默认值 0 -影子寄存器 被中断处理代码使用 -TOC启用位 1 -============= =================== - ----------------------------------------------------------- - -PA-RISC架构定义了7个寄存器作为“影子寄存器”。这些寄存器在 -RETURN FROM INTERRUPTION AND RESTORE指令中使用，通过消 -除中断处理程序中对一般寄存器（GR）的保存和恢复的需要来减 -少状态保存和恢复时间。影子寄存器是GRs 1, 8, 9, 16, 17, -24和25。 - -------------------------------------------------------------------------- - -寄存器使用说明，最初由John Marvin提供，并由Randolph Chung提供一些补充说明。 - -对于通用寄存器: - -r1,r2,r19-r26,r28,r29 & r31可以在不保存它们的情况下被使用。当然，如果你 -关心它们，在调用另一个程序之前，你也需要保存它们。上面的一些寄存器确实 -有特殊的含义，你应该注意一下: - - r1: - addil指令是硬性规定将其结果放在r1中，所以如果你使用这条指令要 - 注意这点。 - - r2: - 这就是返回指针。一般来说，你不想使用它，因为你需要这个指针来返 - 回给你的调用者。然而，它与这组寄存器组合在一起，因为调用者不能 - 依赖你返回时的值是相同的，也就是说，你可以将r2复制到另一个寄存 - 器，并在作废r2后通过该寄存器返回，这应该不会给调用程序带来问题。 - - r19-r22: - 这些通常被认为是临时寄存器。 - 请注意，在64位中它们是arg7-arg4。 - - r23-r26: - 这些是arg3-arg0，也就是说，如果你不再关心传入的值，你可以使用 - 它们。 - - r28,r29: - 这俩是ret0和ret1。它们是你传入返回值的地方。r28是主返回值。当返回 - 小结构体时，r29也可以用来将数据传回给调用程序。 - - r30: - 栈指针 - - r31: - ble指令将返回指针放在这里。 - - - r3-r18,r27,r30需要被保存和恢复。r3-r18只是一般用途的寄存器。 - r27是数据指针，用来使对全局变量的引用更容易。r30是栈指针。 diff --git a/MAINTAINERS b/MAINTAINERS index c515abc269f2..02720bc91481 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15834,7 +15834,7 @@ W: https://parisc.wiki.kernel.org Q: http://patchwork.kernel.org/project/linux-parisc/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git -F: Documentation/parisc/ +F: Documentation/arch/parisc/ F: arch/parisc/ F: drivers/char/agp/parisc-agp.c F: drivers/input/misc/hp_sdc_rtc.c -- cgit v1.2.3