From ee19f644c4594d1b8382f1538c19396f92c3c171 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sat, 26 Sep 2020 01:58:27 +0200 Subject: dt-bindings: phy: Drop reset-gpios from marvell,mmp3-hsic-phy This has been added in error -- the PHY block doesn't have a reset pin. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200925235828.228626-2-lkundrak@v3.sk Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml | 7 ------- 1 file changed, 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml index 00609ace677c..30e290c57930 100644 --- a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml +++ b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml @@ -18,27 +18,20 @@ properties: maxItems: 1 description: base address of the device - reset-gpios: - maxItems: 1 - description: GPIO connected to reset - "#phy-cells": const: 0 required: - compatible - reg - - reset-gpios - "#phy-cells" additionalProperties: false examples: - | - #include hsic-phy@f0001800 { compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0001800 0x40>; - reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; #phy-cells = <0>; }; -- cgit v1.2.3 From a1b87f1aac4dba2bac0e0019a9c05f7efa36c37d Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sat, 26 Sep 2020 01:58:28 +0200 Subject: dt-bindings: phy: Allow BSD licensing of marvell,mmp3-hsic-phy.yaml I wrote this binding and I'm fine with it being GPL + BSD dual-licensed, as is recommended for new DT bindings. Signed-off-by: Lubomir Rintel Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200925235828.228626-3-lkundrak@v3.sk Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml index 30e290c57930..ff255aa4cc10 100644 --- a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml +++ b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) # Copyright 2019 Lubomir Rintel %YAML 1.2 --- -- cgit v1.2.3 From f96a15c7698ede0e60bf5b4b9b5d0c7d0a0b505f Mon Sep 17 00:00:00 2001 From: Samuel Thibault Date: Sun, 8 Nov 2020 19:18:24 +0100 Subject: speakup: Document read_all_doc shortcut This was implemented a long time ago, but never actually added to the documentation. Signed-off-by: Samuel Thibault Link: https://lore.kernel.org/r/20201108181824.bso5exam72b4p4tk@function Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/spkguide.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/admin-guide/spkguide.txt b/Documentation/admin-guide/spkguide.txt index 3782f6a09e97..5ff6a0fe87d1 100644 --- a/Documentation/admin-guide/spkguide.txt +++ b/Documentation/admin-guide/spkguide.txt @@ -344,6 +344,7 @@ spk key_slash = say_attributes spk key_8 = speakup_paste shift spk key_m = say_first_char ctrl spk key_semicolon = say_last_char +spk key_r = read_all_doc 5. The Speakup Sys System -- cgit v1.2.3 From 439e8f6f1e5d1ca973da278499078e213dad63bb Mon Sep 17 00:00:00 2001 From: Ivan Zaentsev Date: Thu, 12 Nov 2020 09:49:31 +0300 Subject: w1: w1_therm: Rename conflicting sysfs attribute 'eeprom' to 'eeprom_cmd' Duplicate attribute 'eeprom' is defined in: 1) Documentation/ABI/testing/sysfs-driver-w1_therm 2) Documentation/ABI/stable/sysfs-driver-w1_ds28e04 Both drivers define an attribute: /sys/bus/w1/devices/.../eeprom with conflicting behavior. Fix by renaming the newer one in w1_therm.c to 'eeprom_cmd'. Reported-by: Mauro Carvalho Chehab Suggested-by: Greg Kroah-Hartman Link: https://lore.kernel.org/lkml/20201029152845.6bbb39ce@coco.lan/ Signed-off-by: Ivan Zaentsev Link: https://lore.kernel.org/r/20201112064931.8471-1-ivan.zaentsev@wirenboard.ru Signed-off-by: Greg Kroah-Hartman --- Documentation/ABI/testing/sysfs-driver-w1_therm | 2 +- Documentation/w1/slaves/w1_therm.rst | 2 +- drivers/w1/slaves/w1_therm.c | 12 ++++++------ 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-driver-w1_therm b/Documentation/ABI/testing/sysfs-driver-w1_therm index 6a37dc33ffdb..74642c73d29c 100644 --- a/Documentation/ABI/testing/sysfs-driver-w1_therm +++ b/Documentation/ABI/testing/sysfs-driver-w1_therm @@ -14,7 +14,7 @@ Users: any user space application which wants to communicate with w1_term device -What: /sys/bus/w1/devices/.../eeprom +What: /sys/bus/w1/devices/.../eeprom_cmd Date: May 2020 Contact: Akira Shimahara Description: diff --git a/Documentation/w1/slaves/w1_therm.rst b/Documentation/w1/slaves/w1_therm.rst index e39202e2b000..c3c9ed7a356c 100644 --- a/Documentation/w1/slaves/w1_therm.rst +++ b/Documentation/w1/slaves/w1_therm.rst @@ -82,7 +82,7 @@ resolution is read back from the chip and verified. Note: Changing the resolution reverts the conversion time to default. -The write-only sysfs entry ``eeprom`` is an alternative for EEPROM operations. +The write-only sysfs entry ``eeprom_cmd`` is an alternative for EEPROM operations. Write ``save`` to save device RAM to EEPROM. Write ``restore`` to restore EEPROM data in device RAM. diff --git a/drivers/w1/slaves/w1_therm.c b/drivers/w1/slaves/w1_therm.c index cddf60b7309c..3712b1e6dc71 100644 --- a/drivers/w1/slaves/w1_therm.c +++ b/drivers/w1/slaves/w1_therm.c @@ -315,7 +315,7 @@ static ssize_t resolution_show(struct device *device, static ssize_t resolution_store(struct device *device, struct device_attribute *attr, const char *buf, size_t size); -static ssize_t eeprom_store(struct device *device, +static ssize_t eeprom_cmd_store(struct device *device, struct device_attribute *attr, const char *buf, size_t size); static ssize_t alarms_store(struct device *device, @@ -350,7 +350,7 @@ static DEVICE_ATTR_RO(w1_seq); static DEVICE_ATTR_RO(temperature); static DEVICE_ATTR_RO(ext_power); static DEVICE_ATTR_RW(resolution); -static DEVICE_ATTR_WO(eeprom); +static DEVICE_ATTR_WO(eeprom_cmd); static DEVICE_ATTR_RW(alarms); static DEVICE_ATTR_RW(conv_time); static DEVICE_ATTR_RW(features); @@ -386,7 +386,7 @@ static struct attribute *w1_therm_attrs[] = { &dev_attr_temperature.attr, &dev_attr_ext_power.attr, &dev_attr_resolution.attr, - &dev_attr_eeprom.attr, + &dev_attr_eeprom_cmd.attr, &dev_attr_alarms.attr, &dev_attr_conv_time.attr, &dev_attr_features.attr, @@ -397,7 +397,7 @@ static struct attribute *w1_ds18s20_attrs[] = { &dev_attr_w1_slave.attr, &dev_attr_temperature.attr, &dev_attr_ext_power.attr, - &dev_attr_eeprom.attr, + &dev_attr_eeprom_cmd.attr, &dev_attr_alarms.attr, &dev_attr_conv_time.attr, &dev_attr_features.attr, @@ -410,7 +410,7 @@ static struct attribute *w1_ds28ea00_attrs[] = { &dev_attr_temperature.attr, &dev_attr_ext_power.attr, &dev_attr_resolution.attr, - &dev_attr_eeprom.attr, + &dev_attr_eeprom_cmd.attr, &dev_attr_alarms.attr, &dev_attr_conv_time.attr, &dev_attr_features.attr, @@ -1740,7 +1740,7 @@ static ssize_t resolution_store(struct device *device, return size; } -static ssize_t eeprom_store(struct device *device, +static ssize_t eeprom_cmd_store(struct device *device, struct device_attribute *attr, const char *buf, size_t size) { struct w1_slave *sl = dev_to_w1_slave(device); -- cgit v1.2.3 From 5594b407a48b1fcf6da1ecbfe4a647f2ce3c284a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 27 Oct 2020 22:30:29 +0530 Subject: dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings Add the below three PCIe PHYs found in SM8250 to the QMP binding: QMP GEN3x1 PHY - 1 lane QMP GEN3x2 PHY - 2 lanes QMP Modem PHY - 2 lanes Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201027170033.8475-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 185cdea9cf81..ec05db374645 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -31,6 +31,9 @@ properties: - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy reg: items: @@ -259,6 +262,9 @@ allOf: enum: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy then: properties: clocks: -- cgit v1.2.3 From ba2bf1f090ebdf36f02c6d31381a0685982ff7fe Mon Sep 17 00:00:00 2001 From: Swapnil Jakhade Date: Wed, 28 Oct 2020 16:22:41 +0100 Subject: dt-bindings: phy: Add Cadence Sierra PHY bindings in YAML format Add Cadence Sierra PHY bindings in YAML format. Signed-off-by: Swapnil Jakhade Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/phy-cadence-sierra.txt | 70 ---------- .../bindings/phy/phy-cadence-sierra.yaml | 152 +++++++++++++++++++++ 2 files changed, 152 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt deleted file mode 100644 index 03f5939d3d19..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt +++ /dev/null @@ -1,70 +0,0 @@ -Cadence Sierra PHY ------------------------ - -Required properties: -- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform - Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC. -- resets: Must contain an entry for each in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include "sierra_reset" and "sierra_apb". - "sierra_reset" must control the reset line to the PHY. - "sierra_apb" must control the reset line to the APB PHY - interface ("sierra_apb" is optional). -- reg: register range for the PHY. -- #address-cells: Must be 1 -- #size-cells: Must be 0 - -Optional properties: -- clocks: Must contain an entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must contain "cmn_refclk_dig_div" and - "cmn_refclk1_dig_div" for configuring the frequency of - the clock to the lanes. "phy_clk" is deprecated. -- cdns,autoconf: A boolean property whose presence indicates that the - PHY registers will be configured by hardware. If not - present, all sub-node optional properties must be - provided. - -Sub-nodes: - Each group of PHY lanes with a single master lane should be represented as - a sub-node. Note that the actual configuration of each lane is determined by - hardware strapping, and must match the configuration specified here. - -Sub-node required properties: -- #phy-cells: Generic PHY binding; must be 0. -- reg: The master lane number. This is the lowest numbered lane - in the lane group. -- resets: Must contain one entry which controls the reset line for the - master lane of the sub-node. - See ../reset/reset.txt for details. - -Sub-node optional properties: -- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The - group is made up of consecutive lanes. -- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on - configuration of lanes. - -Example: - pcie_phy4: pcie-phy@fd240000 { - compatible = "cdns,sierra-phy-t0"; - reg = <0x0 0xfd240000 0x0 0x40000>; - resets = <&phyrst 0>, <&phyrst 1>; - reset-names = "sierra_reset", "sierra_apb"; - clocks = <&phyclock>; - clock-names = "phy_clk"; - #address-cells = <1>; - #size-cells = <0>; - pcie0_phy0: pcie-phy@0 { - reg = <0>; - resets = <&phyrst 2>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - }; - pcie0_phy1: pcie-phy@2 { - reg = <2>; - resets = <&phyrst 4>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml new file mode 100644 index 000000000000..d210843863df --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence Sierra PHY binding + +description: + This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink + multiprotocol combinations including protocols such as PCIe, USB etc. + +maintainers: + - Swapnil Jakhade + - Yuti Amonkar + +properties: + compatible: + enum: + - cdns,sierra-phy-t0 + - ti,sierra-phy-t0 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + resets: + minItems: 1 + maxItems: 2 + items: + - description: Sierra PHY reset. + - description: Sierra APB reset. This is optional. + + reset-names: + minItems: 1 + maxItems: 2 + items: + - const: sierra_reset + - const: sierra_apb + + reg: + maxItems: 1 + description: + Offset of the Sierra PHY configuration registers. + + reg-names: + const: serdes + + clocks: + maxItems: 2 + + clock-names: + items: + - const: cmn_refclk_dig_div + - const: cmn_refclk1_dig_div + + cdns,autoconf: + type: boolean + description: + A boolean property whose presence indicates that the PHY registers will be + configured by hardware. If not present, all sub-node optional properties + must be provided. + +patternProperties: + '^phy@[0-9a-f]$': + type: object + description: + Each group of PHY lanes with a single master lane should be represented as + a sub-node. Note that the actual configuration of each lane is determined + by hardware strapping, and must match the configuration specified here. + properties: + reg: + description: + The master lane number. This is the lowest numbered lane in the lane group. + minimum: 0 + maximum: 15 + + resets: + minItems: 1 + maxItems: 4 + description: + Contains list of resets, one per lane, to get all the link lanes out of reset. + + "#phy-cells": + const: 0 + + cdns,phy-type: + description: + Specifies the type of PHY for which the group of PHY lanes is used. + Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4] + + cdns,num-lanes: + description: + Number of lanes in this group. The group is made up of consecutive lanes. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 + + required: + - reg + - resets + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + sierra-phy@fd240000 { + compatible = "cdns,sierra-phy-t0"; + reg = <0x0 0xfd240000 0x0 0x40000>; + resets = <&phyrst 0>, <&phyrst 1>; + reset-names = "sierra_reset", "sierra_apb"; + clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + #address-cells = <1>; + #size-cells = <0>; + pcie0_phy0: phy@0 { + reg = <0>; + resets = <&phyrst 2>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + }; + pcie0_phy1: phy@2 { + reg = <2>; + resets = <&phyrst 4>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + }; + }; + }; -- cgit v1.2.3 From 6d3b3f88423e4edc0fad5853c10558b42e1a91dd Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 22 Oct 2020 13:50:55 -0700 Subject: dt-bindings: phy: Allow defining the SATA AFE TX amplitude Document a new property which allows the selection of the SATA AFE TX amplitude in milli Volts. Possible values are 400, 500, 600 and 800mV. Acked-by: Rob Herring Signed-off-by: Florian Fainelli Link: https://lore.kernel.org/r/20201022205056.233879-2-f.fainelli@gmail.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt index c03ad2198410..e5abbace93a3 100644 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt @@ -38,6 +38,9 @@ Sub-nodes optional properties: - brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX equalizer value that should be used. Allowed range is 0..63. +- brcm,tx-amplitude-millivolt: transmit amplitude voltage in millivolt. + Possible values are 400, 500, 600 or 800 mV. + Example sata-phy@f0458100 { compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; -- cgit v1.2.3 From e1404d203139d871946df9091a6e042b1154bd63 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 16 Nov 2020 11:13:14 +0100 Subject: dt-bindings: phy: add Amlogic AXG MIPI D-PHY bindings The Amlogic AXg SoCs embeds a MIPI D-PHY to communicate with DSI panels, this adds the bindings. This D-PHY depends on a separate analog PHY. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201116101315.71720-2-narmstrong@baylibre.com Signed-off-by: Vinod Koul --- .../bindings/phy/amlogic,axg-mipi-dphy.yaml | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,axg-mipi-dphy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/amlogic,axg-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/amlogic,axg-mipi-dphy.yaml new file mode 100644 index 000000000000..be485f500887 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,axg-mipi-dphy.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic AXG MIPI D-PHY + +maintainers: + - Neil Armstrong + +properties: + compatible: + enum: + - amlogic,axg-mipi-dphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + "#phy-cells": + const: 0 + + phys: + maxItems: 1 + + phy-names: + items: + - const: analog + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@ff640000 { + compatible = "amlogic,axg-mipi-dphy"; + reg = <0xff640000 0x100>; + clocks = <&clk_mipi_dsi_phy>; + clock-names = "pclk"; + resets = <&reset_phy>; + reset-names = "phy"; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + }; -- cgit v1.2.3 From 450889074f4fafaff0ea82c2c4c7e0a93b3cd5c7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 16 Nov 2020 11:16:45 +0100 Subject: dt-bindings: phy: amlogic,meson-axg-mipi-pcie-analog: remove reg attribute The PHY registers happens to be at the beginning of a large zone containing interleaved system registers (mainly clocks, power management, PHY control..), found in all Amlogic SoC so far. The goal is to model it the same way as the other "features" of this zone, like Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt and Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml and have a coherent bindings scheme over the Amlogic SoCs. This update the description, removed the reg attribute then updates the example accordingly. Signed-off-by: Neil Armstrong Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201116101647.73448-2-narmstrong@baylibre.com Signed-off-by: Vinod Koul --- .../phy/amlogic,meson-axg-mipi-pcie-analog.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml index 18c1ec5e19ad..702763a84dac 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml @@ -9,27 +9,32 @@ title: Amlogic AXG shared MIPI/PCIE analog PHY maintainers: - Remi Pommarel +description: |+ + The Everything-Else Power Domains node should be the child of a syscon + node with the required property: + + - compatible: Should be the following: + "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon" + + Refer to the the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + properties: compatible: const: amlogic,axg-mipi-pcie-analog-phy - reg: - maxItems: 1 - "#phy-cells": const: 1 required: - compatible - - reg - "#phy-cells" additionalProperties: false examples: - | - mpphy: phy@0 { + mpphy: phy { compatible = "amlogic,axg-mipi-pcie-analog-phy"; - reg = <0x0 0xc>; #phy-cells = <1>; }; -- cgit v1.2.3 From 87c3cdecb3d5150270f1529ac140e7d0c192ba9d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 16 Nov 2020 11:16:46 +0100 Subject: dt-bindings: phy: amlogic,meson-axg-mipi-pcie-analog: remove phy cell parameter The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and is not exclusive. Thus remove the invalid phy cell parameter. Signed-off-by: Neil Armstrong Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201116101647.73448-3-narmstrong@baylibre.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml index 702763a84dac..4d01f3124e1c 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml @@ -24,7 +24,7 @@ properties: const: amlogic,axg-mipi-pcie-analog-phy "#phy-cells": - const: 1 + const: 0 required: - compatible @@ -36,5 +36,5 @@ examples: - | mpphy: phy { compatible = "amlogic,axg-mipi-pcie-analog-phy"; - #phy-cells = <1>; + #phy-cells = <0>; }; -- cgit v1.2.3 From 864788c00fd75d76c1e3183ab54fcf4fac22f3b7 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Mon, 16 Nov 2020 18:19:17 +0100 Subject: dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format using json-schema. Signed-off-by: Amelie Delaunay Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 73 ----------- .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 138 +++++++++++++++++++++ 2 files changed, 138 insertions(+), 73 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt deleted file mode 100644 index 725ae71ae653..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt +++ /dev/null @@ -1,73 +0,0 @@ -STMicroelectronics STM32 USB HS PHY controller - -The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI -switch. It controls PHY configuration and status, and the UTMI+ switch that -selects either OTG or HOST controller for the second PHY port. It also sets -PLL configuration. - -USBPHYC - |_ PLL - | - |_ PHY port#1 _________________ HOST controller - | _ | - | / 1|________________| - |_ PHY port#2 ----| |________________ - | \_0| | - |_ UTMI switch_______| OTG controller - - -Phy provider node -================= - -Required properties: -- compatible: must be "st,stm32mp1-usbphyc" -- reg: address and length of the usb phy control register set -- clocks: phandle + clock specifier for the PLL phy clock -- #address-cells: number of address cells for phys sub-nodes, must be <1> -- #size-cells: number of size cells for phys sub-nodes, must be <0> - -Optional properties: -- assigned-clocks: phandle + clock specifier for the PLL phy clock -- assigned-clock-parents: the PLL phy clock parent -- resets: phandle + reset specifier - -Required nodes: one sub-node per port the controller provides. - -Phy sub-nodes -============== - -Required properties: -- reg: phy port index -- phy-supply: phandle to the regulator providing 3V3 power to the PHY, - see phy-bindings.txt in the same directory. -- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY -- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY -- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY - port#1 and must be <1> for PHY port#2, to select USB controller - - -Example: - usbphyc: usb-phy@5a006000 { - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc_clk USBPHY_K>; - resets = <&rcc_rst USBPHY_R>; - #address-cells = <1>; - #size-cells = <0>; - - usbphyc_port0: usb-phy@0 { - reg = <0>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <0>; - }; - - usbphyc_port1: usb-phy@1 { - reg = <1>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml new file mode 100644 index 000000000000..0ba61979b970 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 USB HS PHY controller binding + +description: + + The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI + switch. It controls PHY configuration and status, and the UTMI+ switch that + selects either OTG or HOST controller for the second PHY port. It also sets + PLL configuration. + + USBPHYC + |_ PLL + | + |_ PHY port#1 _________________ HOST controller + | __ | + | / 1|________________| + |_ PHY port#2 ----| |________________ + | \_0| | + |_ UTMI switch_______| OTG controller + +maintainers: + - Amelie Delaunay + +properties: + compatible: + const: st,stm32mp1-usbphyc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +#Required child nodes: + +patternProperties: + "^usb-phy@[0|1]$": + type: object + description: + Each port the controller provides must be represented as a sub-node. + + properties: + reg: + description: phy port index. + maxItems: 1 + + phy-supply: + description: regulator providing 3V3 power supply to the PHY. + + vdda1v1-supply: + description: regulator providing 1V1 power supply to the PLL block + + vdda1v8-supply: + description: regulator providing 1V8 power supply to the PLL block + + "#phy-cells": + enum: [ 0x0, 0x1 ] + + allOf: + - if: + properties: + reg: + const: 0 + then: + properties: + "#phy-cells": + const: 0 + else: + properties: + "#phy-cells": + const: 1 + description: + The value is used to select UTMI switch output. + 0 for OTG controller and 1 for Host controller. + + required: + - reg + - phy-supply + - vdda1v1-supply + - vdda1v8-supply + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - usb-phy@0 + - usb-phy@1 + +additionalProperties: false + +examples: + - | + #include + #include + usbphyc: usbphyc@5a006000 { + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + #address-cells = <1>; + #size-cells = <0>; + + usbphyc_port0: usb-phy@0 { + reg = <0>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + #phy-cells = <0>; + }; + + usbphyc_port1: usb-phy@1 { + reg = <1>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + #phy-cells = <1>; + }; + }; +... -- cgit v1.2.3 From 8f3991f0669ef271615e25c3390c20b8fb00d674 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 27 Nov 2020 10:28:33 +0000 Subject: dt-bindings: nvmem: mtk-efuse: add documentation for MT8516 SoC Add binding documentation for MT8516 SoCs. Acked-by: Rob Herring Signed-off-by: Fabien Parent Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20201127102837.19366-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt index 0668c45a156d..ef93c3b95424 100644 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt @@ -7,6 +7,7 @@ Required properties: "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 + "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 - reg: Should contain registers location and length = Data cells = -- cgit v1.2.3 From c8b336bb1aeb88baebdf116f151a4afe712512c5 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Fri, 27 Nov 2020 10:28:35 +0000 Subject: dt-bindings: nvmem: Add soc qfprom compatible strings Add SoC-specific compatible strings so that data can be attached to it in the driver. Reviewed-by: Rob Herring Signed-off-by: Evan Green Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20201127102837.19366-4-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/qcom,qfprom.yaml | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 1a18b6bab35e..992777c90a0b 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -14,7 +14,18 @@ allOf: properties: compatible: - const: qcom,qfprom + items: + - enum: + - qcom,apq8064-qfprom + - qcom,apq8084-qfprom + - qcom,msm8974-qfprom + - qcom,msm8916-qfprom + - qcom,msm8996-qfprom + - qcom,msm8998-qfprom + - qcom,qcs404-qfprom + - qcom,sc7180-qfprom + - qcom,sdm845-qfprom + - const: qcom,qfprom reg: # If the QFPROM is read-only OS image then only the corrected region @@ -60,7 +71,7 @@ examples: #size-cells = <2>; efuse@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>, <0 0x00780000 0 0x7a0>, <0 0x00782000 0 0x100>, @@ -85,7 +96,7 @@ examples: #size-cells = <2>; efuse@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 4086afa2a16279392e453605aac09728e60d9316 Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Mon, 16 Nov 2020 20:08:30 +0800 Subject: dt-bindings: phy: Add Intel Keem Bay USB PHY bindings Binding description for Intel Keem Bay USB PHY. Signed-off-by: Wan Ahmad Zainie Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201116120831.32641-2-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul --- .../bindings/phy/intel,phy-keembay-usb.yaml | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml b/Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml new file mode 100644 index 000000000000..a217bb8ac5bc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,phy-keembay-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay USB PHY bindings + +maintainers: + - Wan Ahmad Zainie + +properties: + compatible: + const: intel,keembay-usb-phy + + reg: + items: + - description: USB APB CPR (clock, power, reset) register + - description: USB APB slave register + + reg-names: + items: + - const: cpr-apb-base + - const: slv-apb-base + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - '#phy-cells' + +additionalProperties: false + +examples: + - | + usb-phy@20400000 { + compatible = "intel,keembay-usb-phy"; + reg = <0x20400000 0x1c>, + <0x20480000 0xd0>; + reg-names = "cpr-apb-base", "slv-apb-base"; + #phy-cells = <0>; + }; -- cgit v1.2.3 From 27076a7358b5e170b7cba80b43b4e49ac3e279fc Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Sat, 21 Nov 2020 16:50:34 +0100 Subject: dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY Add bindings to describe Mediatek MT7621 PCIe PHY. Signed-off-by: Sergio Paracuellos Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201121155037.21354-2-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul --- .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml new file mode 100644 index 000000000000..0ccaded3f245 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek Mt7621 PCIe PHY Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +properties: + compatible: + const: mediatek,mt7621-pci-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: selects if the phy is dual-ported + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + pcie0_phy: pcie-phy@1e149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e149000 0x0700>; + #phy-cells = <1>; + }; -- cgit v1.2.3 From 81b534f7e9b27309b99ac2b870518c17381d2912 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 20 Nov 2020 09:56:36 +0100 Subject: phy: samsung: Add support for the Exynos5420 variant of the USB2 PHY Exynos5420 differs a bit from Exynos5250 in USB2 PHY related registers in the PMU region. Add a variant for the Exynos5420 case. Till now, USB2 PHY worked only because the bootloader enabled the PHY, but then driver messed USB 3.0 DRD related registers during the suspend/resume cycle. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201120085637.7299-2-m.szyprowski@samsung.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/samsung-phy.txt | 1 + drivers/phy/samsung/Kconfig | 7 +++- drivers/phy/samsung/phy-exynos5250-usb2.c | 48 +++++++++++++++------- drivers/phy/samsung/phy-samsung-usb2.c | 6 +++ drivers/phy/samsung/phy-samsung-usb2.h | 1 + 5 files changed, 48 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index 7510830a79bd..8f51aee91101 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -47,6 +47,7 @@ Required properties: - "samsung,exynos4210-usb2-phy" - "samsung,exynos4x12-usb2-phy" - "samsung,exynos5250-usb2-phy" + - "samsung,exynos5420-usb2-phy" - "samsung,s5pv210-usb2-phy" - reg : a list of registers used by phy driver - first and obligatory is the location of phy modules registers diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig index e20d2fcc9fe7..0f51d3bf38cc 100644 --- a/drivers/phy/samsung/Kconfig +++ b/drivers/phy/samsung/Kconfig @@ -64,7 +64,12 @@ config PHY_EXYNOS4X12_USB2 config PHY_EXYNOS5250_USB2 bool depends on PHY_SAMSUNG_USB2 - default SOC_EXYNOS5250 || SOC_EXYNOS5420 + default SOC_EXYNOS5250 + +config PHY_EXYNOS5420_USB2 + bool + depends on PHY_SAMSUNG_USB2 + default SOC_EXYNOS5420 config PHY_S5PV210_USB2 bool "Support for S5PV210" diff --git a/drivers/phy/samsung/phy-exynos5250-usb2.c b/drivers/phy/samsung/phy-exynos5250-usb2.c index 4f53b711fd6f..e198010e1bfd 100644 --- a/drivers/phy/samsung/phy-exynos5250-usb2.c +++ b/drivers/phy/samsung/phy-exynos5250-usb2.c @@ -117,9 +117,9 @@ /* Isolation, configured in the power management unit */ #define EXYNOS_5250_USB_ISOL_OTG_OFFSET 0x704 -#define EXYNOS_5250_USB_ISOL_OTG BIT(0) #define EXYNOS_5250_USB_ISOL_HOST_OFFSET 0x708 -#define EXYNOS_5250_USB_ISOL_HOST BIT(0) +#define EXYNOS_5420_USB_ISOL_HOST_OFFSET 0x70C +#define EXYNOS_5250_USB_ISOL_ENABLE BIT(0) /* Mode swtich register */ #define EXYNOS_5250_MODE_SWITCH_OFFSET 0x230 @@ -132,7 +132,6 @@ enum exynos4x12_phy_id { EXYNOS5250_HOST, EXYNOS5250_HSIC0, EXYNOS5250_HSIC1, - EXYNOS5250_NUM_PHYS, }; /* @@ -176,20 +175,19 @@ static void exynos5250_isol(struct samsung_usb2_phy_instance *inst, bool on) { struct samsung_usb2_phy_driver *drv = inst->drv; u32 offset; - u32 mask; + u32 mask = EXYNOS_5250_USB_ISOL_ENABLE; - switch (inst->cfg->id) { - case EXYNOS5250_DEVICE: + if (drv->cfg == &exynos5250_usb2_phy_config && + inst->cfg->id == EXYNOS5250_DEVICE) offset = EXYNOS_5250_USB_ISOL_OTG_OFFSET; - mask = EXYNOS_5250_USB_ISOL_OTG; - break; - case EXYNOS5250_HOST: + else if (drv->cfg == &exynos5250_usb2_phy_config && + inst->cfg->id == EXYNOS5250_HOST) offset = EXYNOS_5250_USB_ISOL_HOST_OFFSET; - mask = EXYNOS_5250_USB_ISOL_HOST; - break; - default: + else if (drv->cfg == &exynos5420_usb2_phy_config && + inst->cfg->id == EXYNOS5250_HOST) + offset = EXYNOS_5420_USB_ISOL_HOST_OFFSET; + else return; - } regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); } @@ -390,9 +388,31 @@ static const struct samsung_usb2_common_phy exynos5250_phys[] = { }, }; +static const struct samsung_usb2_common_phy exynos5420_phys[] = { + { + .label = "host", + .id = EXYNOS5250_HOST, + .power_on = exynos5250_power_on, + .power_off = exynos5250_power_off, + }, + { + .label = "hsic", + .id = EXYNOS5250_HSIC0, + .power_on = exynos5250_power_on, + .power_off = exynos5250_power_off, + }, +}; + const struct samsung_usb2_phy_config exynos5250_usb2_phy_config = { .has_mode_switch = 1, - .num_phys = EXYNOS5250_NUM_PHYS, + .num_phys = ARRAY_SIZE(exynos5250_phys), .phys = exynos5250_phys, .rate_to_clk = exynos5250_rate_to_clk, }; + +const struct samsung_usb2_phy_config exynos5420_usb2_phy_config = { + .has_mode_switch = 1, + .num_phys = ARRAY_SIZE(exynos5420_phys), + .phys = exynos5420_phys, + .rate_to_clk = exynos5250_rate_to_clk, +}; diff --git a/drivers/phy/samsung/phy-samsung-usb2.c b/drivers/phy/samsung/phy-samsung-usb2.c index f79f605cff79..3908153f2ce5 100644 --- a/drivers/phy/samsung/phy-samsung-usb2.c +++ b/drivers/phy/samsung/phy-samsung-usb2.c @@ -128,6 +128,12 @@ static const struct of_device_id samsung_usb2_phy_of_match[] = { .data = &exynos5250_usb2_phy_config, }, #endif +#ifdef CONFIG_PHY_EXYNOS5420_USB2 + { + .compatible = "samsung,exynos5420-usb2-phy", + .data = &exynos5420_usb2_phy_config, + }, +#endif #ifdef CONFIG_PHY_S5PV210_USB2 { .compatible = "samsung,s5pv210-usb2-phy", diff --git a/drivers/phy/samsung/phy-samsung-usb2.h b/drivers/phy/samsung/phy-samsung-usb2.h index 77fb23bc218f..ebaf43bfc5a2 100644 --- a/drivers/phy/samsung/phy-samsung-usb2.h +++ b/drivers/phy/samsung/phy-samsung-usb2.h @@ -66,5 +66,6 @@ extern const struct samsung_usb2_phy_config exynos3250_usb2_phy_config; extern const struct samsung_usb2_phy_config exynos4210_usb2_phy_config; extern const struct samsung_usb2_phy_config exynos4x12_usb2_phy_config; extern const struct samsung_usb2_phy_config exynos5250_usb2_phy_config; +extern const struct samsung_usb2_phy_config exynos5420_usb2_phy_config; extern const struct samsung_usb2_phy_config s5pv210_usb2_phy_config; #endif -- cgit v1.2.3 From f34e43f123825a39190b978a433423c2e2030830 Mon Sep 17 00:00:00 2001 From: Chris Ruehl Date: Sun, 29 Nov 2020 13:44:15 +0800 Subject: devicetree: phy: rockchip-emmc: pulldown property Update the documentation and add the bool property enable-strobe-pulldown used to enable the internal pull-down for the strobe line. Signed-off-by: Chris Ruehl Link: https://lore.kernel.org/r/20201129054416.3980-3-chris.ruehl@gtsys.com.hk Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt index e728786f21e0..3e4d2d79a65d 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt @@ -16,6 +16,8 @@ Optional properties: - drive-impedance-ohm: Specifies the drive impedance in Ohm. Possible values are 33, 40, 50, 66 and 100. If not set, the default value of 50 will be applied. + - enable-strobe-pulldown: Enable internal pull-down for the strobe line. + If not set, pull-down is not used. Example: -- cgit v1.2.3 From 4f6ecfaf3e22a70d905a627a0e84e9edb2b32835 Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Mon, 16 Nov 2020 22:19:05 +0800 Subject: dt-bindings: USB: Add bindings for Ingenic JZ4775 and X2000. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move Ingenic USB PHY bindings from Documentation/devicetree/bindings/usb to Documentation/devicetree/bindings/phy, and add bindings for JZ4775 SoC and X2000 SoC. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Rob Herring Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20201116141906.11758-3-zhouyanjie@wanyeetech.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/clock/ingenic,cgu.yaml | 2 +- .../devicetree/bindings/phy/ingenic,phy-usb.yaml | 58 ++++++++++++++++++++++ .../bindings/usb/ingenic,jz4770-phy.yaml | 56 --------------------- 3 files changed, 59 insertions(+), 57 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/ingenic,phy-usb.yaml delete mode 100644 Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index 5dd7ea8a78e4..c65b9458c0b6 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -92,7 +92,7 @@ required: patternProperties: "^usb-phy@[a-f0-9]+$": - allOf: [ $ref: "../usb/ingenic,jz4770-phy.yaml#" ] + allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ] additionalProperties: false diff --git a/Documentation/devicetree/bindings/phy/ingenic,phy-usb.yaml b/Documentation/devicetree/bindings/phy/ingenic,phy-usb.yaml new file mode 100644 index 000000000000..0fd93d71fe5a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ingenic,phy-usb.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ingenic,phy-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs USB PHY devicetree bindings + +maintainers: + - Paul Cercueil + - 周琰杰 (Zhou Yanjie) + +properties: + $nodename: + pattern: '^usb-phy@.*' + + compatible: + enum: + - ingenic,jz4770-phy + - ingenic,jz4775-phy + - ingenic,jz4780-phy + - ingenic,x1000-phy + - ingenic,x1830-phy + - ingenic,x2000-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcc-supply: + description: VCC power supply + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - vcc-supply + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + otg_phy: usb-phy@3c { + compatible = "ingenic,jz4770-phy"; + reg = <0x3c 0x10>; + + vcc-supply = <&vcc>; + clocks = <&cgu JZ4770_CLK_OTG_PHY>; + + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml b/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml deleted file mode 100644 index 2d61166ea5cf..000000000000 --- a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/usb/ingenic,jz4770-phy.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Ingenic SoCs USB PHY devicetree bindings - -maintainers: - - Paul Cercueil - - 周琰杰 (Zhou Yanjie) - -properties: - $nodename: - pattern: '^usb-phy@.*' - - compatible: - enum: - - ingenic,jz4770-phy - - ingenic,jz4780-phy - - ingenic,x1000-phy - - ingenic,x1830-phy - - reg: - maxItems: 1 - - clocks: - maxItems: 1 - - vcc-supply: - description: VCC power supply - - '#phy-cells': - const: 0 - -required: - - compatible - - reg - - clocks - - vcc-supply - - '#phy-cells' - -additionalProperties: false - -examples: - - | - #include - otg_phy: usb-phy@3c { - compatible = "ingenic,jz4770-phy"; - reg = <0x3c 0x10>; - - vcc-supply = <&vcc>; - clocks = <&cgu JZ4770_CLK_OTG_PHY>; - - #phy-cells = <0>; - }; -- cgit v1.2.3 From 86e21677e775bcf10d676e0e93710ce17d52fdb7 Mon Sep 17 00:00:00 2001 From: Chris Ruehl Date: Wed, 2 Dec 2020 16:25:07 +0800 Subject: devicetree: phy: rockchip-emmc add output-tapdelay-select Update the rockchip-emmc-phy.txt and add the u32 property 'output-tapdelay-select'. This allow to set the otapdlysec register. Tested with our customized rk3399 board to tune eMMC. Signed-off-by: Chris Ruehl Link: https://lore.kernel.org/r/20201202082507.3536-3-chris.ruehl@gtsys.com.hk Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt index 3e4d2d79a65d..00aa2d349e55 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt @@ -18,6 +18,9 @@ Optional properties: If not set, the default value of 50 will be applied. - enable-strobe-pulldown: Enable internal pull-down for the strobe line. If not set, pull-down is not used. + - output-tapdelay-select: Specifies the phyctrl_otapdlysec register. + If not set, the register defaults to 0x4. + Maximum value 0xf. Example: -- cgit v1.2.3 From af89e575152a9b6d4a3e0e5e35bf6b7075905276 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 4 Dec 2020 11:35:31 -0800 Subject: dt-bindings: phy: Convert Broadcom SATA PHY to YAML Update the Broadcom SATA PHY Device Tree binding to a YAML format. Suggested-by: Vinod Koul Signed-off-by: Florian Fainelli Link: https://lore.kernel.org/r/20201204193532.1934108-1-f.fainelli@gmail.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/brcm,sata-phy.yaml | 148 +++++++++++++++++++++ .../devicetree/bindings/phy/brcm-sata-phy.txt | 61 --------- 2 files changed, 148 insertions(+), 61 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/brcm-sata-phy.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml new file mode 100644 index 000000000000..58c3ef8004ad --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Broadcom SATA3 PHY + +maintainers: + - Florian Fainelli + +properties: + $nodename: + pattern: "^sata[-|_]phy(@.*)?$" + + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7216-sata-phy + - brcm,bcm7425-sata-phy + - brcm,bcm7445-sata-phy + - brcm,bcm63138-sata-phy + - const: brcm,phy-sata3 + - items: + - const: brcm,iproc-nsp-sata-phy + - items: + - const: brcm,iproc-ns2-sata-phy + - items: + - const: brcm,iproc-sr-sata-phy + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: phy + - const: phy-ctrl + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^sata-phy@[0-9]+$": + type: object + description: | + Each port's PHY should be represented as a sub-node. + + properties: + reg: + description: The SATA PHY port number + maxItems: 1 + + "#phy-cells": + const: 0 + + "brcm,enable-ssc": + $ref: /schemas/types.yaml#/definitions/flag + description: | + Use spread spectrum clocking (SSC) on this port + This property is not applicable for "brcm,iproc-ns2-sata-phy", + "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy". + + "brcm,rxaeq-mode": + $ref: /schemas/types.yaml#/definitions/string + description: + String that indicates the desired RX equalizer mode. + enum: + - off + - auto + - manual + + "brcm,rxaeq-value": + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + When 'brcm,rxaeq-mode' is set to "manual", provides the RX + equalizer value that should be used. + minimum: 0 + maximum: 63 + + "brcm,tx-amplitude-millivolt": + description: | + Transmit amplitude voltage in millivolt. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [400, 500, 600, 800] + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +if: + properties: + compatible: + items: + const: brcm,iproc-ns2-sata-phy +then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: "phy" + - const: "phy-ctrl" +else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + items: + - const: "phy" + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - reg-names + +additionalProperties: false + +examples: + - | + sata_phy@f0458100 { + compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; + reg = <0xf0458100 0x1e00>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + + sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt deleted file mode 100644 index e5abbace93a3..000000000000 --- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Broadcom SATA3 PHY - -Required properties: -- compatible: should be one or more of - "brcm,bcm7216-sata-phy" - "brcm,bcm7425-sata-phy" - "brcm,bcm7445-sata-phy" - "brcm,iproc-ns2-sata-phy" - "brcm,iproc-nsp-sata-phy" - "brcm,phy-sata3" - "brcm,iproc-sr-sata-phy" - "brcm,bcm63138-sata-phy" -- address-cells: should be 1 -- size-cells: should be 0 -- reg: register ranges for the PHY PCB interface -- reg-names: should be "phy" and "phy-ctrl" - The "phy-ctrl" registers are only required for - "brcm,iproc-ns2-sata-phy" and "brcm,iproc-sr-sata-phy". - -Sub-nodes: - Each port's PHY should be represented as a sub-node. - -Sub-nodes required properties: -- reg: the PHY number -- phy-cells: generic PHY binding; must be 0 - -Sub-nodes optional properties: -- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port - This property is not applicable for "brcm,iproc-ns2-sata-phy", - "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy". - -- brcm,rxaeq-mode: string that indicates the desired RX equalizer - mode, possible values are: - "off" (equivalent to not specifying the property) - "auto" - "manual" (brcm,rxaeq-value is used in that case) - -- brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX - equalizer value that should be used. Allowed range is 0..63. - -- brcm,tx-amplitude-millivolt: transmit amplitude voltage in millivolt. - Possible values are 400, 500, 600 or 800 mV. - -Example - sata-phy@f0458100 { - compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; - reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - - sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; -- cgit v1.2.3 From f6f79dd22f589d485ad2a79e743e00b9ff278d8b Mon Sep 17 00:00:00 2001 From: Michael Auchter Date: Thu, 15 Oct 2020 09:07:35 -0500 Subject: dt-bindings: extcon: add binding for TUSB320 Add a device tree binding for the TI TUSB320. Signed-off-by: Michael Auchter Reviewed-by: Rob Herring Signed-off-by: Chanwoo Choi --- .../bindings/extcon/extcon-usbc-tusb320.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/extcon/extcon-usbc-tusb320.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/extcon/extcon-usbc-tusb320.yaml b/Documentation/devicetree/bindings/extcon/extcon-usbc-tusb320.yaml new file mode 100644 index 000000000000..9875b4d5c356 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/extcon-usbc-tusb320.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/extcon-usbc-tusb320.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TUSB320 USB Type-C CC Logic controller + +maintainers: + - Michael Auchter + +properties: + compatible: + const: ti,tusb320 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + tusb320@61 { + compatible = "ti,tusb320"; + reg = <0x61>; + interrupt-parent = <&gpio>; + interrupts = <27 1>; + }; + }; +... -- cgit v1.2.3 From 0e77f8e1d0c22f768fb41f88ad14347b032c043f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 1 Nov 2020 01:43:56 +0100 Subject: extcon: fsa9480: Rewrite bindings in YAML and extend This rewrites the FSA9480 DT bindings using YAML and extends them with the compatible TI TSU6111. I chose to name the file fcs,fsa880 since this is the first switch, later versions are improvements. Signed-off-by: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/extcon/extcon-fsa9480.txt | 21 --------- .../devicetree/bindings/extcon/fcs,fsa880.yaml | 52 ++++++++++++++++++++++ 2 files changed, 52 insertions(+), 21 deletions(-) delete mode 100644 Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt create mode 100644 Documentation/devicetree/bindings/extcon/fcs,fsa880.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt b/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt deleted file mode 100644 index 624bd76f468e..000000000000 --- a/Documentation/devicetree/bindings/extcon/extcon-fsa9480.txt +++ /dev/null @@ -1,21 +0,0 @@ -FAIRCHILD SEMICONDUCTOR FSA9480 MICROUSB SWITCH - -The FSA9480 is a USB port accessory detector and switch. The FSA9480 is fully -controlled using I2C and enables USB data, stereo and mono audio, video, -microphone, and UART data to use a common connector port. - -Required properties: - - compatible : Must be one of - "fcs,fsa9480" - "fcs,fsa880" - - reg : Specifies i2c slave address. Must be 0x25. - - interrupts : Should contain one entry specifying interrupt signal of - interrupt parent to which interrupt pin of the chip is connected. - - Example: - musb@25 { - compatible = "fcs,fsa9480"; - reg = <0x25>; - interrupt-parent = <&gph2>; - interrupts = <7 0>; - }; diff --git a/Documentation/devicetree/bindings/extcon/fcs,fsa880.yaml b/Documentation/devicetree/bindings/extcon/fcs,fsa880.yaml new file mode 100644 index 000000000000..ef6a246a1337 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/fcs,fsa880.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/fcs,fsa880.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fairchild Semiconductor FSA880, FSA9480 and compatibles + +maintainers: + - Linus Walleij + +description: + The FSA880 and FSA9480 are USB port accessory detectors and switches. + The switch is fully controlled using I2C and enables USB data, stereo + and mono audio, video, microphone, and UART data to use a common + connector port. Compatible switches exist from other manufacturers. + +properties: + compatible: + enum: + - fcs,fsa880 + - fcs,fsa9480 + - ti,tsu6111 + + reg: + maxItems: 1 + description: The I2C address for an FSA880 compatible device is + usually 0x25. + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + usb-switch@25 { + compatible = "fcs,fsa880"; + reg = <0x25>; + interrupt-parent = <&gpio>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + }; -- cgit v1.2.3