From 79bfe480a0a0b259ab9fddcd2fe52c03542b1196 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 16 Feb 2021 00:58:49 +0900 Subject: firmware: xilinx: Remove zynqmp_pm_get_eemi_ops() in IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) zynqmp_pm_get_eemi_ops() was removed in commit 4db8180ffe7c: "Firmware: xilinx: Remove eemi ops for fpga related APIs", but not in IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE). Any driver who want to communicate with PMC using EEMI APIs use the functions provided for each function This removed zynqmp_pm_get_eemi_ops() in IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE), and also modify the documentation for this driver. Fixes: 4db8180ffe7c ("firmware: xilinx: Remove eemi ops for fpga related APIs") Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20210215155849.2425846-1-iwamatsu@nigauri.org Signed-off-by: Michal Simek --- Documentation/driver-api/xilinx/eemi.rst | 31 ++----------------------------- 1 file changed, 2 insertions(+), 29 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/xilinx/eemi.rst b/Documentation/driver-api/xilinx/eemi.rst index 9dcbc6f18d75..c1bc47b9000d 100644 --- a/Documentation/driver-api/xilinx/eemi.rst +++ b/Documentation/driver-api/xilinx/eemi.rst @@ -16,35 +16,8 @@ components running across different processing clusters on a chip or device to communicate with a power management controller (PMC) on a device to issue or respond to power management requests. -EEMI ops is a structure containing all eemi APIs supported by Zynq MPSoC. -The zynqmp-firmware driver maintain all EEMI APIs in zynqmp_eemi_ops -structure. Any driver who want to communicate with PMC using EEMI APIs -can call zynqmp_pm_get_eemi_ops(). - -Example of EEMI ops:: - - /* zynqmp-firmware driver maintain all EEMI APIs */ - struct zynqmp_eemi_ops { - int (*get_api_version)(u32 *version); - int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); - }; - - static const struct zynqmp_eemi_ops eemi_ops = { - .get_api_version = zynqmp_pm_get_api_version, - .query_data = zynqmp_pm_query_data, - }; - -Example of EEMI ops usage:: - - static const struct zynqmp_eemi_ops *eemi_ops; - u32 ret_payload[PAYLOAD_ARG_CNT]; - int ret; - - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - - ret = eemi_ops->query_data(qdata, ret_payload); +Any driver who wants to communicate with PMC using EEMI APIs use the +functions provided for each function. IOCTL ------ -- cgit v1.2.3 From f20b61b86a7503940cbe3da7f346e54adb86e7e4 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 10 Feb 2021 16:12:56 +0530 Subject: dt-bindings: power: Add rpm power domain bindings for SM8350 Add RPM power domain bindings for the SM8350 SoC Acked-by: Rob Herring Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210210104257.339462-1-vkoul@kernel.org [bjorn: Added dt-bindings include file changes from the driver patch] Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 1ea21acbbd55..42a0b8c97ea2 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -29,6 +29,7 @@ properties: - qcom,sdx55-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd + - qcom,sm8350-rpmhpd '#power-domain-cells': const: 1 diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index d711e250cf2c..cf1ffe890d66 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -45,6 +45,21 @@ #define SM8250_MX 8 #define SM8250_MX_AO 9 +/* SM8350 Power Domain Indexes */ +#define SM8350_CX 0 +#define SM8350_CX_AO 1 +#define SM8350_EBI 2 +#define SM8350_GFX 3 +#define SM8350_LCX 4 +#define SM8350_LMX 5 +#define SM8350_MMCX 6 +#define SM8350_MMCX_AO 7 +#define SM8350_MX 8 +#define SM8350_MX_AO 9 +#define SM8350_MXC 10 +#define SM8350_MXC_AO 11 +#define SM8350_MSS 12 + /* SC7180 Power Domain Indexes */ #define SC7180_CX 0 #define SC7180_CX_AO 1 -- cgit v1.2.3 From 9a3e49d749800e1f3e0185db0092d449a543843b Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 2 Mar 2021 11:18:11 +0530 Subject: dt-bindings: power: rpmpd: Add sc7280 to rpmpd binding Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm Technologies Inc sc7280 platform. Signed-off-by: Rajendra Nayak Link: https://lore.kernel.org/r/1614664092-9394-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 42a0b8c97ea2..ff21bfef8204 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -25,6 +25,7 @@ properties: - qcom,qcs404-rpmpd - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd + - qcom,sc7280-rpmhpd - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sm8150-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index cf1ffe890d66..eedb5d94c020 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -70,6 +70,17 @@ #define SC7180_LCX 6 #define SC7180_MSS 7 +/* SC7280 Power Domain Indexes */ +#define SC7280_CX 0 +#define SC7280_CX_AO 1 +#define SC7280_EBI 2 +#define SC7280_GFX 3 +#define SC7280_MX 4 +#define SC7280_MX_AO 5 +#define SC7280_LMX 6 +#define SC7280_LCX 7 +#define SC7280_MSS 8 + /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -- cgit v1.2.3 From cfe53781fc5f1c3cfed9513ebdcc3e87074de718 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Thu, 25 Feb 2021 15:00:17 +0530 Subject: dt-bindings: arm: msm: Add LLCC for SC7280 Add LLCC compatible for SC7280 SoC. Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/f3b32d437d7c1165a74ceec2cd52ff56b496e5a3.1614244789.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index c299dc907f6c..62fcbd883392 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -22,6 +22,7 @@ properties: compatible: enum: - qcom,sc7180-llcc + - qcom,sc7280-llcc - qcom,sdm845-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc -- cgit v1.2.3 From 28822aeae414582f6645c140d110778f3f0fd322 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Thu, 25 Feb 2021 15:00:22 +0530 Subject: dt-bindings: soc: qcom: aoss: Add SC7280 compatible Add SC7280 AOSS QMP compatible to the list of possible bindings. Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/8584e915f42405a7a4a799133a09d0d4aa65d2a8.1614244789.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt index 19c059e44681..783dc81b0f26 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -17,6 +17,7 @@ power-domains. Value type: Definition: must be one of: "qcom,sc7180-aoss-qmp" + "qcom,sc7280-aoss-qmp" "qcom,sdm845-aoss-qmp" "qcom,sm8150-aoss-qmp" "qcom,sm8250-aoss-qmp" -- cgit v1.2.3 From ddd6b7267fe6e3c5a48e2e4eda18f354595c6d65 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 11 Mar 2021 16:55:49 +0530 Subject: dt-bindings: firmware: scm: Add sc7280 support Add compatible for sc7280 SoC Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring Link: https://lore.kernel.org/r/1615461961-17716-3-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index a884955f861e..1edc31165d23 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -20,6 +20,7 @@ Required properties: * "qcom,scm-msm8996" * "qcom,scm-msm8998" * "qcom,scm-sc7180" + * "qcom,scm-sc7280" * "qcom,scm-sdm845" * "qcom,scm-sm8150" * "qcom,scm-sm8250" -- cgit v1.2.3 From a953e68ef2df657d8b65e16370e5808ec5819f23 Mon Sep 17 00:00:00 2001 From: Nicolas Saenz Julienne Date: Mon, 18 Jan 2021 13:32:42 +0100 Subject: dt-bindings: pwm: Add binding for RPi firmware PWM bus The PWM bus controlling the fan in RPi's official PoE hat can only be controlled by the board's co-processor. Signed-off-by: Nicolas Saenz Julienne Reviewed-by: Rob Herring --- .../arm/bcm/raspberrypi,bcm2835-firmware.yaml | 20 ++++++++++++++++++++ .../dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h | 13 +++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 include/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml index a2c63c8b1d10..e3664eab0f6a 100644 --- a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml @@ -64,6 +64,21 @@ properties: - compatible - "#reset-cells" + pwm: + type: object + + properties: + compatible: + const: raspberrypi,firmware-poe-pwm + + "#pwm-cells": + # See pwm.yaml in this directory for a description of the cells format. + const: 2 + + required: + - compatible + - "#pwm-cells" + additionalProperties: false required: @@ -87,5 +102,10 @@ examples: compatible = "raspberrypi,firmware-reset"; #reset-cells = <1>; }; + + pwm: pwm { + compatible = "raspberrypi,firmware-poe-pwm"; + #pwm-cells = <2>; + }; }; ... diff --git a/include/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h b/include/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h new file mode 100644 index 000000000000..27c5ce68847b --- /dev/null +++ b/include/dt-bindings/pwm/raspberrypi,firmware-poe-pwm.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Nicolas Saenz Julienne + * Author: Nicolas Saenz Julienne + */ + +#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_PWM_H +#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_PWM_H + +#define RASPBERRYPI_FIRMWARE_PWM_POE 0 +#define RASPBERRYPI_FIRMWARE_PWM_NUM 1 + +#endif -- cgit v1.2.3 From 42eb2fa14ac0c6253d2cf7003409933a7e52aac1 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Thu, 14 Jan 2021 18:53:38 +0100 Subject: dt-bindings: power: bcm-pmb: add BCM63138 binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PMB can be also found on bcm63xx chipsets. It uses difference device addresses so a new binding is required. Signed-off-by: Rafał Miłecki Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml b/Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml index 40b08d83c80b..f8e7ddbd2705 100644 --- a/Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml +++ b/Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - brcm,bcm4908-pmb + - brcm,bcm63138-pmb reg: description: register space of one or more buses -- cgit v1.2.3 From 4bcadf8d553593aae4c7daf7db7d6c65dd453167 Mon Sep 17 00:00:00 2001 From: Hsin-Hsiung Wang Date: Fri, 12 Mar 2021 23:34:44 +0800 Subject: dt-bindings: mediatek: add compatible for MT6873/8192 pwrap This adds dt-binding documentation of pwrap for Mediatek MT6873/8192 SoCs Platform. Signed-off-by: Hsin-Hsiung Wang Acked-by: Rob Herring Link: https://lore.kernel.org/r/1615563286-22126-4-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index ecac2bbeae45..8051c17e640e 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -22,6 +22,7 @@ Required properties in pwrap device node. "mediatek,mt6765-pwrap" for MT6765 SoCs "mediatek,mt6779-pwrap" for MT6779 SoCs "mediatek,mt6797-pwrap" for MT6797 SoCs + "mediatek,mt6873-pwrap" for MT6873/8192 SoCs "mediatek,mt7622-pwrap" for MT7622 SoCs "mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs -- cgit v1.2.3 From 4be3973c001ee627d220037d2be67a8e39cecc66 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 31 Mar 2021 02:04:40 +0300 Subject: dt-bindings: memory: tegra20: emc: Replace core regulator with power domain Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210330230445.26619-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index cc443fcf4bec..d2250498c36d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -23,7 +23,7 @@ For each opp entry in 'operating-points-v2' table: matches, the OPP gets enabled. Optional properties: -- core-supply: Phandle of voltage regulator of the SoC "core" power domain. +- power-domains: Phandle of the SoC "core" power domain. Child device nodes describe the memory settings for different configurations and clock rates. @@ -48,7 +48,7 @@ Example: interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; nvidia,memory-controller = <&mc>; - core-supply = <&core_vdd_reg>; + power-domains = <&domain>; operating-points-v2 = <&opp_table>; } -- cgit v1.2.3 From 7885db0ce77426df8bc82bb71d295263772afc3e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 31 Mar 2021 02:04:41 +0300 Subject: dt-bindings: memory: tegra30: emc: Replace core regulator with power domain Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210330230445.26619-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 0a2e2c0d0fdd..fb6af14cb49c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -39,9 +39,10 @@ properties: description: Phandle of the Memory Controller node. - core-supply: + power-domains: + maxItems: 1 description: - Phandle of voltage regulator of the SoC "core" power domain. + Phandle of the SoC "core" power domain. operating-points-v2: description: @@ -241,7 +242,7 @@ examples: nvidia,memory-controller = <&mc>; operating-points-v2 = <&dvfs_opp_table>; - core-supply = <&vdd_core>; + power-domains = <&domain>; #interconnect-cells = <0>; -- cgit v1.2.3 From 21e4e0d114d7f4341935cce3b0c2a93d9a0925b7 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 31 Mar 2021 02:04:42 +0300 Subject: dt-bindings: memory: tegra124: emc: Replace core regulator with power domain Power domain fits much better than a voltage regulator in regards to a proper hardware description and from a software perspective as well. Hence replace the core regulator with the power domain. Note that this doesn't affect any existing DTBs because we haven't started to use the regulator yet, and thus, it's okay to change it. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210330230445.26619-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 09bde65e1955..9163c3f12a85 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -37,9 +37,10 @@ properties: description: phandle of the memory controller node - core-supply: + power-domains: + maxItems: 1 description: - Phandle of voltage regulator of the SoC "core" power domain. + Phandle of the SoC "core" power domain. operating-points-v2: description: @@ -370,7 +371,7 @@ examples: nvidia,memory-controller = <&mc>; operating-points-v2 = <&dvfs_opp_table>; - core-supply = <&vdd_core>; + power-domains = <&domain>; #interconnect-cells = <0>; -- cgit v1.2.3 From d8d5cbc619e86b8f2167ae40d029a9d07e97b303 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 31 Mar 2021 02:04:43 +0300 Subject: dt-bindings: memory: tegra20: mc: Convert to schema Convert Tegra20 Memory Controller binding to schema. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210330230445.26619-5-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/nvidia,tegra20-mc.txt | 40 ----------- .../memory-controllers/nvidia,tegra20-mc.yaml | 79 ++++++++++++++++++++++ 2 files changed, 79 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt deleted file mode 100644 index 739b7c6f2e26..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ /dev/null @@ -1,40 +0,0 @@ -NVIDIA Tegra20 MC(Memory Controller) - -Required properties: -- compatible : "nvidia,tegra20-mc-gart" -- reg : Should contain 2 register ranges: physical base address and length of - the controller's registers and the GART aperture respectively. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - mc: the module's clock input -- interrupts : Should contain MC General interrupt. -- #reset-cells : Should be 1. This cell represents memory client module ID. - The assignments may be found in header file - or in the TRM documentation. -- #iommu-cells: Should be 0. This cell represents the number of cells in an - IOMMU specifier needed to encode an address. GART supports only a single - address space that is shared by all devices, therefore no additional - information needed for the address encoding. -- #interconnect-cells : Should be 1. This cell represents memory client. - The assignments may be found in header file . - -Example: - mc: memory-controller@7000f000 { - compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400 /* controller registers */ - 0x58000000 0x02000000>; /* GART aperture */ - clocks = <&tegra_car TEGRA20_CLK_MC>; - clock-names = "mc"; - interrupts = ; - #reset-cells = <1>; - #iommu-cells = <0>; - #interconnect-cells = <1>; - }; - - video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - ... - resets = <&mc TEGRA20_MC_RESET_VDE>; - iommus = <&mc>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml new file mode 100644 index 000000000000..55caf6905399 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 SoC Memory Controller + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +description: | + The Tegra20 Memory Controller merges request streams from various client + interfaces into request stream(s) for the various memory target devices, + and returns response data to the various clients. The Memory Controller + has a configurable arbitration algorithm to allow the user to fine-tune + performance among the various clients. + + Tegra20 Memory Controller includes the GART (Graphics Address Relocation + Table) which allows Memory Controller to provide a linear view of a + fragmented memory pages. + +properties: + compatible: + const: nvidia,tegra20-mc-gart + + reg: + items: + - description: controller registers + - description: GART registers + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 0 + + "#interconnect-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + - "#interconnect-cells" + +additionalProperties: false + +examples: + - | + memory-controller@7000f000 { + compatible = "nvidia,tegra20-mc-gart"; + reg = <0x7000f000 0x400>, /* Controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ + clocks = <&clock_controller 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <0>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; -- cgit v1.2.3 From f553ba158109a4c5b2e0f704fe5b9316375a1a9a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 11 Mar 2021 16:33:14 -0800 Subject: dt-bindings: soc: qcom: wcnss: Add firmware-name property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The WCNSS needs firmware which differs between platforms, and possibly boards. Add a new property "firmware-name" to allow the DT to specify the platform/board specific path to this firmware file. Acked-by: Rob Herring Tested-by: Aníbal Limón Link: https://lore.kernel.org/r/20210312003318.3273536-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt index 042a2e4159bd..1382b64e1381 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt @@ -24,6 +24,13 @@ block and a BT, WiFi and FM radio block, all using SMD as command channels. "qcom,riva", "qcom,pronto" +- firmware-name: + Usage: optional + Value type: + Definition: specifies the relative firmware image path for the WLAN NV + blob. Defaults to "wlan/prima/WCNSS_qcom_wlan_nv.bin" if + not specified. + = SUBNODES The subnodes of the wcnss node are optional and describe the individual blocks in the WCNSS. -- cgit v1.2.3 From e7be7853ab1b82d5b46fd14810995700a3bf3a05 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 5 Apr 2021 22:03:52 +0200 Subject: dt-bindings: mediatek: mmsys: add mt8167 binding Add binding documentation for MT8167 SoC. Signed-off-by: Fabien Parent Reviewed-by: Chun-Kuang Hu Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210405200354.2194930-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index d8c9108c3b4a..78c50733985c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -13,6 +13,7 @@ Required Properties: - "mediatek,mt6779-mmsys", "syscon" - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" + - "mediatek,mt8167-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" - "mediatek,mt8183-mmsys", "syscon" - #clock-cells: Must be 1 -- cgit v1.2.3 From baffc34d48b7a162f07cd842eeb37838612234ee Mon Sep 17 00:00:00 2001 From: "Chia-Wei, Wang" Date: Fri, 19 Mar 2021 16:57:32 +1030 Subject: dt-bindings: aspeed-lpc: Remove LPC partitioning The LPC controller has no concept of the BMC and the Host partitions. This patch fixes the documentation by removing the description on LPC partitions. The register offsets illustrated in the DTS node examples are also fixed to adapt to the LPC DTS change. Signed-off-by: Chia-Wei Wang Reviewed-by: Andrew Jeffery Acked-by: Rob Herring Acked-by: Lee Jones Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20210319062752.145730-1-andrew@aj.id.au Signed-off-by: Joel Stanley --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 100 ++++++--------------- 1 file changed, 25 insertions(+), 75 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index d0a38ba8b9ce..936aa108eab4 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -9,13 +9,7 @@ primary use case of the Aspeed LPC controller is as a slave on the bus conditions it can also take the role of bus master. The LPC controller is represented as a multi-function device to account for the -mix of functionality it provides. The principle split is between the register -layout at the start of the I/O space which is, to quote the Aspeed datasheet, -"basically compatible with the [LPC registers from the] popular BMC controller -H8S/2168[1]", and everything else, where everything else is an eclectic -collection of functions with a esoteric register layout. "Everything else", -here labeled the "host" portion of the controller, includes, but is not limited -to: +mix of functionality, which includes, but is not limited to: * An IPMI Block Transfer[2] Controller @@ -44,80 +38,36 @@ Required properties =================== - compatible: One of: - "aspeed,ast2400-lpc", "simple-mfd" - "aspeed,ast2500-lpc", "simple-mfd" - "aspeed,ast2600-lpc", "simple-mfd" + "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" + "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" + "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" - reg: contains the physical address and length values of the Aspeed LPC memory region. - #address-cells: <1> - #size-cells: <1> -- ranges: Maps 0 to the physical address and length of the LPC memory - region - -Required LPC Child nodes -======================== - -BMC Node --------- - -- compatible: One of: - "aspeed,ast2400-lpc-bmc" - "aspeed,ast2500-lpc-bmc" - "aspeed,ast2600-lpc-bmc" - -- reg: contains the physical address and length values of the - H8S/2168-compatible LPC controller memory region - -Host Node ---------- - -- compatible: One of: - "aspeed,ast2400-lpc-host", "simple-mfd", "syscon" - "aspeed,ast2500-lpc-host", "simple-mfd", "syscon" - "aspeed,ast2600-lpc-host", "simple-mfd", "syscon" - -- reg: contains the address and length values of the host-related - register space for the Aspeed LPC controller - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the address and length of the host-related LPC memory +- ranges: Maps 0 to the physical address and length of the LPC memory region Example: lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; + compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; reg = <0x1e789000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x1e789000 0x1000>; - lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2600-lpc-snoop"; reg = <0x0 0x80>; - }; - - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; - reg-io-width = <4>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80 0x1e0>; + interrupts = ; + snoop-ports = <0x80>; }; }; -BMC Node Children -================== - - -Host Node Children -================== LPC Host Interface Controller ------------------- @@ -149,14 +99,12 @@ Optional properties: Example: -lpc-host@80 { - lpc_ctrl: lpc-ctrl@0 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x0 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - memory-region = <&flash_memory>; - flash = <&spi>; - }; +lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x80 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; }; LPC Host Controller @@ -179,9 +127,9 @@ Required properties: Example: -lhc: lhc@20 { +lhc: lhc@a0 { compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; + reg = <0xa0 0x24 0xc8 0x8>; }; LPC reset control @@ -192,16 +140,18 @@ state of the LPC bus. Some systems may chose to modify this configuration. Required properties: - - compatible: "aspeed,ast2600-lpc-reset" or - "aspeed,ast2500-lpc-reset" - "aspeed,ast2400-lpc-reset" + - compatible: One of: + "aspeed,ast2600-lpc-reset"; + "aspeed,ast2500-lpc-reset"; + "aspeed,ast2400-lpc-reset"; + - reg: offset and length of the IP in the LHC memory region - #reset-controller indicates the number of reset cells expected Example: -lpc_reset: reset-controller@18 { +lpc_reset: reset-controller@98 { compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x18 0x4>; + reg = <0x98 0x4>; #reset-cells = <1>; }; -- cgit v1.2.3