From ce92d6743fd55331b2466e0b4e6fa004f2cc6cad Mon Sep 17 00:00:00 2001 From: "Sicelo A. Mhlongo" Date: Mon, 7 Mar 2022 15:25:00 +0200 Subject: dt-bindings: iio: st,st-sensors add LIS302DL Update st,st-sensors bindings for STMicroelectronics LIS302DL variant Reviewed-by: Linus Walleij Acked-by: Rob Herring Signed-off-by: Sicelo A. Mhlongo Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20220307132502.73854-2-absicsz@gmail.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/st,st-sensors.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml index 9735a2048255..fcb2902683c7 100644 --- a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml +++ b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml @@ -29,6 +29,7 @@ properties: - st,lis2dw12 - st,lis2hh12 - st,lis2dh12-accel + - st,lis302dl - st,lis331dl-accel - st,lis331dlh-accel - st,lis3de -- cgit v1.2.3 From c4dbfed37fef7e86a82cd28c97ca7d25b2516e37 Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Wed, 23 Mar 2022 13:15:49 +0100 Subject: dt-bindings: iio: imu: mpu6050: Document invensense,icm20608d ICM-20608-D differs from the other ICM-20608 variants by having a DMP (Digital Motion Processor) core tacked on. Despite having a different WHOAMI register, this variant is completely interchangeable with the other ICM-20608 variants by simply pretending the DMP core doesn't exist. Signed-off-by: Michael Srba Acked-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220323121550.16096-2-michael.srba@seznam.cz Signed-off-by: Jonathan Cameron --- .../bindings/iio/imu/invensense,mpu6050.yaml | 34 ++++++++++++---------- 1 file changed, 19 insertions(+), 15 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml index d69595a524c1..3ebc6526d82d 100644 --- a/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml +++ b/Documentation/devicetree/bindings/iio/imu/invensense,mpu6050.yaml @@ -14,21 +14,25 @@ description: | properties: compatible: - enum: - - invensense,iam20680 - - invensense,icm20608 - - invensense,icm20609 - - invensense,icm20689 - - invensense,icm20602 - - invensense,icm20690 - - invensense,mpu6000 - - invensense,mpu6050 - - invensense,mpu6500 - - invensense,mpu6515 - - invensense,mpu6880 - - invensense,mpu9150 - - invensense,mpu9250 - - invensense,mpu9255 + oneOf: + - enum: + - invensense,iam20680 + - invensense,icm20608 + - invensense,icm20609 + - invensense,icm20689 + - invensense,icm20602 + - invensense,icm20690 + - invensense,mpu6000 + - invensense,mpu6050 + - invensense,mpu6500 + - invensense,mpu6515 + - invensense,mpu6880 + - invensense,mpu9150 + - invensense,mpu9250 + - invensense,mpu9255 + - items: + - const: invensense,icm20608d + - const: invensense,icm20608 reg: maxItems: 1 -- cgit v1.2.3 From 210b9ddbcdbcb91d1ed45848863c7d4c68298278 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Mar 2022 21:47:16 +0200 Subject: dt-bindings: iio: adc: ti,ads1015: Add missing ADS1115 compatible string Add missing ti,ads1115 compatible string. This compatible string is supported by the Linux kernel driver and the ads1015 is a 12bit ADC while ads1115 is 16bit ADC. Add the missing compatible string. Acked-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Cc: Daniel Baluta Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20220328194725.149150-1-marex@denx.de Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml index 2c2d01bbc296..c31c80989cc9 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/adc/ti,ads1015.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI ADS1015 4 channel I2C analog to digital converter +title: TI ADS1015/ADS1115 4 channel I2C analog to digital converter maintainers: - Daniel Baluta @@ -15,7 +15,9 @@ description: | properties: compatible: - const: ti,ads1015 + enum: + - ti,ads1015 + - ti,ads1115 reg: maxItems: 1 -- cgit v1.2.3 From 94d9f3cb97f4a2c88d9040504cfcef114adb0741 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Mar 2022 21:47:17 +0200 Subject: dt-bindings: iio: adc: ti,ads1015: Add TLA2024 compatible string Add ti,tla2024 compatible string. This device is compatible with ADS1015 except it has no on-chip comparator. Acked-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Reviewed-by: Andy Shevchenko Cc: Daniel Baluta Cc: Rob Herring Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20220328194725.149150-2-marex@denx.de Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml index c31c80989cc9..a3b79438a13a 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml @@ -18,6 +18,7 @@ properties: enum: - ti,ads1015 - ti,ads1115 + - ti,tla2024 reg: maxItems: 1 -- cgit v1.2.3 From 60657fb9b19d4ff310bdebfd1fd5a075678c29fb Mon Sep 17 00:00:00 2001 From: Srinivasa Rao Mandadapu Date: Thu, 3 Mar 2022 19:32:08 +0530 Subject: dt-bindings: soundwire: qcom: Add bindings for audio clock reset control property Update description for audio clock reset control property, which is required for latest chipsets, to allow rx, tx and wsa bus clock enabling in software control mode by configuring dynamic clock gating control registers. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Stephen Boyd Acked-by: Rob Herring Link: https://lore.kernel.org/r/1646316128-21082-3-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt index 51ddbc509382..c85c25779e3f 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt +++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt @@ -162,6 +162,18 @@ board specific bus parameters. or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. +- reset: + Usage: optional + Value type: + Definition: Should specify the SoundWire audio CSR reset controller interface, + which is required for SoundWire version 1.6.0 and above. + +- reset-names: + Usage: optional + Value type: + Definition: should be "swr_audio_cgcr" for SoundWire audio CSR reset + controller interface. + Note: More Information on detail of encoding of these fields can be found in MIPI Alliance SoundWire 1.0 Specifications. @@ -180,6 +192,8 @@ soundwire: soundwire@c85 { interrupts = <20 IRQ_TYPE_EDGE_RISING>; clocks = <&wcc>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; #sound-dai-cells = <1>; qcom,dports-type = <0>; qcom,dout-ports = <6>; -- cgit v1.2.3 From 082ffee0505810bba7c4add343fa178861e26212 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 21 Mar 2022 14:33:14 +0100 Subject: dt-bindings: phy: qcom,qmp: Add SM6350 UFS PHY bindings Document the compatible string for the UFS PHY found in SM6350. Signed-off-by: Luca Weiss Acked-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220321133318.99406-3-luca.weiss@fairphone.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index e20d9b087bb8..5d7417c34c87 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -39,6 +39,7 @@ properties: - qcom,sdm845-qmp-usb3-phy - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm6115-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8150-qmp-usb3-phy - qcom,sm8150-qmp-usb3-uni-phy @@ -279,6 +280,7 @@ allOf: enum: - qcom,msm8998-qmp-ufs-phy - qcom,sdm845-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy - qcom,sc8180x-qmp-ufs-phy -- cgit v1.2.3 From cfe4c1021ef5621384878f1de0bc8fdab761a702 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 30 Mar 2022 19:55:11 +0900 Subject: dt-bindings: phy: uniphier-usb2: Add vbus-supply UniPhier USB2 PHY controller can apply vbus-supply. Add "vbus-supply" property to fix the following warning. uniphier-pro4-ace.dtb: usb-glue: phy@2: 'vbus-supply' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml Signed-off-by: Kunihiko Hayashi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1648637715-19262-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml index 479b203f7aa6..63dab914a48d 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb2-phy.yaml @@ -43,6 +43,9 @@ patternProperties: "#phy-cells": const: 0 + vbus-supply: + description: A phandle to the regulator for USB VBUS, only for USB host + required: - reg - "#phy-cells" -- cgit v1.2.3 From 61a37dc9c36fe4be455cef89e17388fa6e9c1e82 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 30 Mar 2022 19:55:12 +0900 Subject: dt-bindings: phy: uniphier-usb3ss: Treat vbus-supply as optional The usb-device doesn't need "vbus-supply" property, so the property should be removed from required. Signed-off-by: Kunihiko Hayashi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1648637715-19262-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml index 92d46eb913a3..06c957d52d23 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml @@ -61,7 +61,7 @@ properties: - const: phy vbus-supply: - description: A phandle to the regulator for USB VBUS + description: A phandle to the regulator for USB VBUS, only for USB host required: - compatible @@ -71,7 +71,6 @@ required: - clock-names - resets - reset-names - - vbus-supply additionalProperties: false -- cgit v1.2.3 From fccd2f32deb1bef32915b2240dfd603633eef960 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 30 Mar 2022 19:55:13 +0900 Subject: dt-bindings: phy: uniphier-ahci: Fix missing reset-names UniPhier AHCI PHY controller needs to specify 6 reset lines, so this adds missing "phy" to reset-names and increases maxItems of resets. Fixes: 34f92b67621f ("dt-bindings: phy: uniphier-ahci: Add bindings for Pro4 SoC") Signed-off-by: Kunihiko Hayashi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1648637715-19262-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml index 3b400a85b44a..14f7579e7daa 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -43,13 +43,14 @@ properties: resets: minItems: 2 - maxItems: 5 + maxItems: 6 reset-names: oneOf: - items: # for Pro4 - const: link - const: gio + - const: phy - const: pm - const: tx - const: rx -- cgit v1.2.3 From 45d1f841d5a4afb415415f9f87c9d4ce15e19f42 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 30 Mar 2022 19:55:14 +0900 Subject: dt-bindings: phy: uniphier-usb3hs: Fix incorrect clock-names and reset-names There is no clock-names and reset-names for Pro5 SoC, that should have two properties, "gio" and "link" like usb3-ssphy. And according to the existing PXs2 devicetree, the clock-names for PXs2 SoC should have "link" and "phy", and minItems of clocks should be 2. Fixes: 134ab2845acb ("dt-bindings: phy: Convert UniPhier USB3-PHY conroller to json-schema") Signed-off-by: Kunihiko Hayashi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1648637715-19262-5-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- .../bindings/phy/socionext,uniphier-usb3hs-phy.yaml | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml index 33946efcac5e..1bbd164f2527 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml @@ -31,12 +31,14 @@ properties: const: 0 clocks: - minItems: 1 + minItems: 2 maxItems: 3 clock-names: oneOf: - - const: link # for PXs2 + - items: # for Pro5 + - const: gio + - const: link - items: # for PXs3 with phy-ext - const: link - const: phy @@ -49,9 +51,13 @@ properties: maxItems: 2 reset-names: - items: - - const: link - - const: phy + oneOf: + - items: # for Pro5 + - const: gio + - const: link + - items: # for others + - const: link + - const: phy vbus-supply: description: A phandle to the regulator for USB VBUS -- cgit v1.2.3 From 09cc358a39d41152236e8f2653a94ab39b35cd3f Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 30 Mar 2022 19:55:15 +0900 Subject: dt-bindings: phy: uniphier: Clean up clocks, resets, and their names using compatible string Instead of "oneOf:" choices, use "allOf:" and "if:" to define clocks, clock-names, resets, and reset-names that can be taken by the compatible string. The order of clock-names and reset-names doesn't change here. Signed-off-by: Kunihiko Hayashi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1648637715-19262-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 90 +++++++++++++++----- .../bindings/phy/socionext,uniphier-pcie-phy.yaml | 47 ++++++++--- .../phy/socionext,uniphier-usb3hs-phy.yaml | 93 ++++++++++++++++----- .../phy/socionext,uniphier-usb3ss-phy.yaml | 95 +++++++++++++++++----- 4 files changed, 251 insertions(+), 74 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml index 14f7579e7daa..a3cd45acea28 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -30,33 +30,79 @@ properties: minItems: 1 maxItems: 2 - clock-names: - oneOf: - - items: # for PXs2 - - const: link - - items: # for Pro4 - - const: link - - const: gio - - items: # for others - - const: link - - const: phy + clock-names: true resets: minItems: 2 maxItems: 6 - reset-names: - oneOf: - - items: # for Pro4 - - const: link - - const: gio - - const: phy - - const: pm - - const: tx - - const: rx - - items: # for others - - const: link - - const: phy + reset-names: true + +allOf: + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pro4-ahci-phy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: gio + resets: + minItems: 6 + maxItems: 6 + reset-names: + items: + - const: link + - const: gio + - const: phy + - const: pm + - const: tx + - const: rx + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pxs2-ahci-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pxs3-ahci-phy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: phy + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy required: - compatible diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml index fbb71d6dd531..b3ed2f74a414 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml @@ -31,28 +31,51 @@ properties: minItems: 1 maxItems: 2 - clock-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - const: link # for others + clock-names: true resets: minItems: 1 maxItems: 2 - reset-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - const: link # for others + reset-names: true socionext,syscon: $ref: /schemas/types.yaml#/definitions/phandle description: A phandle to system control to set configurations for phy +allOf: + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pro5-pcie-phy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: gio + - const: link + else: + properties: + clocks: + maxItems: 1 + clock-names: + const: link + resets: + maxItems: 1 + reset-names: + const: link + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml index 1bbd164f2527..21e4414eea60 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml @@ -34,30 +34,12 @@ properties: minItems: 2 maxItems: 3 - clock-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - items: # for PXs3 with phy-ext - - const: link - - const: phy - - const: phy-ext - - items: # for others - - const: link - - const: phy + clock-names: true resets: maxItems: 2 - reset-names: - oneOf: - - items: # for Pro5 - - const: gio - - const: link - - items: # for others - - const: link - - const: phy + reset-names: true vbus-supply: description: A phandle to the regulator for USB VBUS @@ -80,6 +62,77 @@ properties: required for each port, if any one is omitted, the trimming data of the port will not be set at all. +allOf: + - if: + properties: + compatible: + contains: + const: socionext,uniphier-pro5-usb3-hsphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: gio + - const: link + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs2-usb3-hsphy + - socionext,uniphier-ld20-usb3-hsphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: phy + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs3-usb3-hsphy + - socionext,uniphier-nx1-usb3-hsphy + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + clock-names: + minItems: 2 + items: + - const: link + - const: phy + - const: phy-ext + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml index 06c957d52d23..4c26d2d2303d 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml @@ -35,34 +35,89 @@ properties: minItems: 2 maxItems: 3 - clock-names: - oneOf: - - items: # for Pro4, Pro5 - - const: gio - - const: link - - items: # for PXs3 with phy-ext - - const: link - - const: phy - - const: phy-ext - - items: # for others - - const: link - - const: phy + clock-names: true resets: maxItems: 2 - reset-names: - oneOf: - - items: # for Pro4,Pro5 - - const: gio - - const: link - - items: # for others - - const: link - - const: phy + reset-names: true vbus-supply: description: A phandle to the regulator for USB VBUS, only for USB host +allOf: + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pro4-usb3-ssphy + - socionext,uniphier-pro5-usb3-ssphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: gio + - const: link + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: gio + - const: link + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs2-usb3-ssphy + - socionext,uniphier-ld20-usb3-ssphy + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: link + - const: phy + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + - if: + properties: + compatible: + contains: + enum: + - socionext,uniphier-pxs3-usb3-ssphy + - socionext,uniphier-nx1-usb3-ssphy + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + clock-names: + minItems: 2 + items: + - const: link + - const: phy + - const: phy-ext + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: link + - const: phy + required: - compatible - reg -- cgit v1.2.3 From aa1855a79a95960cc51c51ce714d4cd4d3cf1757 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 12 Apr 2022 10:47:31 +0530 Subject: dt-bindings: phy: qcom,qmp: Add SDX65 USB PHY binding Add devicetree YAML binding for Qualcomm QMP Super Speed (SS) PHY found in SDX65. Signed-off-by: Rohit Agarwal Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1649740652-17515-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 5d7417c34c87..8b850c5ab116 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -58,6 +58,7 @@ properties: - qcom,sm8450-qmp-usb3-phy - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy reg: minItems: 1 @@ -164,6 +165,7 @@ allOf: contains: enum: - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy then: properties: clocks: -- cgit v1.2.3 From f9b0593dd4fc6ea766175d881a82f8d76b9d18a2 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 19 Apr 2022 09:08:50 +0800 Subject: dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch converts the mixel,mipi-dsi-phy binding to DT schema format using json-schema. Comparing to the plain text version, the new binding adds the 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' properites, otherwise 'make dtbs_check' would complain that there are mis-matches. Also, the new binding requires the 'power-domains' property since all potential SoCs that embed this PHY would provide a power domain for it. The example of the new binding takes reference to the latest dphy node in imx8mq.dtsi. Cc: Guido Günther Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Rob Herring Cc: NXP Linux Team Reviewed-by: Rob Herring Reviewed-by: Guido Günther Signed-off-by: Liu Ying Link: https://lore.kernel.org/r/20220419010852.452169-4-victor.liu@nxp.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 29 --------- .../bindings/phy/mixel,mipi-dsi-phy.yaml | 72 ++++++++++++++++++++++ 2 files changed, 72 insertions(+), 29 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt deleted file mode 100644 index 9b23407233c0..000000000000 --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt +++ /dev/null @@ -1,29 +0,0 @@ -Mixel DSI PHY for i.MX8 - -The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the -MIPI-DSI IP from Northwest Logic). It represents the physical layer for the -electrical signals for DSI. - -Required properties: -- compatible: Must be: - - "fsl,imx8mq-mipi-dphy" -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Must contain the following entries: - - "phy_ref": phandle and specifier referring to the DPHY ref clock -- reg: the register range of the PHY controller -- #phy-cells: number of cells in PHY, as defined in - Documentation/devicetree/bindings/phy/phy-bindings.txt - this must be <0> - -Optional properties: -- power-domains: phandle to power domain - -Example: - dphy: dphy@30a0030 { - compatible = "fsl,imx8mq-mipi-dphy"; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - reg = <0x30a00300 0x100>; - power-domains = <&pd_mipi0>; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml new file mode 100644 index 000000000000..c34f2e6d6bd5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mixel DSI PHY for i.MX8 + +maintainers: + - Guido Günther + +description: | + The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the + MIPI-DSI IP from Northwest Logic). It represents the physical layer for the + electrical signals for DSI. + +properties: + compatible: + enum: + - fsl,imx8mq-mipi-dphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: phy_ref + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + assigned-clock-rates: + maxItems: 1 + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - assigned-clock-rates + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + #include + dphy: dphy@30a0030 { + compatible = "fsl,imx8mq-mipi-dphy"; + reg = <0x30a00300 0x100>; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <24000000>; + #phy-cells = <0>; + power-domains = <&pgc_mipi>; + }; -- cgit v1.2.3 From 0ccb8385e92af90443791b7706675feb45b8b9f9 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 19 Apr 2022 09:08:51 +0800 Subject: dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Mixel MIPI DPHY + LVDS PHY combo IP as found on Freescale i.MX8qxp SoC. Cc: Guido Günther Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Rob Herring Cc: NXP Linux Team Reviewed-by: Rob Herring Reviewed-by: Guido Günther Signed-off-by: Liu Ying Link: https://lore.kernel.org/r/20220419010852.452169-5-victor.liu@nxp.com Signed-off-by: Vinod Koul --- .../bindings/phy/mixel,mipi-dsi-phy.yaml | 41 ++++++++++++++++++++-- 1 file changed, 38 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml index c34f2e6d6bd5..786cfd71cb7e 100644 --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml @@ -14,10 +14,14 @@ description: | MIPI-DSI IP from Northwest Logic). It represents the physical layer for the electrical signals for DSI. + The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work + in either MIPI-DSI PHY mode or LVDS PHY mode. + properties: compatible: enum: - fsl,imx8mq-mipi-dphy + - fsl,imx8qxp-mipi-dphy reg: maxItems: 1 @@ -40,6 +44,11 @@ properties: "#phy-cells": const: 0 + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers(CSR) module. + power-domains: maxItems: 1 @@ -48,12 +57,38 @@ required: - reg - clocks - clock-names - - assigned-clocks - - assigned-clock-parents - - assigned-clock-rates - "#phy-cells" - power-domains +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-mipi-dphy + then: + properties: + fsl,syscon: false + + required: + - assigned-clocks + - assigned-clock-parents + - assigned-clock-rates + + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-mipi-dphy + then: + properties: + assigned-clocks: false + assigned-clock-parents: false + assigned-clock-rates: false + + required: + - fsl,syscon + additionalProperties: false examples: -- cgit v1.2.3 From c20f80d0b89cf43be964797e6170f085b312ea01 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 15 Apr 2022 17:21:31 +0200 Subject: dt-bindings: sun6i-a31-mipi-dphy: Add optional direction property The Allwinner A31 MIPI D-PHY block supports both tx and rx directions, although each instance of the block is meant to be used in one direction only. There will typically be one instance for MIPI DSI and one for MIPI CSI-2 (it seems unlikely to ever see a shared instance). Describe the direction with a new allwinner,direction property. For backwards compatibility, the property is optional and tx mode should be assumed by default. Signed-off-by: Paul Kocialkowski Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220415152138.635525-2-paul.kocialkowski@bootlin.com Signed-off-by: Vinod Koul --- .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml index d0b541a461f3..22636c9fdab8 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml @@ -37,6 +37,18 @@ properties: resets: maxItems: 1 + allwinner,direction: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + Direction of the D-PHY: + - "rx" for receiving (e.g. when used with MIPI CSI-2); + - "tx" for transmitting (e.g. when used with MIPI DSI). + + enum: + - tx + - rx + default: tx + required: - "#phy-cells" - compatible -- cgit v1.2.3 From ea3364db9068e37bd8e12b9a99c7c92385593ed7 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 8 Apr 2022 14:48:34 -0700 Subject: dt-bindings: interconnect: qcom: Add sc8280xp binding The Qualcomm SC8280XP platform has the usual set of busses, add a binding for these interconnect providers and port definitions to allow interconnect paths to be expressed in the sc8280xp DeviceTree. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220408214835.624494-1-bjorn.andersson@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,rpmh.yaml | 12 ++ include/dt-bindings/interconnect/qcom,sc8280xp.h | 232 +++++++++++++++++++++ 2 files changed, 244 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,sc8280xp.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 5a911be0c2ea..0286f40fdc44 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -60,6 +60,18 @@ properties: - qcom,sc8180x-mc-virt - qcom,sc8180x-mmss-noc - qcom,sc8180x-system-noc + - qcom,sc8280xp-aggre1-noc + - qcom,sc8280xp-aggre2-noc + - qcom,sc8280xp-clk-virt + - qcom,sc8280xp-config-noc + - qcom,sc8280xp-dc-noc + - qcom,sc8280xp-gem-noc + - qcom,sc8280xp-lpass-ag-noc + - qcom,sc8280xp-mc-virt + - qcom,sc8280xp-mmss-noc + - qcom,sc8280xp-nspa-noc + - qcom,sc8280xp-nspb-noc + - qcom,sc8280xp-system-noc - qcom,sdm845-aggre1-noc - qcom,sdm845-aggre2-noc - qcom,sdm845-config-noc diff --git a/include/dt-bindings/interconnect/qcom,sc8280xp.h b/include/dt-bindings/interconnect/qcom,sc8280xp.h new file mode 100644 index 000000000000..a3e5fda7c127 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sc8280xp.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC8280XP_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SC8280XP_H + +/* aggre1_noc */ +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_QUP_2 2 +#define MASTER_A1NOC_CFG 3 +#define MASTER_IPA 4 +#define MASTER_EMAC_1 5 +#define MASTER_SDCC_4 6 +#define MASTER_UFS_MEM 7 +#define MASTER_USB3_0 8 +#define MASTER_USB3_1 9 +#define MASTER_USB3_MP 10 +#define MASTER_USB4_0 11 +#define MASTER_USB4_1 12 +#define SLAVE_A1NOC_SNOC 13 +#define SLAVE_USB_NOC_SNOC 14 +#define SLAVE_SERVICE_A1NOC 15 + +/* aggre2_noc */ +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_0 1 +#define MASTER_A2NOC_CFG 2 +#define MASTER_CRYPTO 3 +#define MASTER_SENSORS_PROC 4 +#define MASTER_SP 5 +#define MASTER_EMAC 6 +#define MASTER_PCIE_0 7 +#define MASTER_PCIE_1 8 +#define MASTER_PCIE_2A 9 +#define MASTER_PCIE_2B 10 +#define MASTER_PCIE_3A 11 +#define MASTER_PCIE_3B 12 +#define MASTER_PCIE_4 13 +#define MASTER_QDSS_ETR 14 +#define MASTER_SDCC_2 15 +#define MASTER_UFS_CARD 16 +#define SLAVE_A2NOC_SNOC 17 +#define SLAVE_ANOC_PCIE_GEM_NOC 18 +#define SLAVE_SERVICE_A2NOC 19 + +/* clk_virt */ +#define MASTER_IPA_CORE 0 +#define MASTER_QUP_CORE_0 1 +#define MASTER_QUP_CORE_1 2 +#define MASTER_QUP_CORE_2 3 +#define SLAVE_IPA_CORE 4 +#define SLAVE_QUP_CORE_0 5 +#define SLAVE_QUP_CORE_1 6 +#define SLAVE_QUP_CORE_2 7 + +/* config_noc */ +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AHB2PHY_0 2 +#define SLAVE_AHB2PHY_1 3 +#define SLAVE_AHB2PHY_2 4 +#define SLAVE_AOSS 5 +#define SLAVE_APPSS 6 +#define SLAVE_CAMERA_CFG 7 +#define SLAVE_CLK_CTL 8 +#define SLAVE_CDSP_CFG 9 +#define SLAVE_CDSP1_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_RBCPR_MMCX_CFG 12 +#define SLAVE_RBCPR_MX_CFG 13 +#define SLAVE_CPR_NSPCX 14 +#define SLAVE_CRYPTO_0_CFG 15 +#define SLAVE_CX_RDPM 16 +#define SLAVE_DCC_CFG 17 +#define SLAVE_DISPLAY_CFG 18 +#define SLAVE_DISPLAY1_CFG 19 +#define SLAVE_EMAC_CFG 20 +#define SLAVE_EMAC1_CFG 21 +#define SLAVE_GFX3D_CFG 22 +#define SLAVE_HWKM 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_IPC_ROUTER_CFG 26 +#define SLAVE_LPASS 27 +#define SLAVE_MX_RDPM 28 +#define SLAVE_MXC_RDPM 29 +#define SLAVE_PCIE_0_CFG 30 +#define SLAVE_PCIE_1_CFG 31 +#define SLAVE_PCIE_2A_CFG 32 +#define SLAVE_PCIE_2B_CFG 33 +#define SLAVE_PCIE_3A_CFG 34 +#define SLAVE_PCIE_3B_CFG 35 +#define SLAVE_PCIE_4_CFG 36 +#define SLAVE_PCIE_RSC_CFG 37 +#define SLAVE_PDM 38 +#define SLAVE_PIMEM_CFG 39 +#define SLAVE_PKA_WRAPPER_CFG 40 +#define SLAVE_PMU_WRAPPER_CFG 41 +#define SLAVE_QDSS_CFG 42 +#define SLAVE_QSPI_0 43 +#define SLAVE_QUP_0 44 +#define SLAVE_QUP_1 45 +#define SLAVE_QUP_2 46 +#define SLAVE_SDCC_2 47 +#define SLAVE_SDCC_4 48 +#define SLAVE_SECURITY 49 +#define SLAVE_SMMUV3_CFG 50 +#define SLAVE_SMSS_CFG 51 +#define SLAVE_SPSS_CFG 52 +#define SLAVE_TCSR 53 +#define SLAVE_TLMM 54 +#define SLAVE_UFS_CARD_CFG 55 +#define SLAVE_UFS_MEM_CFG 56 +#define SLAVE_USB3_0 57 +#define SLAVE_USB3_1 58 +#define SLAVE_USB3_MP 59 +#define SLAVE_USB4_0 60 +#define SLAVE_USB4_1 61 +#define SLAVE_VENUS_CFG 62 +#define SLAVE_VSENSE_CTRL_CFG 63 +#define SLAVE_VSENSE_CTRL_R_CFG 64 +#define SLAVE_A1NOC_CFG 65 +#define SLAVE_A2NOC_CFG 66 +#define SLAVE_ANOC_PCIE_BRIDGE_CFG 67 +#define SLAVE_DDRSS_CFG 68 +#define SLAVE_CNOC_MNOC_CFG 69 +#define SLAVE_SNOC_CFG 70 +#define SLAVE_SNOC_SF_BRIDGE_CFG 71 +#define SLAVE_IMEM 72 +#define SLAVE_PIMEM 73 +#define SLAVE_SERVICE_CNOC 74 +#define SLAVE_PCIE_0 75 +#define SLAVE_PCIE_1 76 +#define SLAVE_PCIE_2A 77 +#define SLAVE_PCIE_2B 78 +#define SLAVE_PCIE_3A 79 +#define SLAVE_PCIE_3B 80 +#define SLAVE_PCIE_4 81 +#define SLAVE_QDSS_STM 82 +#define SLAVE_SMSS 83 +#define SLAVE_TCU 84 + +/* dc_noc */ +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +/* gem_noc */ +#define MASTER_GPU_TCU 0 +#define MASTER_PCIE_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_COMPUTE_NOC_1 5 +#define MASTER_GEM_NOC_CFG 6 +#define MASTER_GFX3D 7 +#define MASTER_MNOC_HF_MEM_NOC 8 +#define MASTER_MNOC_SF_MEM_NOC 9 +#define MASTER_ANOC_PCIE_GEM_NOC 10 +#define MASTER_SNOC_GC_MEM_NOC 11 +#define MASTER_SNOC_SF_MEM_NOC 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_GEM_NOC_PCIE_CNOC 15 +#define SLAVE_SERVICE_GEM_NOC_1 16 +#define SLAVE_SERVICE_GEM_NOC_2 17 +#define SLAVE_SERVICE_GEM_NOC 18 + +/* lpass_ag_noc */ +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define MASTER_LPASS_PROC 1 +#define SLAVE_LPASS_CORE_CFG 2 +#define SLAVE_LPASS_LPI_CFG 3 +#define SLAVE_LPASS_MPU_CFG 4 +#define SLAVE_LPASS_TOP_CFG 5 +#define SLAVE_LPASS_SNOC 6 +#define SLAVE_SERVICES_LPASS_AML_NOC 7 +#define SLAVE_SERVICE_LPASS_AG_NOC 8 + +/* mc_virt */ +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +/*mmss_noc */ +#define MASTER_CAMNOC_HF 0 +#define MASTER_MDP0 1 +#define MASTER_MDP1 2 +#define MASTER_MDP_CORE1_0 3 +#define MASTER_MDP_CORE1_1 4 +#define MASTER_CNOC_MNOC_CFG 5 +#define MASTER_ROTATOR 6 +#define MASTER_ROTATOR_1 7 +#define MASTER_VIDEO_P0 8 +#define MASTER_VIDEO_P1 9 +#define MASTER_VIDEO_PROC 10 +#define MASTER_CAMNOC_ICP 11 +#define MASTER_CAMNOC_SF 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 +#define SLAVE_SERVICE_MNOC 15 + +/* nspa_noc */ +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_CDSP_MEM_NOC 2 +#define SLAVE_NSP_XFR 3 +#define SLAVE_SERVICE_NSP_NOC 4 + +/* nspb_noc */ +#define MASTER_CDSPB_NOC_CFG 0 +#define MASTER_CDSP_PROC_B 1 +#define SLAVE_CDSPB_MEM_NOC 2 +#define SLAVE_NSPB_XFR 3 +#define SLAVE_SERVICE_NSPB_NOC 4 + +/* system_noc */ +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_USB_NOC_SNOC 2 +#define MASTER_LPASS_ANOC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_SERVICE_SNOC 9 + +#endif -- cgit v1.2.3 From 95c33ae41b822c37dc841cf80ca388fea376e36d Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Mon, 18 Apr 2022 11:18:47 -0600 Subject: bus: mhi: host: Add soc_reset sysfs The MHI bus supports a standardized hardware reset, which is known as the "SoC Reset". This reset is similar to the reset sysfs for PCI devices - a hardware mechanism to reset the state back to square one. The MHI SoC Reset is described in the spec as a reset of last resort. If some unrecoverable error has occurred where other resets have failed, SoC Reset is the "big hammer" that ungracefully resets the device. This is effectivly the same as yanking the power on the device, and reapplying it. However, depending on the nature of the particular issue, the underlying transport link may remain active and configured. If the link remains up, the device will flag a MHI system error early in the boot process after the reset is executed, which allows the MHI bus to process a fatal error event, and clean up appropiately. While the SoC Reset is generally intended as a means of recovery when all else has failed, it can be useful in non-error scenarios. For example, if the device loads firmware from the host filesystem, the device may need to be fully rebooted inorder to pick up the new firmware. In this scenario, the system administrator may use the soc_reset sysfs to cause the device to pick up the new firmware that the admin placed on the filesystem. Signed-off-by: Jeffrey Hugo Reviewed-by: Bhaumik Bhatt Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1650302327-30439-1-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam --- Documentation/ABI/stable/sysfs-bus-mhi | 10 ++++++++++ drivers/bus/mhi/host/init.c | 14 ++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/stable/sysfs-bus-mhi b/Documentation/ABI/stable/sysfs-bus-mhi index ecfe7662f8d0..96ccc3385a2b 100644 --- a/Documentation/ABI/stable/sysfs-bus-mhi +++ b/Documentation/ABI/stable/sysfs-bus-mhi @@ -19,3 +19,13 @@ Description: The file holds the OEM PK Hash value of the endpoint device read without having the device power on at least once, the file will read all 0's. Users: Any userspace application or clients interested in device info. + +What: /sys/bus/mhi/devices/.../soc_reset +Date: April 2022 +KernelVersion: 5.19 +Contact: mhi@lists.linux.dev +Description: Initiates a SoC reset on the MHI controller. A SoC reset is + a reset of last resort, and will require a complete re-init. + This can be useful as a method of recovery if the device is + non-responsive, or as a means of loading new firmware as a + system administration task. diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index a665b8e92408..a8c18c5f1672 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -108,9 +108,23 @@ static ssize_t oem_pk_hash_show(struct device *dev, } static DEVICE_ATTR_RO(oem_pk_hash); +static ssize_t soc_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct mhi_device *mhi_dev = to_mhi_device(dev); + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + + mhi_soc_reset(mhi_cntrl); + return count; +} +static DEVICE_ATTR_WO(soc_reset); + static struct attribute *mhi_dev_attrs[] = { &dev_attr_serial_number.attr, &dev_attr_oem_pk_hash.attr, + &dev_attr_soc_reset.attr, NULL, }; ATTRIBUTE_GROUPS(mhi_dev); -- cgit v1.2.3 From d405ac52ab19301622bddabf4bf925d199937823 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 13 Apr 2022 18:23:34 +0530 Subject: dt-bindings: interconnect: Add Qualcomm SDX65 DT bindings Add interconnect IDs for Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1649854415-11174-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,rpmh.yaml | 3 + include/dt-bindings/interconnect/qcom,sdx65.h | 67 ++++++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,sdx65.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 5a911be0c2ea..9ee2a51d6ad7 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -72,6 +72,9 @@ properties: - qcom,sdx55-mc-virt - qcom,sdx55-mem-noc - qcom,sdx55-system-noc + - qcom,sdx65-mc-virt + - qcom,sdx65-mem-noc + - qcom,sdx65-system-noc - qcom,sm8150-aggre1-noc - qcom,sm8150-aggre2-noc - qcom,sm8150-camnoc-noc diff --git a/include/dt-bindings/interconnect/qcom,sdx65.h b/include/dt-bindings/interconnect/qcom,sdx65.h new file mode 100644 index 000000000000..b25288aa7d74 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdx65.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX65_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX65_H + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_TCU_0 0 +#define MASTER_SNOC_GC_MEM_NOC 1 +#define MASTER_APPSS_PROC 2 +#define SLAVE_LLCC 3 +#define SLAVE_MEM_NOC_SNOC 4 +#define SLAVE_MEM_NOC_PCIE_SNOC 5 + +#define MASTER_AUDIO 0 +#define MASTER_BLSP_1 1 +#define MASTER_QDSS_BAM 2 +#define MASTER_QPIC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_SPMI_FETCHER 5 +#define MASTER_ANOC_SNOC 6 +#define MASTER_IPA 7 +#define MASTER_MEM_NOC_SNOC 8 +#define MASTER_MEM_NOC_PCIE_SNOC 9 +#define MASTER_CRYPTO 10 +#define MASTER_IPA_PCIE 11 +#define MASTER_PCIE_0 12 +#define MASTER_QDSS_ETR 13 +#define MASTER_SDCC_1 14 +#define MASTER_USB3 15 +#define SLAVE_AOSS 16 +#define SLAVE_APPSS 17 +#define SLAVE_AUDIO 18 +#define SLAVE_BLSP_1 19 +#define SLAVE_CLK_CTL 20 +#define SLAVE_CRYPTO_0_CFG 21 +#define SLAVE_CNOC_DDRSS 22 +#define SLAVE_ECC_CFG 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_CNOC_MSS 26 +#define SLAVE_PCIE_PARF 27 +#define SLAVE_PDM 28 +#define SLAVE_PRNG 29 +#define SLAVE_QDSS_CFG 30 +#define SLAVE_QPIC 31 +#define SLAVE_SDCC_1 32 +#define SLAVE_SNOC_CFG 33 +#define SLAVE_SPMI_FETCHER 34 +#define SLAVE_SPMI_VGI_COEX 35 +#define SLAVE_TCSR 36 +#define SLAVE_TLMM 37 +#define SLAVE_USB3 38 +#define SLAVE_USB3_PHY_CFG 39 +#define SLAVE_ANOC_SNOC 40 +#define SLAVE_SNOC_MEM_NOC_GC 41 +#define SLAVE_IMEM 42 +#define SLAVE_SERVICE_SNOC 43 +#define SLAVE_PCIE_0 44 +#define SLAVE_QDSS_STM 45 +#define SLAVE_TCU 46 + +#endif -- cgit v1.2.3 From eb5e26a491d17f520921b7e236b3bf0520553542 Mon Sep 17 00:00:00 2001 From: Nuno Sá Date: Mon, 4 Apr 2022 10:49:59 +0200 Subject: dt-bindings: iio: dac: change ad3552r maintainer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the maintainer email no longer exists, change it to myself. Signed-off-by: Nuno Sá Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220404085000.249423-2-nuno.sa@analog.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index 501a463e5d88..9c48c76993fe 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices AD2552R DAC device driver maintainers: - - Mihail Chindris + - Nuno Sá description: | Bindings for the Analog Devices AD3552R DAC device and similar. -- cgit v1.2.3 From 180ab171616119a1343924db1e281c48bfbee6be Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Mon, 4 Apr 2022 21:24:44 +0200 Subject: dt-bindings: iio: imu: st_lsm6dsx: add asm330lhhx device bindings Add device bindings for asm330lhhx IMU sensor. Use lsm6dsr as fallback device for asm330lhhx since it implements all the features currently supported by asm330lhhx. Signed-off-by: Lorenzo Bianconi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/2e5304b7e11085d4e701b4b591fd79cc54f01301.1649100168.git.lorenzo@kernel.org Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/imu/st,lsm6dsx.yaml | 38 ++++++++++++---------- 1 file changed, 21 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml index 0750f700a143..5d4839f00898 100644 --- a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml +++ b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml @@ -14,23 +14,27 @@ description: properties: compatible: - enum: - - st,lsm6ds3 - - st,lsm6ds3h - - st,lsm6dsl - - st,lsm6dsm - - st,ism330dlc - - st,lsm6dso - - st,asm330lhh - - st,lsm6dsox - - st,lsm6dsr - - st,lsm6ds3tr-c - - st,ism330dhcx - - st,lsm9ds1-imu - - st,lsm6ds0 - - st,lsm6dsrx - - st,lsm6dst - - st,lsm6dsop + oneOf: + - enum: + - st,lsm6ds3 + - st,lsm6ds3h + - st,lsm6dsl + - st,lsm6dsm + - st,ism330dlc + - st,lsm6dso + - st,asm330lhh + - st,lsm6dsox + - st,lsm6dsr + - st,lsm6ds3tr-c + - st,ism330dhcx + - st,lsm9ds1-imu + - st,lsm6ds0 + - st,lsm6dsrx + - st,lsm6dst + - st,lsm6dsop + - items: + - const: st,asm330lhhx + - const: st,lsm6dsr reg: maxItems: 1 -- cgit v1.2.3 From 42763b249aaa0ec8950b433c3cbed021c9779a95 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 23 Apr 2022 14:16:54 +0100 Subject: dt-bindings: iio: adc: Document Renesas RZ/V2L ADC Document renesas RZ/V2L ADC bindings. RZ/V2L ADC is identical to RZ/G2L with same number of channels. While at it remove RZ/G2LC SoC from binding documentation as it does not support ADC. Signed-off-by: Biju Das Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220423131654.131390-1-biju.das.jz@bp.renesas.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml index c80201d6a716..d66c24cae1e1 100644 --- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml @@ -19,7 +19,8 @@ properties: compatible: items: - enum: - - renesas,r9a07g044-adc # RZ/G2{L,LC} + - renesas,r9a07g044-adc # RZ/G2L + - renesas,r9a07g054-adc # RZ/V2L - const: renesas,rzg2l-adc reg: -- cgit v1.2.3 From b71b538b477f4ab7bb8bf39d1fa40e9f296df8b6 Mon Sep 17 00:00:00 2001 From: Arnaud Ferraris Date: Wed, 20 Apr 2022 13:25:39 +0200 Subject: dt-bindings: iio: light: stk33xx: Add proximity-near-level This allows exporting the value from which userspace should assert an object is "near". Signed-off-by: Arnaud Ferraris Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220420112540.91907-2-arnaud.ferraris@collabora.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/light/stk33xx.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/light/stk33xx.yaml b/Documentation/devicetree/bindings/iio/light/stk33xx.yaml index f92bf7b2b7f0..f6e22dc9814a 100644 --- a/Documentation/devicetree/bindings/iio/light/stk33xx.yaml +++ b/Documentation/devicetree/bindings/iio/light/stk33xx.yaml @@ -13,6 +13,9 @@ maintainers: description: | Ambient light and proximity sensor over an i2c interface. +allOf: + - $ref: ../common.yaml# + properties: compatible: enum: @@ -26,6 +29,8 @@ properties: interrupts: maxItems: 1 + proximity-near-level: true + required: - compatible - reg @@ -44,6 +49,7 @@ examples: stk3310@48 { compatible = "sensortek,stk3310"; reg = <0x48>; + proximity-near-level = <25>; interrupt-parent = <&gpio1>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; }; -- cgit v1.2.3 From 392eeccc3b593558694f7caaf855bc2b827c5b0b Mon Sep 17 00:00:00 2001 From: Cixi Geng Date: Tue, 19 Apr 2022 22:24:52 +0800 Subject: dt-bindings:iio:adc: add sprd,ump9620-adc dt-binding sprd,ump9620-adc is one variant of sc27xx series, add ump9620 description and sample in dt-bindings. Signed-off-by: Cixi Geng Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220419142458.884933-2-gengcixi@gmail.com Signed-off-by: Jonathan Cameron --- .../bindings/iio/adc/sprd,sc2720-adc.yaml | 60 +++++++++++++++++++--- 1 file changed, 54 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml b/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml index caa3ee0b4b8c..44aa28b59197 100644 --- a/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/sprd,sc2720-adc.yaml @@ -20,6 +20,7 @@ properties: - sprd,sc2723-adc - sprd,sc2730-adc - sprd,sc2731-adc + - sprd,ump9620-adc reg: maxItems: 1 @@ -33,13 +34,39 @@ properties: hwlocks: maxItems: 1 - nvmem-cells: - maxItems: 2 + nvmem-cells: true - nvmem-cell-names: - items: - - const: big_scale_calib - - const: small_scale_calib + nvmem-cell-names: true + +allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - sprd,ump9620-adc + then: + properties: + nvmem-cells: + maxItems: 2 + nvmem-cell-names: + items: + - const: big_scale_calib + - const: small_scale_calib + + else: + properties: + nvmem-cells: + maxItems: 6 + nvmem-cell-names: + items: + - const: big_scale_calib1 + - const: big_scale_calib2 + - const: small_scale_calib1 + - const: small_scale_calib2 + - const: vbat_det_cal1 + - const: vbat_det_cal2 required: - compatible @@ -69,4 +96,25 @@ examples: nvmem-cell-names = "big_scale_calib", "small_scale_calib"; }; }; + + - | + #include + pmic { + #address-cells = <1>; + #size-cells = <0>; + adc@504 { + compatible = "sprd,ump9620-adc"; + reg = <0x504>; + interrupt-parent = <&ump9620_pmic>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + hwlocks = <&hwlock 4>; + nvmem-cells = <&adc_bcal1>, <&adc_bcal2>, + <&adc_scal1>, <&adc_scal2>, + <&vbat_det_cal1>, <&vbat_det_cal2>; + nvmem-cell-names = "big_scale_calib1", "big_scale_calib2", + "small_scale_calib1", "small_scale_calib2", + "vbat_det_cal1", "vbat_det_cal2"; + }; + }; ... -- cgit v1.2.3 From e678acedf364a8843388af4e1e0ebe854f2e0e8c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 22 Apr 2022 14:20:39 -0500 Subject: dt-bindings: iio: Fix incorrect compatible strings in examples Fix a couple of examples using incorrect compatible strings. Signed-off-by: Rob Herring Reviewed-by: Slawomir Stepien Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220422192039.2590548-1-robh@kernel.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml | 2 +- .../devicetree/bindings/iio/potentiometer/microchip,mcp4131.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml b/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml index edf804d0aca2..b1eb77335d05 100644 --- a/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml +++ b/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml @@ -68,7 +68,7 @@ examples: #size-cells = <0>; dac@0 { - compatible = "lltc,ltc2632"; + compatible = "lltc,ltc2632-l12"; reg = <0>; /* CS0 */ spi-max-frequency = <1000000>; vref-supply = <&vref>; diff --git a/Documentation/devicetree/bindings/iio/potentiometer/microchip,mcp4131.yaml b/Documentation/devicetree/bindings/iio/potentiometer/microchip,mcp4131.yaml index 945a2d644ddc..32e92bced81f 100644 --- a/Documentation/devicetree/bindings/iio/potentiometer/microchip,mcp4131.yaml +++ b/Documentation/devicetree/bindings/iio/potentiometer/microchip,mcp4131.yaml @@ -95,7 +95,7 @@ examples: #size-cells = <0>; potentiometer@0 { - compatible = "mcp4131-502"; + compatible = "microchip,mcp4131-502"; reg = <0>; spi-max-frequency = <500000>; }; -- cgit v1.2.3 From c4f2a32a7fc212a843f0540822a6f1880d176267 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 22 Apr 2022 14:20:54 -0500 Subject: dt-bindings: phy: marvell,armada-3700-utmi-host-phy: Fix incorrect compatible in example Fix the example using the incorrect compatible string. Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220422192054.2591093-1-robh@kernel.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml index 2437c3683326..632d61c07f40 100644 --- a/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml @@ -45,7 +45,7 @@ additionalProperties: false examples: - | usb2_utmi_host_phy: phy@5f000 { - compatible = "marvell,armada-3700-utmi-host-phy"; + compatible = "marvell,a3700-utmi-host-phy"; reg = <0x5f000 0x800>; marvell,usb-misc-reg = <&usb2_syscon>; #phy-cells = <0>; -- cgit v1.2.3 From bc055a50a8594a634e09a7286601d0d2bd51c734 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 23 Apr 2022 14:47:52 +0100 Subject: dt-bindings: phy: renesas,usb2-phy: Document RZ/G2UL phy bindings Document USB phy bindings for RZ/G2UL SoC. RZ/G2UL USB phy is identical to one found on the RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,rzg2l-usb2-phy" will be used as a fallback. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220423134752.143090-1-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 16807bbbdcb1..f82649a55e91 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -32,6 +32,7 @@ properties: - items: - enum: + - renesas,usb2-phy-r9a07g043 # RZ/G2UL - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC} - renesas,usb2-phy-r9a07g054 # RZ/V2L - const: renesas,rzg2l-usb2-phy -- cgit v1.2.3 From 7177042bdd1605b6c8d6b5c65a72f3e389690eaf Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Fri, 29 Apr 2022 17:26:49 +0100 Subject: dt-bindings: nvmem: Add apple,efuses Apple SoCs come with eFuses used to store factory-programmed data such as calibration settings for the PCIe and Type-C PHY. Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Sven Peter Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220429162701.2222-5-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/apple,efuses.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/apple,efuses.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/apple,efuses.yaml b/Documentation/devicetree/bindings/nvmem/apple,efuses.yaml new file mode 100644 index 000000000000..5ec8f2bdb3a5 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/apple,efuses.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/apple,efuses.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC eFuse-based NVMEM + +description: | + Apple SoCs such as the M1 contain factory-programmed eFuses used to e.g. store + calibration data for the PCIe and the Type-C PHY or unique chip identifiers + such as the ECID. + +maintainers: + - Sven Peter + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + items: + - enum: + - apple,t8103-efuses + - apple,t6000-efuses + - const: apple,efuses + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + efuse@3d2bc000 { + compatible = "apple,t8103-efuses", "apple,efuses"; + reg = <0x3d2bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ecid: efuse@500 { + reg = <0x500 0x8>; + }; + }; + +... -- cgit v1.2.3 From c75945ac2e503375a5fcd44684a5243df07a6158 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 29 Apr 2022 17:26:56 +0100 Subject: dt-bindings: nvmem: sfp: Fix typo There is a small grammatical error in the description. Fix it. Reviewed-by: Michael Walle Reviewed-by: Andrew Lunn Signed-off-by: Sean Anderson Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220429162701.2222-12-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml index 80914b93638e..b7798e903191 100644 --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml @@ -10,7 +10,7 @@ maintainers: - Michael Walle description: | - SFP is the security fuse processor which among other things provide a + SFP is the security fuse processor which among other things provides a unique identifier per part. allOf: -- cgit v1.2.3 From 8cb0cd68bef75af5ac8ef93f3314d4f8dc8767a3 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 29 Apr 2022 17:26:57 +0100 Subject: dt-bindings: nvmem: sfp: Add clock properties To program fuses, it is necessary to set the fuse programming time. This is determined based on the value of the platform clock. Add a clock property. Because this property is necessary for programming, it is made mandatory. Since these bindings have not yet been present in a stable release (though they are on track for 5.18), it is not an ABI break to change them in this manner. Signed-off-by: Sean Anderson Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220429162701.2222-13-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml index b7798e903191..54086f50157d 100644 --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml @@ -24,15 +24,29 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 1 + description: + The SFP clock. Typically, this is the platform clock divided by 4. + + clock-names: + const: sfp + required: - compatible - reg + - clock-names + - clocks unevaluatedProperties: false examples: - | + #include efuse@1e80000 { compatible = "fsl,ls1028a-sfp"; reg = <0x1e80000 0x8000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; + clock-names = "sfp"; }; -- cgit v1.2.3 From 54eb278a06128a83973390fc8b06acf4d6c0675b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 29 Apr 2022 17:26:58 +0100 Subject: dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply The TA_PROG_SFP supply must be enabled to program the fuses, and disabled to read the fuses (such as at power-on-reset). On many boards, this supply is controlled by a jumper. The user must manually insert or remove it at the appropriate time in the programming process. However, on other boards this supply is controlled by an FPGA or a GPIO. In these cases, the driver can automatically enable and disable it as necessary. Reviewed-by: Andrew Lunn Signed-off-by: Sean Anderson Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220429162701.2222-14-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml index 54086f50157d..c5d7375b840a 100644 --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml @@ -32,6 +32,11 @@ properties: clock-names: const: sfp + ta-prog-sfp-supply: + description: + The regulator for the TA_PROG_SFP pin. It will be enabled for programming + and disabled for reading. + required: - compatible - reg -- cgit v1.2.3 From 60ed1f7cecbdaf0e3f2d62ca53d118138f4065e0 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 29 Apr 2022 17:26:59 +0100 Subject: dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs Trust Architecture (TA) 2.1 devices include the LS1012A, LS1021A, LS1043A, and LS1046A. The SFP device on TA 2.1 devices is very similar to the SFP on TA 3.0 devices. The primary difference is a few fields in the control register. Add a compatible string. Signed-off-by: Sean Anderson Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220429162701.2222-15-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml index c5d7375b840a..3b4e6e94cb81 100644 --- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml +++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml @@ -18,8 +18,13 @@ allOf: properties: compatible: - enum: - - fsl,ls1028a-sfp + oneOf: + - description: Trust architecture 2.1 SFP + items: + - const: fsl,ls1021a-sfp + - description: Trust architecture 3.0 SFP + items: + - const: fsl,ls1028a-sfp reg: maxItems: 1 -- cgit v1.2.3 From 2b28c9e0fe97fa2bae2ab52540a2970c0d3bdf8d Mon Sep 17 00:00:00 2001 From: Tianfei zhang Date: Mon, 18 Apr 2022 23:29:42 -0400 Subject: Documentation: fpga: dfl: add link address of feature id table This patch adds the link address of feature id table in documentation. Signed-off-by: Tianfei zhang Reviewed-by: Matthew Gerlach Acked-by: Moritz Fischer Acked-by: Wu Hao Link: https://lore.kernel.org/r/20220419032942.427429-3-tianfei.zhang@intel.com Signed-off-by: Xu Yilun --- Documentation/fpga/dfl.rst | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..15b670926084 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Please refer to below link to existing feature id table and guide for new feature +ids application. +https://github.com/OPAE/dfl-feature-id + + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the -- cgit v1.2.3 From 9869ba6dc9302624fc024c0a5ead4137d9de150b Mon Sep 17 00:00:00 2001 From: Markuss Broks Date: Sat, 12 Mar 2022 20:41:53 +0200 Subject: dt-bindings: extcon: bindings for SM5703 This patch adds device-tree bindings for Silicon Mitus SM5703 MUIC. Signed-off-by: Markuss Broks Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml b/Documentation/devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml index fd2e55088888..7a224b2f0977 100644 --- a/Documentation/devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml +++ b/Documentation/devicetree/bindings/extcon/siliconmitus,sm5502-muic.yaml @@ -20,11 +20,12 @@ properties: enum: - siliconmitus,sm5502-muic - siliconmitus,sm5504-muic + - siliconmitus,sm5703-muic reg: maxItems: 1 - description: I2C slave address of the device. Usually 0x25 for SM5502, - 0x14 for SM5504. + description: I2C slave address of the device. Usually 0x25 for SM5502 + and SM5703, 0x14 for SM5504. interrupts: maxItems: 1 -- cgit v1.2.3 From b9e2a1d50e36688d9e515cd981bf3e501a300451 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 3 May 2022 14:19:22 -0700 Subject: dt-bindings: interconnect: Add SC8180X QUP0 virt provider Add compatible for the QUP0 BCM provider found in SC8180X. Signed-off-by: Bjorn Andersson Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220503211925.1022169-2-bjorn.andersson@linaro.org Signed-off-by: Georgi Djakov --- Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 5a911be0c2ea..f87fecf5a60c 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -59,6 +59,7 @@ properties: - qcom,sc8180x-ipa-virt - qcom,sc8180x-mc-virt - qcom,sc8180x-mmss-noc + - qcom,sc8180x-qup-virt - qcom,sc8180x-system-noc - qcom,sdm845-aggre1-noc - qcom,sdm845-aggre2-noc -- cgit v1.2.3 From 3be0ec65fd17b9677d0a4c8913ee359bd941da5d Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 14 Apr 2022 17:58:28 -0700 Subject: dt-bindings: interconnect: Remove sc7180/sdx55 ipa compatibles These interconnects are modeled as clks, not interconnects, therefore remove the compatibles from the binding as they're unused. Cc: Alex Elder Cc: Taniya Das Cc: Mike Tipton Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20220415005828.1980055-3-swboyd@chromium.org Signed-off-by: Georgi Djakov --- Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index cf684640fe6d..28b3516aa089 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -31,7 +31,6 @@ properties: - qcom,sc7180-config-noc - qcom,sc7180-dc-noc - qcom,sc7180-gem-noc - - qcom,sc7180-ipa-virt - qcom,sc7180-mc-virt - qcom,sc7180-mmss-noc - qcom,sc7180-npu-noc @@ -81,7 +80,6 @@ properties: - qcom,sdm845-mem-noc - qcom,sdm845-mmss-noc - qcom,sdm845-system-noc - - qcom,sdx55-ipa-virt - qcom,sdx55-mc-virt - qcom,sdx55-mem-noc - qcom,sdx55-system-noc -- cgit v1.2.3 From d0b59cf68cecf48cc3e7ab817046a221967fbf8c Mon Sep 17 00:00:00 2001 From: Ohad Sharabi Date: Tue, 22 Mar 2022 14:32:40 +0200 Subject: habanalabs/gaudi: add debugfs to fetch internal sync status When Gaudi device is secured the monitors data in the configuration space is blocked from PCI access. As we need to enable user to get sync-manager monitors registers when debugging, this patch adds a debugfs that dumps the information to a binary file (blob). When a root user will trigger the dump, the driver will send request to the f/w to fill a data structure containing dump of all monitors registers. Signed-off-by: Ohad Sharabi Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/debugfs-driver-habanalabs | 24 ++++++ drivers/misc/habanalabs/common/debugfs.c | 87 +++++++++++++++++++--- drivers/misc/habanalabs/common/firmware_if.c | 48 ++++++++++++ drivers/misc/habanalabs/common/habanalabs.h | 13 +++- drivers/misc/habanalabs/gaudi/gaudi.c | 11 +++ drivers/misc/habanalabs/goya/goya.c | 6 ++ drivers/misc/habanalabs/include/common/cpucp_if.h | 38 ++++++++++ 7 files changed, 211 insertions(+), 16 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index bcf6915987e4..84bf3da2bb27 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -190,6 +190,30 @@ Description: Check and display page fault or access violation mmu errors for echo "0x200" > /sys/kernel/debug/habanalabs/hl0/mmu_error cat /sys/kernel/debug/habanalabs/hl0/mmu_error +What: /sys/kernel/debug/habanalabs/hl/monitor_dump +Date: Mar 2022 +KernelVersion: 5.19 +Contact: osharabi@habana.ai +Description: Allows the root user to dump monitors status from the device's + protected config space. + This property is a binary blob that contains the result of the + monitors registers dump. + This custom interface is needed (instead of using the generic + Linux user-space PCI mapping) because this space is protected + and cannot be accessed using PCI read. + This interface doesn't support concurrency in the same device. + Only supported on GAUDI. + +What: /sys/kernel/debug/habanalabs/hl/monitor_dump_trig +Date: Mar 2022 +KernelVersion: 5.19 +Contact: osharabi@habana.ai +Description: Triggers dump of monitor data. The value to trigger the operation + must be 1. Triggering the monitor dump operation initiates dump of + current registers values of all monitors. + When the write is finished, the user can read the "monitor_dump" + blob + What: /sys/kernel/debug/habanalabs/hl/set_power_state Date: Jan 2019 KernelVersion: 5.1 diff --git a/drivers/misc/habanalabs/common/debugfs.c b/drivers/misc/habanalabs/common/debugfs.c index f18495545854..30c637eaf59b 100644 --- a/drivers/misc/habanalabs/common/debugfs.c +++ b/drivers/misc/habanalabs/common/debugfs.c @@ -829,23 +829,67 @@ static ssize_t hl_dma_size_write(struct file *f, const char __user *buf, } /* Free the previous allocation, if there was any */ - entry->blob_desc.size = 0; - vfree(entry->blob_desc.data); + entry->data_dma_blob_desc.size = 0; + vfree(entry->data_dma_blob_desc.data); - entry->blob_desc.data = vmalloc(size); - if (!entry->blob_desc.data) + entry->data_dma_blob_desc.data = vmalloc(size); + if (!entry->data_dma_blob_desc.data) return -ENOMEM; rc = hdev->asic_funcs->debugfs_read_dma(hdev, addr, size, - entry->blob_desc.data); + entry->data_dma_blob_desc.data); if (rc) { dev_err(hdev->dev, "Failed to DMA from 0x%010llx\n", addr); - vfree(entry->blob_desc.data); - entry->blob_desc.data = NULL; + vfree(entry->data_dma_blob_desc.data); + entry->data_dma_blob_desc.data = NULL; return -EIO; } - entry->blob_desc.size = size; + entry->data_dma_blob_desc.size = size; + + return count; +} + +static ssize_t hl_monitor_dump_trigger(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 size, trig; + ssize_t rc; + + if (hdev->reset_info.in_reset) { + dev_warn_ratelimited(hdev->dev, "Can't dump monitors during reset\n"); + return 0; + } + rc = kstrtouint_from_user(buf, count, 10, &trig); + if (rc) + return rc; + + if (trig != 1) { + dev_err(hdev->dev, "Must write 1 to trigger monitor dump\n"); + return -EINVAL; + } + + size = sizeof(struct cpucp_monitor_dump); + + /* Free the previous allocation, if there was any */ + entry->mon_dump_blob_desc.size = 0; + vfree(entry->mon_dump_blob_desc.data); + + entry->mon_dump_blob_desc.data = vmalloc(size); + if (!entry->mon_dump_blob_desc.data) + return -ENOMEM; + + rc = hdev->asic_funcs->get_monitor_dump(hdev, entry->mon_dump_blob_desc.data); + if (rc) { + dev_err(hdev->dev, "Failed to dump monitors\n"); + vfree(entry->mon_dump_blob_desc.data); + entry->mon_dump_blob_desc.data = NULL; + return -EIO; + } + + entry->mon_dump_blob_desc.size = size; return count; } @@ -1235,6 +1279,11 @@ static const struct file_operations hl_dma_size_fops = { .write = hl_dma_size_write }; +static const struct file_operations hl_monitor_dump_fops = { + .owner = THIS_MODULE, + .write = hl_monitor_dump_trigger +}; + static const struct file_operations hl_i2c_data_fops = { .owner = THIS_MODULE, .read = hl_i2c_data_read, @@ -1350,8 +1399,10 @@ void hl_debugfs_add_device(struct hl_device *hdev) if (!dev_entry->entry_arr) return; - dev_entry->blob_desc.size = 0; - dev_entry->blob_desc.data = NULL; + dev_entry->data_dma_blob_desc.size = 0; + dev_entry->data_dma_blob_desc.data = NULL; + dev_entry->mon_dump_blob_desc.size = 0; + dev_entry->mon_dump_blob_desc.data = NULL; INIT_LIST_HEAD(&dev_entry->file_list); INIT_LIST_HEAD(&dev_entry->cb_list); @@ -1470,7 +1521,18 @@ void hl_debugfs_add_device(struct hl_device *hdev) debugfs_create_blob("data_dma", 0400, dev_entry->root, - &dev_entry->blob_desc); + &dev_entry->data_dma_blob_desc); + + debugfs_create_file("monitor_dump_trig", + 0200, + dev_entry->root, + dev_entry, + &hl_monitor_dump_fops); + + debugfs_create_blob("monitor_dump", + 0400, + dev_entry->root, + &dev_entry->mon_dump_blob_desc); debugfs_create_x8("skip_reset_on_timeout", 0644, @@ -1509,7 +1571,8 @@ void hl_debugfs_remove_device(struct hl_device *hdev) mutex_destroy(&entry->file_mutex); - vfree(entry->blob_desc.data); + vfree(entry->data_dma_blob_desc.data); + vfree(entry->mon_dump_blob_desc.data); for (i = 0; i < ARRAY_SIZE(entry->state_dump); ++i) vfree(entry->state_dump[i]); diff --git a/drivers/misc/habanalabs/common/firmware_if.c b/drivers/misc/habanalabs/common/firmware_if.c index 42dce28ca815..7d9d58577bcc 100644 --- a/drivers/misc/habanalabs/common/firmware_if.c +++ b/drivers/misc/habanalabs/common/firmware_if.c @@ -821,6 +821,54 @@ out: return rc; } +int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data) +{ + struct cpucp_monitor_dump *mon_dump_cpu_addr; + dma_addr_t mon_dump_dma_addr; + struct cpucp_packet pkt = {}; + size_t data_size; + __le32 *src_ptr; + u32 *dst_ptr; + u64 result; + int i, rc; + + data_size = sizeof(struct cpucp_monitor_dump); + mon_dump_cpu_addr = hdev->asic_funcs->cpu_accessible_dma_pool_alloc(hdev, data_size, + &mon_dump_dma_addr); + if (!mon_dump_cpu_addr) { + dev_err(hdev->dev, + "Failed to allocate DMA memory for CPU-CP monitor-dump packet\n"); + return -ENOMEM; + } + + memset(mon_dump_cpu_addr, 0, data_size); + + pkt.ctl = cpu_to_le32(CPUCP_PACKET_MONITOR_DUMP_GET << CPUCP_PKT_CTL_OPCODE_SHIFT); + pkt.addr = cpu_to_le64(mon_dump_dma_addr); + pkt.data_max_size = cpu_to_le32(data_size); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_CPUCP_MON_DUMP_TIMEOUT_USEC, &result); + if (rc) { + dev_err(hdev->dev, "Failed to handle CPU-CP monitor-dump packet, error %d\n", rc); + goto out; + } + + /* result contains the actual size */ + src_ptr = (__le32 *) mon_dump_cpu_addr; + dst_ptr = data; + for (i = 0; i < (data_size / sizeof(u32)); i++) { + *dst_ptr = le32_to_cpu(*src_ptr); + src_ptr++; + dst_ptr++; + } + +out: + hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev, data_size, mon_dump_cpu_addr); + + return rc; +} + int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, struct hl_info_pci_counters *counters) { diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 1f7758fed51e..ece83b264b97 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -61,6 +61,7 @@ #define HL_CPUCP_INFO_TIMEOUT_USEC 10000000 /* 10s */ #define HL_CPUCP_EEPROM_TIMEOUT_USEC 10000000 /* 10s */ +#define HL_CPUCP_MON_DUMP_TIMEOUT_USEC 10000000 /* 10s */ #define HL_FW_STATUS_POLL_INTERVAL_USEC 10000 /* 10ms */ @@ -1293,6 +1294,7 @@ struct fw_load_mgr { * @hw_queues_unlock: release H/W queues lock. * @get_pci_id: retrieve PCI ID. * @get_eeprom_data: retrieve EEPROM data from F/W. + * @get_monitor_dump: retrieve monitor registers dump from F/W. * @send_cpu_message: send message to F/W. If the message is timedout, the * driver will eventually reset the device. The timeout can * be determined by the calling function or it can be 0 and @@ -1426,8 +1428,8 @@ struct hl_asic_funcs { void (*hw_queues_lock)(struct hl_device *hdev); void (*hw_queues_unlock)(struct hl_device *hdev); u32 (*get_pci_id)(struct hl_device *hdev); - int (*get_eeprom_data)(struct hl_device *hdev, void *data, - size_t max_size); + int (*get_eeprom_data)(struct hl_device *hdev, void *data, size_t max_size); + int (*get_monitor_dump)(struct hl_device *hdev, void *data); int (*send_cpu_message)(struct hl_device *hdev, u32 *msg, u16 len, u32 timeout, u64 *result); int (*pci_bars_map)(struct hl_device *hdev); @@ -2021,7 +2023,8 @@ struct hl_debugfs_entry { * @userptr_spinlock: protects userptr_list. * @ctx_mem_hash_list: list of available contexts with MMU mappings. * @ctx_mem_hash_spinlock: protects cb_list. - * @blob_desc: descriptor of blob + * @data_dma_blob_desc: data DMA descriptor of blob. + * @mon_dump_blob_desc: monitor dump descriptor of blob. * @state_dump: data of the system states in case of a bad cs. * @state_dump_sem: protects state_dump. * @addr: next address to read/write from/to in read/write32. @@ -2050,7 +2053,8 @@ struct hl_dbg_device_entry { spinlock_t userptr_spinlock; struct list_head ctx_mem_hash_list; spinlock_t ctx_mem_hash_spinlock; - struct debugfs_blob_wrapper blob_desc; + struct debugfs_blob_wrapper data_dma_blob_desc; + struct debugfs_blob_wrapper mon_dump_blob_desc; char *state_dump[HL_STATE_DUMP_HIST_LEN]; struct rw_semaphore state_dump_sem; u64 addr; @@ -3183,6 +3187,7 @@ int hl_fw_cpucp_handshake(struct hl_device *hdev, u32 sts_boot_dev_sts1_reg, u32 boot_err0_reg, u32 boot_err1_reg); int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size); +int hl_fw_get_monitor_dump(struct hl_device *hdev, void *data); int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev, struct hl_info_pci_counters *counters); int hl_fw_cpucp_total_energy_get(struct hl_device *hdev, diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 2101abf1d092..fdcdf47087c8 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -8500,6 +8500,16 @@ static int gaudi_get_eeprom_data(struct hl_device *hdev, void *data, return hl_fw_get_eeprom_data(hdev, data, max_size); } +static int gaudi_get_monitor_dump(struct hl_device *hdev, void *data) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_get_monitor_dump(hdev, data); +} + /* * this function should be used only during initialization and/or after reset, * when there are no active users. @@ -9459,6 +9469,7 @@ static const struct hl_asic_funcs gaudi_funcs = { .hw_queues_unlock = gaudi_hw_queues_unlock, .get_pci_id = gaudi_get_pci_id, .get_eeprom_data = gaudi_get_eeprom_data, + .get_monitor_dump = gaudi_get_monitor_dump, .send_cpu_message = gaudi_send_cpu_message, .pci_bars_map = gaudi_pci_bars_map, .init_iatu = gaudi_init_iatu, diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index bc8431e4b50b..36b3cf57aaae 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -5680,6 +5680,11 @@ static void goya_get_valid_dram_page_orders(struct hl_info_dev_memalloc_page_siz info->page_order_bitmask = 0; } +static int goya_get_monitor_dump(struct hl_device *hdev, void *data) +{ + return -EOPNOTSUPP; +} + static int goya_mmu_prefetch_cache_range(struct hl_device *hdev, u32 flags, u32 asid, u64 va, u64 size) { @@ -5739,6 +5744,7 @@ static const struct hl_asic_funcs goya_funcs = { .hw_queues_unlock = goya_hw_queues_unlock, .get_pci_id = goya_get_pci_id, .get_eeprom_data = goya_get_eeprom_data, + .get_monitor_dump = goya_get_monitor_dump, .send_cpu_message = goya_send_cpu_message, .pci_bars_map = goya_pci_bars_map, .init_iatu = goya_init_iatu, diff --git a/drivers/misc/habanalabs/include/common/cpucp_if.h b/drivers/misc/habanalabs/include/common/cpucp_if.h index 65668dac6a5f..4af5bb695c16 100644 --- a/drivers/misc/habanalabs/include/common/cpucp_if.h +++ b/drivers/misc/habanalabs/include/common/cpucp_if.h @@ -389,6 +389,14 @@ enum pq_init_status { * * CPUCP_PACKET_ENGINE_CORE_ASID_SET - * Packet to perform engine core ASID configuration + * + * CPUCP_PACKET_MONITOR_DUMP_GET - + * Get monitors registers dump from the CpuCP kernel. + * The CPU will put the registers dump in the a buffer allocated by the driver + * which address is passed via the CpuCp packet. In addition, the host's driver + * passes the max size it allows the CpuCP to write to the structure, to prevent + * data corruption in case of mismatched driver/FW versions. + * Relevant only to Gaudi. */ enum cpucp_packet_id { @@ -439,6 +447,11 @@ enum cpucp_packet_id { CPUCP_PACKET_POWER_SET, /* internal */ CPUCP_PACKET_RESERVED, /* not used */ CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */ + CPUCP_PACKET_RESERVED2, /* not used */ + CPUCP_PACKET_RESERVED3, /* not used */ + CPUCP_PACKET_RESERVED4, /* not used */ + CPUCP_PACKET_RESERVED5, /* not used */ + CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */ }; #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 @@ -889,4 +902,29 @@ struct cpucp_hbm_row_replaced_rows_info { struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; }; +/* + * struct dcore_monitor_regs_data - DCORE monitor regs data. + * the structure follows sync manager block layout. relevant only to Gaudi. + * @mon_pay_addrl: array of payload address low bits. + * @mon_pay_addrh: array of payload address high bits. + * @mon_pay_data: array of payload data. + * @mon_arm: array of monitor arm. + * @mon_status: array of monitor status. + */ +struct dcore_monitor_regs_data { + __le32 mon_pay_addrl[512]; + __le32 mon_pay_addrh[512]; + __le32 mon_pay_data[512]; + __le32 mon_arm[512]; + __le32 mon_status[512]; +}; + +/* contains SM data for each SYNC_MNGR (relevant only to Gaudi) */ +struct cpucp_monitor_dump { + struct dcore_monitor_regs_data sync_mngr_w_s; + struct dcore_monitor_regs_data sync_mngr_e_s; + struct dcore_monitor_regs_data sync_mngr_w_n; + struct dcore_monitor_regs_data sync_mngr_e_n; +}; + #endif /* CPUCP_IF_H */ -- cgit v1.2.3 From 0688474eda80ba8a87c38c138aa00b4fea90d8cc Mon Sep 17 00:00:00 2001 From: Dafna Hirschfeld Date: Mon, 11 Apr 2022 17:11:23 +0300 Subject: habanalabs: add device memory scrub ability through debugfs Add the ability to scrub the device memory with a given value. Add file 'dram_mem_scrub_val' to set the value and a file 'dram_mem_scrub' to scrub the dram. This is very important to help during automated tests, when you want the CI system to randomize the memory before training certain DL topologies. Signed-off-by: Dafna Hirschfeld Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/debugfs-driver-habanalabs | 14 +++++++ drivers/misc/habanalabs/common/debugfs.c | 49 ++++++++++++++++++++++ drivers/misc/habanalabs/common/habanalabs.h | 6 +++ drivers/misc/habanalabs/common/habanalabs_drv.c | 8 ++++ drivers/misc/habanalabs/gaudi/gaudi.c | 18 ++++---- drivers/misc/habanalabs/goya/goya.c | 6 +++ 6 files changed, 93 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index 84bf3da2bb27..0f8d20fe343f 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -170,6 +170,20 @@ KernelVersion: 5.1 Contact: ogabbay@kernel.org Description: Sets the state of the third S/W led on the device +What: /sys/kernel/debug/habanalabs/hl/memory_scrub +Date: May 2022 +KernelVersion: 5.19 +Contact: dhirschfeld@habana.ai +Description: Allows the root user to scrub the dram memory. The scrubbing + value can be set using the debugfs file memory_scrub_val. + +What: /sys/kernel/debug/habanalabs/hl/memory_scrub_val +Date: May 2022 +KernelVersion: 5.19 +Contact: dhirschfeld@habana.ai +Description: The value to which the dram will be set to when the user + scrubs the dram using 'memory_scrub' debugfs file + What: /sys/kernel/debug/habanalabs/hl/mmu Date: Jan 2019 KernelVersion: 5.1 diff --git a/drivers/misc/habanalabs/common/debugfs.c b/drivers/misc/habanalabs/common/debugfs.c index a9c4f2d4139d..c6744bfc6da4 100644 --- a/drivers/misc/habanalabs/common/debugfs.c +++ b/drivers/misc/habanalabs/common/debugfs.c @@ -538,6 +538,39 @@ static int engines_show(struct seq_file *s, void *data) return 0; } +static ssize_t hl_memory_scrub(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u64 val = entry->memory_scrub_val; + int rc; + + if (!hl_device_operational(hdev, NULL)) { + dev_warn_ratelimited(hdev->dev, "Can't scrub memory, device is not operational\n"); + return -EIO; + } + + mutex_lock(&hdev->fpriv_list_lock); + if (hdev->is_compute_ctx_active) { + mutex_unlock(&hdev->fpriv_list_lock); + dev_err(hdev->dev, "can't scrub dram, context exist\n"); + return -EBUSY; + } + hdev->is_in_dram_scrub = true; + mutex_unlock(&hdev->fpriv_list_lock); + + rc = hdev->asic_funcs->scrub_device_dram(hdev, val); + + mutex_lock(&hdev->fpriv_list_lock); + hdev->is_in_dram_scrub = false; + mutex_unlock(&hdev->fpriv_list_lock); + + if (rc) + return rc; + return count; +} + static bool hl_is_device_va(struct hl_device *hdev, u64 addr) { struct asic_fixed_properties *prop = &hdev->asic_prop; @@ -1316,6 +1349,11 @@ static ssize_t hl_timeout_locked_write(struct file *f, const char __user *buf, return count; } +static const struct file_operations hl_mem_scrub_fops = { + .owner = THIS_MODULE, + .write = hl_memory_scrub, +}; + static const struct file_operations hl_data32b_fops = { .owner = THIS_MODULE, .read = hl_data_read32, @@ -1475,6 +1513,17 @@ void hl_debugfs_add_device(struct hl_device *hdev) dev_entry->root = debugfs_create_dir(dev_name(hdev->dev), hl_debug_root); + debugfs_create_x64("memory_scrub_val", + 0644, + dev_entry->root, + &dev_entry->memory_scrub_val); + + debugfs_create_file("memory_scrub", + 0200, + dev_entry->root, + dev_entry, + &hl_mem_scrub_fops); + debugfs_create_x64("addr", 0644, dev_entry->root, diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h index 496d61ee07c5..59150caa98a2 100644 --- a/drivers/misc/habanalabs/common/habanalabs.h +++ b/drivers/misc/habanalabs/common/habanalabs.h @@ -1246,6 +1246,7 @@ struct fw_load_mgr { * its implementation is not trivial when the driver * is loaded in simulation mode (not upstreamed). * @scrub_device_mem: Scrub device memory given an address and size + * @scrub_device_dram: Scrub the dram memory of the device. * @get_int_queue_base: get the internal queue base address. * @test_queues: run simple test on all queues for sanity check. * @asic_dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool. @@ -1357,6 +1358,7 @@ struct hl_asic_funcs { void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size, void *cpu_addr, dma_addr_t dma_handle); int (*scrub_device_mem)(struct hl_device *hdev, u64 addr, u64 size); + int (*scrub_device_dram)(struct hl_device *hdev, u64 val); void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id, dma_addr_t *dma_handle, u16 *queue_len); int (*test_queues)(struct hl_device *hdev); @@ -2011,6 +2013,7 @@ struct hl_debugfs_entry { * @addr: next address to read/write from/to in read/write32. * @mmu_addr: next virtual address to translate to physical address in mmu_show. * @userptr_lookup: the target user ptr to look up for on demand. + * @memory_scrub_val: the value to which the dram will be scrubbed to using cb scrub_device_dram * @mmu_asid: ASID to use while translating in mmu_show. * @state_dump_head: index of the latest state dump * @i2c_bus: generic u8 debugfs file for bus value to use in i2c_data_read. @@ -2041,6 +2044,7 @@ struct hl_dbg_device_entry { u64 addr; u64 mmu_addr; u64 userptr_lookup; + u64 memory_scrub_val; u32 mmu_asid; u32 state_dump_head; u8 i2c_bus; @@ -2704,6 +2708,7 @@ struct hl_reset_info { * @id_control: minor of the control device * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit * addresses. + * @is_in_dram_scrub: true if dram scrub operation is on going. * @disabled: is device disabled. * @late_init_done: is late init stage was done during initialization. * @hwmon_initialized: is H/W monitor sensors was initialized. @@ -2834,6 +2839,7 @@ struct hl_device { u16 id; u16 id_control; u16 cpu_pci_msb_addr; + u8 is_in_dram_scrub; u8 disabled; u8 late_init_done; u8 hwmon_initialized; diff --git a/drivers/misc/habanalabs/common/habanalabs_drv.c b/drivers/misc/habanalabs/common/habanalabs_drv.c index 70203433e6cd..1210de39d661 100644 --- a/drivers/misc/habanalabs/common/habanalabs_drv.c +++ b/drivers/misc/habanalabs/common/habanalabs_drv.c @@ -158,6 +158,14 @@ int hl_device_open(struct inode *inode, struct file *filp) goto out_err; } + if (hdev->is_in_dram_scrub) { + dev_dbg_ratelimited(hdev->dev, + "Can't open %s during dram scrub\n", + dev_name(hdev->dev)); + rc = -EAGAIN; + goto out_err; + } + if (hdev->compute_ctx_in_release) { dev_dbg_ratelimited(hdev->dev, "Can't open %s because another user is still releasing it\n", diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c index 8e9bdbac512e..08cd60300b4f 100644 --- a/drivers/misc/habanalabs/gaudi/gaudi.c +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -4740,12 +4740,11 @@ static void gaudi_dma_free_coherent(struct hl_device *hdev, size_t size, dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle); } -static int gaudi_hbm_scrubbing(struct hl_device *hdev) +static int gaudi_scrub_device_dram(struct hl_device *hdev, u64 val) { struct asic_fixed_properties *prop = &hdev->asic_prop; u64 cur_addr = DRAM_BASE_ADDR_USER; - u32 val; - u32 chunk_size; + u32 chunk_size, busy; int rc, dma_id; while (cur_addr < prop->dram_end_address) { @@ -4759,8 +4758,10 @@ static int gaudi_hbm_scrubbing(struct hl_device *hdev) "Doing HBM scrubbing for 0x%09llx - 0x%09llx\n", cur_addr, cur_addr + chunk_size); - WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, 0xdeadbeaf); - WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, 0xdeadbeaf); + WREG32(mmDMA0_CORE_SRC_BASE_LO + dma_offset, + lower_32_bits(val)); + WREG32(mmDMA0_CORE_SRC_BASE_HI + dma_offset, + upper_32_bits(val)); WREG32(mmDMA0_CORE_DST_BASE_LO + dma_offset, lower_32_bits(cur_addr)); WREG32(mmDMA0_CORE_DST_BASE_HI + dma_offset, @@ -4783,8 +4784,8 @@ static int gaudi_hbm_scrubbing(struct hl_device *hdev) rc = hl_poll_timeout( hdev, mmDMA0_CORE_STS0 + dma_offset, - val, - ((val & DMA0_CORE_STS0_BUSY_MASK) == 0), + busy, + ((busy & DMA0_CORE_STS0_BUSY_MASK) == 0), 1000, HBM_SCRUBBING_TIMEOUT_US); @@ -4838,7 +4839,7 @@ static int gaudi_scrub_device_mem(struct hl_device *hdev, u64 addr, u64 size) } /* Scrub HBM using all DMA channels in parallel */ - rc = gaudi_hbm_scrubbing(hdev); + rc = gaudi_scrub_device_dram(hdev, 0xdeadbeaf); if (rc) dev_err(hdev->dev, "Failed to clear HBM in mem scrub all\n"); @@ -9208,6 +9209,7 @@ static const struct hl_asic_funcs gaudi_funcs = { .asic_dma_alloc_coherent = gaudi_dma_alloc_coherent, .asic_dma_free_coherent = gaudi_dma_free_coherent, .scrub_device_mem = gaudi_scrub_device_mem, + .scrub_device_dram = gaudi_scrub_device_dram, .get_int_queue_base = gaudi_get_int_queue_base, .test_queues = gaudi_test_queues, .asic_dma_pool_zalloc = gaudi_dma_pool_zalloc, diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index f8fb6dc04269..f2d4362f6a46 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -5434,6 +5434,11 @@ static int goya_mmu_prefetch_cache_range(struct hl_device *hdev, u32 flags, u32 return 0; } +static int goya_scrub_device_dram(struct hl_device *hdev, u64 val) +{ + return -EOPNOTSUPP; +} + static const struct hl_asic_funcs goya_funcs = { .early_init = goya_early_init, .early_fini = goya_early_fini, @@ -5452,6 +5457,7 @@ static const struct hl_asic_funcs goya_funcs = { .asic_dma_alloc_coherent = goya_dma_alloc_coherent, .asic_dma_free_coherent = goya_dma_free_coherent, .scrub_device_mem = goya_scrub_device_mem, + .scrub_device_dram = goya_scrub_device_dram, .get_int_queue_base = goya_get_int_queue_base, .test_queues = goya_test_queues, .asic_dma_pool_zalloc = goya_dma_pool_zalloc, -- cgit v1.2.3