From 38eceb3a441232150020754553ba161b1224fe09 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 19 Sep 2016 13:09:03 +0530 Subject: Documentation: regulator: tps65218: Update examples This updates the Device Tree according to the preferred way of parsing the nodes using the regulator framework. Signed-off-by: Keerthy Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/regulator/tps65218.txt | 87 ++++++++++++++++++---- 1 file changed, 71 insertions(+), 16 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/regulator/tps65218.txt b/Documentation/devicetree/bindings/regulator/tps65218.txt index fccc1d24af58..02f0e9bbfbf8 100644 --- a/Documentation/devicetree/bindings/regulator/tps65218.txt +++ b/Documentation/devicetree/bindings/regulator/tps65218.txt @@ -1,23 +1,78 @@ TPS65218 family of regulators Required properties: -For tps65218 regulators/LDOs -- compatible: - - "ti,tps65218-dcdc1" for DCDC1 - - "ti,tps65218-dcdc2" for DCDC2 - - "ti,tps65218-dcdc3" for DCDC3 - - "ti,tps65218-dcdc4" for DCDC4 - - "ti,tps65218-dcdc5" for DCDC5 - - "ti,tps65218-dcdc6" for DCDC6 - - "ti,tps65218-ldo1" for LDO1 - -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt +- compatible: "ti,tps65218" +- reg: I2C slave address + +- List of regulators provided by this controller, must be named + after their hardware counterparts: dcdc[1-6] and ldo1 +- This is the list of child nodes that specify the regulator + initialization data for defined regulators. Not all regulators for the given + device need to be present. The definition for each of these nodes is defined + using the standard binding for regulators found at ./regulator.txt. + + The valid names for regulators are: + tps65217: regulator-dcdc1, regulator-dcdc2, regulator-dcdc3, regulator-dcdc4, + regulator-dcdc5, regulator-dcdc6, regulator-ldo1, regulator-ls3. + Each regulator is defined using the standard binding for regulators. Example: +tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc6: regulator-dcdc6 { + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: regulator-ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; - xyz: regulator@0 { - compatible = "ti,tps65218-dcdc1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; + ls3: regulator-ls3 { + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <1000000>; }; +}; -- cgit v1.2.3 From 7fff7d9b15449c317fcc5dcd82ebb17dd0ae53e1 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Thu, 2 Jun 2016 12:52:21 -0500 Subject: dt-bindings: mfd: Add Altera Arria10 System Resource Chip bindings The Altera Arria10 Devkit System Resource chip is a Multi-Function Device with a GPIO expander. This patch adds documentation for the Altera A10-SR DT bindings. Signed-off-by: Thor Thayer Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/altera-a10sr.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt new file mode 100644 index 000000000000..ea151f295ad7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt @@ -0,0 +1,46 @@ +* Altera Arria10 Development Kit System Resource Chip + +Required parent device properties: +- compatible : "altr,a10sr" +- spi-max-frequency : Maximum SPI frequency. +- reg : The SPI Chip Select address for the Arria10 + System Resource chip +- interrupt-parent : The parent interrupt controller. +- interrupts : The interrupt line the device is connected to. +- interrupt-controller : Marks the device node as an interrupt controller. +- #interrupt-cells : The number of cells to describe an IRQ, should be 2. + The first cell is the IRQ number. + The second cell is the flags, encoded as trigger + masks from ../interrupt-controller/interrupts.txt. + +The A10SR consists of these sub-devices: + +Device Description +------ ---------- +a10sr_gpio GPIO Controller + +Arria10 GPIO +Required Properties: +- compatible : Should be "altr,a10sr-gpio" +- gpio-controller : Marks the device node as a GPIO Controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. + See ../gpio/gpio.txt for more information. + +Example: + + resource-manager@0 { + compatible = "altr,a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + interrupt-parent = <&portb>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + a10sr_gpio: gpio-controller { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; -- cgit v1.2.3 From c5e589a171728c9f5c587f9254ec6b343153c2ce Mon Sep 17 00:00:00 2001 From: Pierre-Hugues Husson Date: Sat, 5 Nov 2016 17:19:24 +0100 Subject: mfd: rn5t618: Add Ricoh RC5T619 PMIC support The Ricoh RN5T567 is from the same family as the Ricoh RN5T618 is, the differences are: + DCDC4/DCDC5 + LDO7-10 + Slightly different output voltage/currents + 32kHz Output + RTC + USB Charger detection Signed-off-by: Pierre-Hugues Husson Acked-by: Rob Herring Signed-off-by: Lee Jones --- Documentation/devicetree/bindings/mfd/rn5t618.txt | 16 ++++++++++------ drivers/mfd/Kconfig | 3 ++- drivers/mfd/rn5t618.c | 1 + include/linux/mfd/rn5t618.h | 9 +++++++++ 4 files changed, 22 insertions(+), 7 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/rn5t618.txt b/Documentation/devicetree/bindings/mfd/rn5t618.txt index 9e6770b105c9..65c23263cc54 100644 --- a/Documentation/devicetree/bindings/mfd/rn5t618.txt +++ b/Documentation/devicetree/bindings/mfd/rn5t618.txt @@ -1,21 +1,25 @@ * Ricoh RN5T567/RN5T618 PMIC -Ricoh RN5T567/RN5T618 is a power management IC family which integrates -3 to 4 step-down DCDC converters, 7 low-dropout regulators, GPIOs and -a watchdog timer. The RN5T618 provides additionally a Li-ion battery -charger, fuel gauge and an ADC. It can be controlled through an I2C -interface. +Ricoh RN5T567/RN5T618/RC5T619 is a power management IC family which +integrates 3 to 5 step-down DCDC converters, 7 to 10 low-dropout regulators, +GPIOs, and a watchdog timer. It can be controlled through an I2C interface. +The RN5T618/RC5T619 provides additionally a Li-ion battery charger, +fuel gauge, and an ADC. +The RC5T619 additionnally includes USB charger detection and an RTC. Required properties: - compatible: must be one of "ricoh,rn5t567" "ricoh,rn5t618" + "ricoh,rc5t619" - reg: the I2C slave address of the device Sub-nodes: - regulators: the node is required if the regulator functionality is needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, DCDC4 - (RN5T567), LDO1, LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2. + (RN5T567/RC5T619), LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, + LDO9, LDO10, LDORTC1 and LDORTC2. + LDO7-10 are specific to RC5T619. The common bindings for each individual regulator can be found in: Documentation/devicetree/bindings/regulator/regulator.txt diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 0fde51ee633d..4ce3b6f11830 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -894,7 +894,8 @@ config MFD_RN5T618 select MFD_CORE select REGMAP_I2C help - Say yes here to add support for the Ricoh RN5T567 or R5T618 PMIC. + Say yes here to add support for the Ricoh RN5T567, + RN5T618, RC5T619 PMIC. This driver provides common support for accessing the device, additional drivers must be enabled in order to use the functionality of the device. diff --git a/drivers/mfd/rn5t618.c b/drivers/mfd/rn5t618.c index ee94080e1cbb..8131d1975745 100644 --- a/drivers/mfd/rn5t618.c +++ b/drivers/mfd/rn5t618.c @@ -87,6 +87,7 @@ static int rn5t618_restart(struct notifier_block *this, static const struct of_device_id rn5t618_of_match[] = { { .compatible = "ricoh,rn5t567", .data = (void *)RN5T567 }, { .compatible = "ricoh,rn5t618", .data = (void *)RN5T618 }, + { .compatible = "ricoh,rc5t619", .data = (void *)RC5T619 }, { } }; MODULE_DEVICE_TABLE(of, rn5t618_of_match); diff --git a/include/linux/mfd/rn5t618.h b/include/linux/mfd/rn5t618.h index cadc6543909d..e5a6cdeb77db 100644 --- a/include/linux/mfd/rn5t618.h +++ b/include/linux/mfd/rn5t618.h @@ -58,10 +58,13 @@ #define RN5T618_DC3CTL2 0x31 #define RN5T618_DC4CTL 0x32 #define RN5T618_DC4CTL2 0x33 +#define RN5T618_DC5CTL 0x34 +#define RN5T618_DC5CTL2 0x35 #define RN5T618_DC1DAC 0x36 #define RN5T618_DC2DAC 0x37 #define RN5T618_DC3DAC 0x38 #define RN5T618_DC4DAC 0x39 +#define RN5T618_DC5DAC 0x3a #define RN5T618_DC1DAC_SLP 0x3b #define RN5T618_DC2DAC_SLP 0x3c #define RN5T618_DC3DAC_SLP 0x3d @@ -77,6 +80,11 @@ #define RN5T618_LDO3DAC 0x4e #define RN5T618_LDO4DAC 0x4f #define RN5T618_LDO5DAC 0x50 +#define RN5T618_LDO6DAC 0x51 +#define RN5T618_LDO7DAC 0x52 +#define RN5T618_LDO8DAC 0x53 +#define RN5T618_LDO9DAC 0x54 +#define RN5T618_LDO10DAC 0x55 #define RN5T618_LDORTCDAC 0x56 #define RN5T618_LDORTC2DAC 0x57 #define RN5T618_LDO1DAC_SLP 0x58 @@ -231,6 +239,7 @@ enum { enum { RN5T567 = 0, RN5T618, + RC5T619, }; struct rn5t618 { -- cgit v1.2.3 From 953f432b3d0a171276455e40fdeac7225d36d678 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Tue, 15 Nov 2016 12:01:51 +0000 Subject: mfd: pm8xxx: add support to pm8821 This patch adds support to PM8821 PMIC and interrupt support. PM8821 is companion device that supplements primary PMIC PM8921 IC. Signed-off-by: Srinivas Kandagatla Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/qcom-pm8xxx.txt | 1 + drivers/mfd/qcom-pm8xxx.c | 231 ++++++++++++++++++++- 2 files changed, 222 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt index 37a088f9a648..9e5eba4a4f0d 100644 --- a/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt +++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt @@ -10,6 +10,7 @@ voltages and other various functionality to Qualcomm SoCs. Value type: Definition: must be one of: "qcom,pm8058" + "qcom,pm8821" "qcom,pm8921" - #address-cells: diff --git a/drivers/mfd/qcom-pm8xxx.c b/drivers/mfd/qcom-pm8xxx.c index 7f9620ec61e8..f08758f6b418 100644 --- a/drivers/mfd/qcom-pm8xxx.c +++ b/drivers/mfd/qcom-pm8xxx.c @@ -39,6 +39,20 @@ #define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7) #define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8) +#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100 +#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30) +#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0) +#define PM8821_SSBI_REG(m, b, offset) \ + ((m == 0) ? \ + (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \ + (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset)) +#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0) +#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01) +#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08) +#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f) + +#define PM8821_BLOCKS_PER_MASTER 7 + #define PM_IRQF_LVL_SEL 0x01 /* level select */ #define PM_IRQF_MASK_FE 0x02 /* mask falling edge */ #define PM_IRQF_MASK_RE 0x04 /* mask rising edge */ @@ -54,6 +68,7 @@ #define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */ #define PM8XXX_NR_IRQS 256 +#define PM8821_NR_IRQS 112 struct pm_irq_chip { struct regmap *regmap; @@ -65,6 +80,12 @@ struct pm_irq_chip { u8 config[0]; }; +struct pm_irq_data { + int num_irqs; + const struct irq_domain_ops *irq_domain_ops; + void (*irq_handler)(struct irq_desc *desc); +}; + static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int *ip) { @@ -182,6 +203,78 @@ static void pm8xxx_irq_handler(struct irq_desc *desc) chained_irq_exit(irq_chip, desc); } +static void pm8821_irq_block_handler(struct pm_irq_chip *chip, + int master, int block) +{ + int pmirq, irq, i, ret; + unsigned int bits; + + ret = regmap_read(chip->regmap, + PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits); + if (ret) { + pr_err("Reading block %d failed ret=%d", block, ret); + return; + } + + /* Convert block offset to global block number */ + block += (master * PM8821_BLOCKS_PER_MASTER) - 1; + + /* Check IRQ bits */ + for (i = 0; i < 8; i++) { + if (bits & BIT(i)) { + pmirq = block * 8 + i; + irq = irq_find_mapping(chip->irqdomain, pmirq); + generic_handle_irq(irq); + } + } +} + +static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip, + int master, u8 master_val) +{ + int block; + + for (block = 1; block < 8; block++) + if (master_val & BIT(block)) + pm8821_irq_block_handler(chip, master, block); +} + +static void pm8821_irq_handler(struct irq_desc *desc) +{ + struct pm_irq_chip *chip = irq_desc_get_handler_data(desc); + struct irq_chip *irq_chip = irq_desc_get_chip(desc); + unsigned int master; + int ret; + + chained_irq_enter(irq_chip, desc); + ret = regmap_read(chip->regmap, + PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master); + if (ret) { + pr_err("Failed to read master 0 ret=%d\n", ret); + goto done; + } + + /* bits 1 through 7 marks the first 7 blocks in master 0 */ + if (master & GENMASK(7, 1)) + pm8821_irq_master_handler(chip, 0, master); + + /* bit 0 marks if master 1 contains any bits */ + if (!(master & BIT(0))) + goto done; + + ret = regmap_read(chip->regmap, + PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master); + if (ret) { + pr_err("Failed to read master 1 ret=%d\n", ret); + goto done; + } + + pm8821_irq_master_handler(chip, 1, master); + +done: + chained_irq_exit(irq_chip, desc); +} + static void pm8xxx_irq_mask_ack(struct irq_data *d) { struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); @@ -299,6 +392,104 @@ static const struct irq_domain_ops pm8xxx_irq_domain_ops = { .map = pm8xxx_irq_domain_map, }; +static void pm8821_irq_mask_ack(struct irq_data *d) +{ + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); + unsigned int pmirq = irqd_to_hwirq(d); + u8 block, master; + int irq_bit, rc; + + block = pmirq / 8; + master = block / PM8821_BLOCKS_PER_MASTER; + irq_bit = pmirq % 8; + block %= PM8821_BLOCKS_PER_MASTER; + + rc = regmap_update_bits(chip->regmap, + PM8821_SSBI_ADDR_IRQ_MASK(master, block), + BIT(irq_bit), BIT(irq_bit)); + if (rc) { + pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc); + return; + } + + rc = regmap_update_bits(chip->regmap, + PM8821_SSBI_ADDR_IRQ_CLEAR(master, block), + BIT(irq_bit), BIT(irq_bit)); + if (rc) + pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc); +} + +static void pm8821_irq_unmask(struct irq_data *d) +{ + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); + unsigned int pmirq = irqd_to_hwirq(d); + int irq_bit, rc; + u8 block, master; + + block = pmirq / 8; + master = block / PM8821_BLOCKS_PER_MASTER; + irq_bit = pmirq % 8; + block %= PM8821_BLOCKS_PER_MASTER; + + rc = regmap_update_bits(chip->regmap, + PM8821_SSBI_ADDR_IRQ_MASK(master, block), + BIT(irq_bit), ~BIT(irq_bit)); + if (rc) + pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc); + +} + +static int pm8821_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool *state) +{ + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d); + int rc, pmirq = irqd_to_hwirq(d); + u8 block, irq_bit, master; + unsigned int bits; + + block = pmirq / 8; + master = block / PM8821_BLOCKS_PER_MASTER; + irq_bit = pmirq % 8; + block %= PM8821_BLOCKS_PER_MASTER; + + rc = regmap_read(chip->regmap, + PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits); + if (rc) { + pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc); + return rc; + } + + *state = !!(bits & BIT(irq_bit)); + + return rc; +} + +static struct irq_chip pm8821_irq_chip = { + .name = "pm8821", + .irq_mask_ack = pm8821_irq_mask_ack, + .irq_unmask = pm8821_irq_unmask, + .irq_get_irqchip_state = pm8821_irq_get_irqchip_state, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE, +}; + +static int pm8821_irq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct pm_irq_chip *chip = d->host_data; + + irq_set_chip_and_handler(irq, &pm8821_irq_chip, handle_level_irq); + irq_set_chip_data(irq, chip); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops pm8821_irq_domain_ops = { + .xlate = irq_domain_xlate_twocell, + .map = pm8821_irq_domain_map, +}; + static const struct regmap_config ssbi_regmap_config = { .reg_bits = 16, .val_bits = 8, @@ -308,22 +499,41 @@ static const struct regmap_config ssbi_regmap_config = { .reg_write = ssbi_reg_write }; +static const struct pm_irq_data pm8xxx_data = { + .num_irqs = PM8XXX_NR_IRQS, + .irq_domain_ops = &pm8xxx_irq_domain_ops, + .irq_handler = pm8xxx_irq_handler, +}; + +static const struct pm_irq_data pm8821_data = { + .num_irqs = PM8821_NR_IRQS, + .irq_domain_ops = &pm8821_irq_domain_ops, + .irq_handler = pm8821_irq_handler, +}; + static const struct of_device_id pm8xxx_id_table[] = { - { .compatible = "qcom,pm8018", }, - { .compatible = "qcom,pm8058", }, - { .compatible = "qcom,pm8921", }, + { .compatible = "qcom,pm8018", .data = &pm8xxx_data}, + { .compatible = "qcom,pm8058", .data = &pm8xxx_data}, + { .compatible = "qcom,pm8821", .data = &pm8821_data}, + { .compatible = "qcom,pm8921", .data = &pm8xxx_data}, { } }; MODULE_DEVICE_TABLE(of, pm8xxx_id_table); static int pm8xxx_probe(struct platform_device *pdev) { + const struct pm_irq_data *data; struct regmap *regmap; int irq, rc; unsigned int val; u32 rev; struct pm_irq_chip *chip; - unsigned int nirqs = PM8XXX_NR_IRQS; + + data = of_device_get_match_data(&pdev->dev); + if (!data) { + dev_err(&pdev->dev, "No matching driver data found\n"); + return -EINVAL; + } irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -354,25 +564,26 @@ static int pm8xxx_probe(struct platform_device *pdev) rev |= val << BITS_PER_BYTE; chip = devm_kzalloc(&pdev->dev, sizeof(*chip) + - sizeof(chip->config[0]) * nirqs, - GFP_KERNEL); + sizeof(chip->config[0]) * data->num_irqs, + GFP_KERNEL); if (!chip) return -ENOMEM; platform_set_drvdata(pdev, chip); chip->regmap = regmap; - chip->num_irqs = nirqs; + chip->num_irqs = data->num_irqs; chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8); chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8); spin_lock_init(&chip->pm_irq_lock); - chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs, - &pm8xxx_irq_domain_ops, + chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, + data->num_irqs, + data->irq_domain_ops, chip); if (!chip->irqdomain) return -ENODEV; - irq_set_chained_handler_and_data(irq, pm8xxx_irq_handler, chip); + irq_set_chained_handler_and_data(irq, data->irq_handler, chip); irq_set_irq_wake(irq, 1); rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); -- cgit v1.2.3