From f517232c5a95408e43b40aa9337e6b742beaa9da Mon Sep 17 00:00:00 2001 From: Aleksandr Aleksandrov Date: Mon, 15 Oct 2018 14:49:49 +0300 Subject: dt-bindings: vendor-prefix: new vendor - Emlid Add vendor Emlid Ltd to vendor-prefixes.txt Acked-by: Rob Herring Signed-off-by: Aleksandr Aleksandrov Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..1b531c730c87 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -113,6 +113,7 @@ edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. embest Shenzhen Embest Technology Co., Ltd. +emlid Emlid, Ltd. emmicro EM Microelectronic emtrion emtrion GmbH endless Endless Mobile, Inc. -- cgit v1.2.3 From 186172f465c29ee6b617af961723a3ce5029a9c8 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 3 Nov 2018 20:32:36 +0800 Subject: dt-binding: dwmac-sun8i: add H6 compatible string (w/ A64 fallback) The Allwinner H6 SoC features a Ethernet MAC that is similar to the one in A64. Add a compatible string for it with A64 fallback compatible string, in this case the A64 driver can be used. The "internal" PHY is not internal from the perspective of the H6 main die, instead it's on the co-packaged AC200 chip, and connected to the main die with RMII at the in-package Port A PIO bank. So from the SoC driver side it needs no special treatment. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 5bb3a18cc38d..54c66d0611cb 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -10,6 +10,7 @@ Required properties: "allwinner,sun8i-r40-gmac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" + "allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device - interrupt-names: must be "macirq" -- cgit v1.2.3 From 505a2fd80b4dcd9e89bcf426ba4314ea339911e8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 4 Jun 2018 11:36:13 +0200 Subject: arm64: dts: rockchip: add Gru Scarlet devicetrees Gru-Scarlet is a tablet device using ChomeOS, dual-dsi display and Wacom touchscreen with stylus. There exist two variants in the market using different displays that are differentiated via their sku-id. The bootloader on them also determines the correct devicetree to load via the sku-id. So add a common scarlet dtsi and two minimal board devicetrees for the two display variants. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 34 ++ arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3399-gru-scarlet-inx.dts | 33 ++ .../boot/dts/rockchip/rk3399-gru-scarlet-kd.dts | 33 ++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 594 +++++++++++++++++++++ 5 files changed, 696 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 0cc71236d639..7ce7382fedd8 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -152,6 +152,40 @@ Rockchip platforms device tree bindings - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", "google,veyron", "rockchip,rk3288"; +- Google Scarlet - with display from Kingdisplay + Required root node properties: + - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", + "google,scarlet-rev14-sku7", "google,scarlet-rev14", + "google,scarlet-rev13-sku7", "google,scarlet-rev13", + "google,scarlet-rev12-sku7", "google,scarlet-rev12", + "google,scarlet-rev11-sku7", "google,scarlet-rev11", + "google,scarlet-rev10-sku7", "google,scarlet-rev10", + "google,scarlet-rev9-sku7", "google,scarlet-rev9", + "google,scarlet-rev8-sku7", "google,scarlet-rev8", + "google,scarlet-rev7-sku7", "google,scarlet-rev7", + "google,scarlet-rev6-sku7", "google,scarlet-rev6", + "google,scarlet-rev5-sku7", "google,scarlet-rev5", + "google,scarlet-rev4-sku7", "google,scarlet-rev4", + "google,scarlet-rev3-sku7", "google,scarlet-rev3", + "google,scarlet", "google,gru", "rockchip,rk3399"; + +- Google Scarlet - with display from Innolux + Required root node properties: + - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; + + - Google Speedy (Asus C201 Chromebook): Required root node properties: - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 49042c477870..de0c406c20cc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -14,6 +14,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts new file mode 100644 index 000000000000..2d721a974790 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Scarlet Rev4+ (SKU-6/Innolux) board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; + +#include "rk3399-gru-scarlet.dtsi" + +/ { + model = "Google Scarlet"; + compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; +}; + +&mipi_panel { + compatible = "innolux,p097pfg"; + avdd-supply = <&ppvarp_lcd>; + avee-supply = <&ppvarn_lcd>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts new file mode 100644 index 000000000000..bd7592217270 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Scarlet Rev3+ (SKU-7/Kingdisplay) board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; + +#include "rk3399-gru-scarlet.dtsi" + +/ { + model = "Google Scarlet"; + compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", + "google,scarlet-rev14-sku7", "google,scarlet-rev14", + "google,scarlet-rev13-sku7", "google,scarlet-rev13", + "google,scarlet-rev12-sku7", "google,scarlet-rev12", + "google,scarlet-rev11-sku7", "google,scarlet-rev11", + "google,scarlet-rev10-sku7", "google,scarlet-rev10", + "google,scarlet-rev9-sku7", "google,scarlet-rev9", + "google,scarlet-rev8-sku7", "google,scarlet-rev8", + "google,scarlet-rev7-sku7", "google,scarlet-rev7", + "google,scarlet-rev6-sku7", "google,scarlet-rev6", + "google,scarlet-rev5-sku7", "google,scarlet-rev5", + "google,scarlet-rev4-sku7", "google,scarlet-rev4", + "google,scarlet-rev3-sku7", "google,scarlet-rev3", + "google,scarlet", "google,gru", "rockchip,rk3399"; +}; + +&mipi_panel { + compatible = "kingdisplay,kd097d04"; + power-supply = <&pp3300_s0>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi new file mode 100644 index 000000000000..fc50b3ef758c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-scarlet board device tree source + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/{ + /* Power tree */ + + /* ppvar_sys children, sorted by name */ + pp1250_s3: pp1250-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp1250_s3"; + + /* EC turns on w/ pp1250_s3_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1250_cam: pp1250-dvdd { + compatible = "regulator-fixed"; + regulator-name = "pp1250_dvdd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1250_cam_en>; + + enable-active-high; + gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + + /* 740us delay from gpio output high to pp1250 stable, + * rounding up to 1ms for safety. + */ + startup-delay-us = <1000>; + vin-supply = <&pp1250_s3>; + }; + + pp900_s0: pp900-s0 { + compatible = "regulator-fixed"; + regulator-name = "pp900_s0"; + + /* EC turns on w/ pp900_s0_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvarn_lcd: ppvarn-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarn_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarn_lcd_en>; + + enable-active-high; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + vin-supply = <&ppvar_sys>; + }; + + ppvarp_lcd: ppvarp-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarp_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarp_lcd_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + vin-supply = <&ppvar_sys>; + }; + + /* pp1800 children, sorted by name */ + pp900_s3: pp900-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp900_s3"; + + /* EC turns on w/ pp900_s3_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&pp1800>; + }; + + /* EC turns on pp1800_s3_en */ + pp1800_s3: pp1800 { + }; + + /* pp3300 children, sorted by name */ + pp2800_cam: pp2800-avdd { + compatible = "regulator-fixed"; + regulator-name = "pp2800_avdd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp2800_cam_en>; + + enable-active-high; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + vin-supply = <&pp3300>; + }; + + /* EC turns on pp3300_s0_en */ + pp3300_s0: pp3300 { + }; + + /* EC turns on pp3300_s3_en */ + pp3300_s3: pp3300 { + }; + + /* + * See b/66922012 + * + * This is a hack to make sure the Bluetooth part of the QCA6174A + * is reset at boot by toggling BT_EN. At boot BT_EN is first set + * to low when the bt_3v3 regulator is registered (in disabled + * state). The fake regulator is configured as a supply of the + * wlan_3v3 regulator below. When wlan_3v3 is enabled early in + * the boot process it also enables its supply regulator bt_3v3, + * which changes BT_EN to high. + */ + bt_3v3: bt-3v3 { + compatible = "regulator-fixed"; + regulator-name = "bt_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_1v8_l>; + + enable-active-high; + gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_s3>; + }; + + wlan_3v3: wlan-3v3 { + compatible = "regulator-fixed"; + regulator-name = "wlan_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pd_1v8_l>; + + /* + * The WL_EN pin is driven low when the regulator is + * registered, and transitions to high when the PCIe bus + * is powered up. + */ + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. + * TODO (b/64444991): how long to assert PD#? + */ + regulator-enable-ramp-delay = <10000>; + /* See bt_3v3 hack above */ + vin-supply = <&bt_3v3>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm1 0 1000000 0>; + pwm-delay-us = <10000>; + }; + + dmic: dmic { + compatible = "dmic-codec"; + dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dmic_en>; + wakeup-delay-ms = <250>; + }; +}; + +/* pp900_s0 aliases */ +pp900_ddrpll_ap: &pp900_s0 { +}; +pp900_pcie: &pp900_s0 { +}; +pp900_usb: &pp900_s0 { +}; + +/* pp900_s3 aliases */ +pp900_emmcpll: &pp900_s3 { +}; + +/* EC turns on; alias for pp1800_s0 */ +pp1800_pcie: &pp1800_s0 { +}; + +/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ +&ppvar_bigcpu { + ctrl-voltage-range = <800074 1299226>; + regulator-min-microvolt = <800074>; + regulator-max-microvolt = <1299226>; +}; + +&ppvar_bigcpu_pwm { + /* On scarlet ppvar big cpu use pwm3 */ + pwms = <&pwm3 0 3337 0>; + regulator-min-microvolt = <800074>; + regulator-max-microvolt = <1299226>; +}; + +&ppvar_litcpu { + ctrl-voltage-range = <802122 1199620>; + regulator-min-microvolt = <802122>; + regulator-max-microvolt = <1199620>; +}; + +&ppvar_litcpu_pwm { + regulator-min-microvolt = <802122>; + regulator-max-microvolt = <1199620>; +}; + +&ppvar_gpu { + ctrl-voltage-range = <799600 1099600>; + regulator-min-microvolt = <799600>; + regulator-max-microvolt = <1099600>; +}; + +&ppvar_gpu_pwm { + regulator-min-microvolt = <799600>; + regulator-max-microvolt = <1099600>; +}; + +&ppvar_sd_card_io { + states = <1800000 0x0 3300000 0x1>; + regulator-max-microvolt = <3300000>; +}; + +&pp3000_sd_slot { + vin-supply = <&pp3300>; +}; + +ap_i2c_dig: &i2c2 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + digitizer: digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x9>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pen_int_odl &pen_reset_l>; + }; +}; + +&ap_i2c_ts { + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l &touch_reset_l>; + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; +}; + +camera: &i2c7 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* 24M mclk is shared between world and user cameras */ + pinctrl-0 = <&i2c7_xfer &test_clkout1>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>; + phys = <&tcphy0_dp>; +}; + +&cpu_alert0 { + temperature = <66000>; +}; + +&cpu_alert1 { + temperature = <71000>; +}; + +&cros_ec { + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +}; + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>, + <&cru ACLK_HDCP>; + assigned-clock-rates = + <600000000>, <1600000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, <800000000>, + <100000000>, <50000000>, + <400000000>, + <200000000>, + <200000000>, + <400000000>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>, <&pen_eject_odl>; + + pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; +}; + +&i2c_tunnel { + google,remote-bus = <0>; +}; + +&io_domains { + bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ + audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ + gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ +}; + +&max98357a { + sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +}; + +&mipi_dsi { + status = "okay"; + clock-master; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + mipi_panel: panel@0 { + /* 2 different panels are used, compatibles are in dts files */ + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&display_rst_l>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + + port@1 { + reg = <1>; + + mipi1_in_panel: endpoint@1 { + remote-endpoint = <&mipi1_out_panel>; + }; + }; + }; + }; +}; + +&mipi_dsi1 { + status = "okay"; + + ports { + mipi1_out: port@1 { + reg = <1>; + + mipi1_out_panel: endpoint { + remote-endpoint = <&mipi1_in_panel>; + }; + }; + }; +}; + +&pcie0 { + ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + + /* PERST# asserted in S3 */ + pcie-reset-suspend = <1>; + + vpcie3v3-supply = <&wlan_3v3>; + vpcie1v8-supply = <&pp1800_pcie>; +}; + +&sdmmc { + cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +}; + +&sound { + rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; +}; + +&spi2 { + status = "okay"; +}; + +&wake_on_bt { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +}; + +/* PINCTRL OVERRIDES */ +&ec_ap_int_l { + rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&ap_fw_wp { + rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&bl_en { + rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&bt_host_wake_l { + rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&ec_ap_int_l { + rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&headset_int_l { + rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&i2s0_8ch_bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 25 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 26 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 27 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 31 RK_FUNC_1 &pcfg_pull_none_6ma>, + <4 0 RK_FUNC_1 &pcfg_pull_none_6ma>; +}; + +/* there is no external pull up, so need to set this pin pull up */ +&sdmmc_cd_gpio { + rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&sd_pwr_1800_sel { + rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&sdmode_en { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&touch_reset_l { + rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&touch_int_l { + rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&pinctrl { + pinctrl-0 = < + &ap_pwroff /* AP will auto-assert this when in S3 */ + &clk_32k /* This pin is always 32k on gru boards */ + &wlan_rf_kill_1v8_l + >; + + pcfg_pull_none_6ma: pcfg-pull-none-6ma { + bias-disable; + drive-strength = <6>; + }; + + camera { + pp1250_cam_en: pp1250-dvdd { + rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pp2800_cam_en: pp2800-avdd { + rockchip,pins = <2 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ucam_rst: ucam_rst { + rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wcam_rst: wcam_rst { + rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + digitizer { + pen_int_odl: pen-int-odl { + rockchip,pins = <1 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pen_reset_l: pen-reset-l { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + discrete-regulators { + display_rst_l: display-rst-l { + rockchip,pins = <4 25 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ppvarp_lcd_en: ppvarp-lcd-en { + rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ppvarn_lcd_en: ppvarn-lcd-en { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dmic { + dmic_en: dmic-en { + rockchip,pins = <4 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + pen_eject_odl: pen-eject-odl { + rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + tpm { + h1_int_od_l: h1-int-od-l { + rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&wifi { + bt_en_1v8_l: bt-en-1v8-l { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_pd_1v8_l: wlan-pd-1v8-l { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* Default pull-up, but just to be clear */ + wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_perst_l: wifi-perst-l { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_up>; + }; +}; -- cgit v1.2.3 From a2aabe5f3c57fabefe369b636db3df86874218be Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 17 Sep 2018 09:22:22 +0100 Subject: dt-bindings: soc: Document "brcm,bcm2836-vchiq" "brcm,bcm2836-vchiq" should be used on BCM2836 and BCM2837 to ensure correct operation. Signed-off-by: Phil Elwell Acked-by: Stefan Wahren Signed-off-by: Stefan Wahren --- Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt index 8dd7b3a7de65..f331316183f6 100644 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt @@ -2,7 +2,8 @@ Broadcom VCHIQ firmware services Required properties: -- compatible: Should be "brcm,bcm2835-vchiq" +- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise + "brcm,bcm2836-vchiq". - reg: Physical base address and length of the doorbell register pair - interrupts: The interrupt number See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt -- cgit v1.2.3 From ad348c3f55962c86adf9c8cb3712825fb7db5336 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2018 15:11:46 +0100 Subject: dt-bindings: usb: xhci-tegra: Add power-domain details Add details for power-domains to the Tegra xHCI bindings so that generic power-domains can be used for inconjunction with the xHCI driver. Signed-off-by: Jon Hunter Acked-by: Thierry Reding Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt index 3eee9e505400..4156c3e181c5 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt @@ -59,6 +59,14 @@ For Tegra210: - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. +- power-domains: A list of PM domain specifiers that reference each power-domain + used by the xHCI controller. This list must comprise of a specifier for the + XUSBA and XUSBC power-domains. See ../power/power_domain.txt and + ../arm/tegra/nvidia,tegra20-pmc.txt for details. +- power-domain-names: A list of names that represent each of the specifiers in + the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which + represent the power-domains XUSBA and XUSBC, respectively. See + ../power/power_domain.txt for details. Optional properties: -------------------- -- cgit v1.2.3 From a6cb8ef03cb0f03e3567f91ab9aeb2f0f6337810 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:45 +0300 Subject: dt: bindings: tegra20-emc: Document interrupt property EMC has a dedicated interrupt that is used to notify about completion of HW operations. Document the interrupt property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Acked-by: Peter De Schrijver Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index 4c33b29dc660..a6fe401d0d48 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -10,6 +10,7 @@ Properties: and chosen using the ramcode board selector. If omitted, only one set of tables can be present and said tables will be used irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. Child device nodes describe the memory settings for different configurations and clock rates. @@ -20,6 +21,7 @@ Example: #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; } -- cgit v1.2.3 From 28016aa1652e64e143b88baacbb13f121894f260 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:46 +0300 Subject: dt: bindings: tegra20-emc: Document clock property Embedded memory controller has a corresponding clock, document the clock property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index a6fe401d0d48..add95367640b 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -11,6 +11,7 @@ Properties: set of tables can be present and said tables will be used irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. Child device nodes describe the memory settings for different configurations and clock rates. @@ -22,6 +23,7 @@ Example: compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; interrupts = <0 78 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EMC>; } -- cgit v1.2.3 From 94ba4a5f16710eaa3a675761a7900bb9f79715db Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:47 +0300 Subject: dt: bindings: Move tegra20-emc binding to memory-controllers directory Move tegra20-emc binding to the memory-controllers directory for consistency with the other Tegra memory bindings. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra20-emc.txt | 104 --------------------- .../memory-controllers/nvidia,tegra20-emc.txt | 104 +++++++++++++++++++++ 2 files changed, 104 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt deleted file mode 100644 index add95367640b..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ /dev/null @@ -1,104 +0,0 @@ -Embedded Memory Controller - -Properties: -- name : Should be emc -- #address-cells : Should be 1 -- #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". -- reg : Offset and length of the register set for the device -- nvidia,use-ram-code : If present, the sub-nodes will be addressed - and chosen using the ramcode board selector. If omitted, only one - set of tables can be present and said tables will be used - irrespective of ram-code configuration. -- interrupts : Should contain EMC General interrupt. -- clocks : Should contain EMC clock. - -Child device nodes describe the memory settings for different configurations and clock rates. - -Example: - - memory-controller@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; - interrupts = <0 78 0x04>; - clocks = <&tegra_car TEGRA20_CLK_EMC>; - } - - -Embedded Memory Controller ram-code table - -If the emc node has the nvidia,use-ram-code property present, then the -next level of nodes below the emc table are used to specify which settings -apply for which ram-code settings. - -If the emc node lacks the nvidia,use-ram-code property, this level is omitted -and the tables are stored directly under the emc node (see below). - -Properties: - -- name : Should be emc-tables -- nvidia,ram-code : the binary representation of the ram-code board strappings - for which this node (and children) are valid. - - - -Embedded Memory Controller configuration table - -This is a table containing the EMC register settings for the various -operating speeds of the memory controller. They are always located as -subnodes of the emc controller node. - -There are two ways of specifying which tables to use: - -* The simplest is if there is just one set of tables in the device tree, - and they will always be used (based on which frequency is used). - This is the preferred method, especially when firmware can fill in - this information based on the specific system information and just - pass it on to the kernel. - -* The slightly more complex one is when more than one memory configuration - might exist on the system. The Tegra20 platform handles this during - early boot by selecting one out of possible 4 memory settings based - on a 2-pin "ram code" bootstrap setting on the board. The values of - these strappings can be read through a register in the SoC, and thus - used to select which tables to use. - -Properties: -- name : Should be emc-table -- compatible : Should contain "nvidia,tegra20-emc-table". -- reg : either an opaque enumerator to tell different tables apart, or - the valid frequency for which the table should be used (in kHz). -- clock-frequency : the clock frequency for the EMC at which this - table should be used (in kHz). -- nvidia,emc-registers : a 46 word array of EMC registers to be programmed - for operation at the 'clock-frequency' setting. - The order and contents of the registers are: - RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, - WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, - PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, - TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, - ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, - ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, - CFG_CLKTRIM_1, CFG_CLKTRIM_2 - - emc-table@166000 { - reg = <166000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 166000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 333000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt new file mode 100644 index 000000000000..add95367640b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -0,0 +1,104 @@ +Embedded Memory Controller + +Properties: +- name : Should be emc +- #address-cells : Should be 1 +- #size-cells : Should be 0 +- compatible : Should contain "nvidia,tegra20-emc". +- reg : Offset and length of the register set for the device +- nvidia,use-ram-code : If present, the sub-nodes will be addressed + and chosen using the ramcode board selector. If omitted, only one + set of tables can be present and said tables will be used + irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. + +Child device nodes describe the memory settings for different configurations and clock rates. + +Example: + + memory-controller@7000f400 { + #address-cells = < 1 >; + #size-cells = < 0 >; + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EMC>; + } + + +Embedded Memory Controller ram-code table + +If the emc node has the nvidia,use-ram-code property present, then the +next level of nodes below the emc table are used to specify which settings +apply for which ram-code settings. + +If the emc node lacks the nvidia,use-ram-code property, this level is omitted +and the tables are stored directly under the emc node (see below). + +Properties: + +- name : Should be emc-tables +- nvidia,ram-code : the binary representation of the ram-code board strappings + for which this node (and children) are valid. + + + +Embedded Memory Controller configuration table + +This is a table containing the EMC register settings for the various +operating speeds of the memory controller. They are always located as +subnodes of the emc controller node. + +There are two ways of specifying which tables to use: + +* The simplest is if there is just one set of tables in the device tree, + and they will always be used (based on which frequency is used). + This is the preferred method, especially when firmware can fill in + this information based on the specific system information and just + pass it on to the kernel. + +* The slightly more complex one is when more than one memory configuration + might exist on the system. The Tegra20 platform handles this during + early boot by selecting one out of possible 4 memory settings based + on a 2-pin "ram code" bootstrap setting on the board. The values of + these strappings can be read through a register in the SoC, and thus + used to select which tables to use. + +Properties: +- name : Should be emc-table +- compatible : Should contain "nvidia,tegra20-emc-table". +- reg : either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). +- clock-frequency : the clock frequency for the EMC at which this + table should be used (in kHz). +- nvidia,emc-registers : a 46 word array of EMC registers to be programmed + for operation at the 'clock-frequency' setting. + The order and contents of the registers are: + RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, + WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, + PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, + TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, + ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, + ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, + CFG_CLKTRIM_1, CFG_CLKTRIM_2 + + emc-table@166000 { + reg = <166000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 166000 >; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 >; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 333000 >; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 >; + }; -- cgit v1.2.3 From b59b94f76e7fa257e92d8e8b0c79755493356861 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 12 Nov 2018 14:11:25 -0800 Subject: dt-bindings: iio: vadc: Add unit address to ADC channel node in example The node has a reg property, therefore its name should include a unit address. Also change the name from 'usb_id_nopull' to 'adc-chan', which is the preferred name for ADC channel nodes. Include headers for constants used in the example. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt index b3c86f4ac7cd..c81993f8d8c3 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt @@ -140,6 +140,10 @@ VADC_GND_REF and VADC_VDD_VADC. Example: +#include +#include +/* ... */ + /* VADC node */ pmic_vadc: vadc@3100 { compatible = "qcom,spmi-vadc"; @@ -151,7 +155,7 @@ Example: io-channel-ranges; /* Channel node */ - usb_id_nopull { + adc-chan@VADC_LR_MUX10_USB_ID { reg = ; qcom,decimation = <512>; qcom,ratiometric; -- cgit v1.2.3 From e55b892e1848e220f5248583b99bdcde63fe8f05 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:35:13 +0100 Subject: dt-bindings: timer: meson6_timer: document all interrupts The meson6_timer IP block supports four timers - each of them has it's own interrupt line. Update the documentation to reflect that all four interrupts should be passed. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt index a092053f7902..dbdda92cffb7 100644 --- a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt @@ -4,12 +4,15 @@ Required properties: - compatible : should be "amlogic,meson6-timer" - reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer +- interrupts : The four interrupts, one for each timer event Example: timer@c1109940 { compatible = "amlogic,meson6-timer"; reg = <0xc1109940 0x14>; - interrupts = <0 10 1>; + interrupts = , + , + , + ; }; -- cgit v1.2.3 From be215b92703bd730fe3968ae8ee1de2e22ba5b1d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:35:14 +0100 Subject: dt-bindings: timer: meson6_timer: document the clock inputs The Meson Timer IP has two clock inputs: - pclk which is used as "system clock" timebase of Timer E - xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer A, B, C, D and E The IP block has four internal dividers (XTAL is running at 24MHz): - "xtal div 24" for 1us resolution - "xtal div 240" for 10us resolution - "xtal div 2400" for 100us resolution - "xtal div 24000" for 1ms resolution Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt index dbdda92cffb7..a9da22bda912 100644 --- a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt @@ -5,6 +5,8 @@ Required properties: - compatible : should be "amlogic,meson6-timer" - reg : Specifies base physical address and size of the registers. - interrupts : The four interrupts, one for each timer event +- clocks : phandles to the pclk (system clock) and XTAL clocks +- clock-names : must contain "pclk" and "xtal" Example: @@ -15,4 +17,6 @@ timer@c1109940 { , , ; + clocks = <&xtal>, <&clk81>; + clock-names = "xtal", "pclk"; }; -- cgit v1.2.3 From bebaa63f5c4070be025f29d182d2d43aa443b510 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 14 Nov 2018 09:58:36 +0530 Subject: dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali Allwinner A64 has Mali-400MP2, so document the relevant compatible as "allwinner,sun50i-a64-mali" along with reset line. Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 63cd91176a68..3f128e4f95c6 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -11,6 +11,7 @@ Required properties: + allwinner,sun4i-a10-mali + allwinner,sun7i-a20-mali + allwinner,sun8i-h3-mali + + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali @@ -73,6 +74,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - allwinner,sun50i-a64-mali + Required properties: + * resets: phandle to the reset line for the GPU + - allwinner,sun50i-h5-mali Required properties: * resets: phandle to the reset line for the GPU -- cgit v1.2.3 From 8cc77e014917c65f05a61503bf67d8a2daa0ed90 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 21 Nov 2018 23:44:47 +0800 Subject: Documentation: ARM: sunxi: Add Allwinner SoC T3. Add Allwinner SoC T3 document and fix format. Signed-off-by: Hao Zhang Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index e4beec3d9ad3..94b9c12df96d 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,7 +14,8 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 - allwinner-sun8i-r40 + allwinner,sun8i-r40 + allwinner,sun8i-t3 allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 -- cgit v1.2.3 From 4b5d90f408f82549b5d02f95e5892a5e1545c4b4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 19 Oct 2018 19:30:17 +0900 Subject: dt-bindings: uniphier: add bindings for UniPhier SoC family Document the list of SoCs and boards of UniPhier platform. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/socionext/uniphier.txt | 47 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/uniphier.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt new file mode 100644 index 000000000000..b3ed1033740e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt @@ -0,0 +1,47 @@ +Socionext UniPhier SoC family +----------------------------- + +Required properties in the root node: + - compatible: should contain board and SoC compatible strings + +SoC and board compatible strings: + (sorted chronologically) + + - LD4 SoC: "socionext,uniphier-ld4" + - Reference Board: "socionext,uniphier-ld4-ref" + + - Pro4 SoC: "socionext,uniphier-pro4" + - Reference Board: "socionext,uniphier-pro4-ref" + - Ace Board: "socionext,uniphier-pro4-ace" + - Sanji Board: "socionext,uniphier-pro4-sanji" + + - sLD8 SoC: "socionext,uniphier-sld8" + - Reference Board: "socionext,uniphier-sld8-ref" + + - PXs2 SoC: "socionext,uniphier-pxs2" + - Gentil Board: "socionext,uniphier-pxs2-gentil" + - Vodka Board: "socionext,uniphier-pxs2-vodka" + + - LD6b SoC: "socionext,uniphier-ld6b" + - Reference Board: "socionext,uniphier-ld6b-ref" + + - LD11 SoC: "socionext,uniphier-ld11" + - Reference Board: "socionext,uniphier-ld11-ref" + - Global Board: "socionext,uniphier-ld11-global" + + - LD20 SoC: "socionext,uniphier-ld20" + - Reference Board: "socionext,uniphier-ld20-ref" + - Global Board: "socionext,uniphier-ld20-global" + + - PXs3 SoC: "socionext,uniphier-pxs3" + - Reference Board: "socionext,uniphier-pxs3-ref" + +Example: + +/dts-v1/; + +/ { + compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; + + ... +}; diff --git a/MAINTAINERS b/MAINTAINERS index f4855974f325..1ed6eafdf1df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2247,6 +2247,7 @@ M: Masahiro Yamada L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git S: Maintained +F: Documentation/devicetree/bindings/arm/socionext/uniphier.txt F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt F: arch/arm/boot/dts/uniphier* -- cgit v1.2.3 From 1c36155a802b6192f3ad532da76a12ad7e2b8158 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 19 Oct 2018 19:30:18 +0900 Subject: dt-bindings: uniphier: move cache-uniphier.txt to vendor directory Now, the Socionext vendor directory is available at Documentation/devicetree/bindings/arm/socionext/ Move cache-uniphier.txt over to it. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring --- .../bindings/arm/socionext/cache-uniphier.txt | 60 ++++++++++++++++++++++ .../bindings/arm/uniphier/cache-uniphier.txt | 60 ---------------------- 2 files changed, 60 insertions(+), 60 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt delete mode 100644 Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt new file mode 100644 index 000000000000..d27a646f48a9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt @@ -0,0 +1,60 @@ +UniPhier outer cache controller + +UniPhier SoCs are integrated with a full-custom outer cache controller system. +All of them have a level 2 cache controller, and some have a level 3 cache +controller as well. + +Required properties: +- compatible: should be "socionext,uniphier-system-cache" +- reg: offsets and lengths of the register sets for the device. It should + contain 3 regions: control register, revision register, operation register, + in this order. +- cache-unified: specifies the cache is a unified cache. +- cache-size: specifies the size in bytes of the cache +- cache-sets: specifies the number of associativity sets of the cache +- cache-line-size: specifies the line size in bytes +- cache-level: specifies the level in the cache hierarchy. The value should + be 2 for L2 cache, 3 for L3 cache, etc. + +Optional properties: +- next-level-cache: phandle to the next level cache if present. The next level + cache should be also compatible with "socionext,uniphier-system-cache". + +The L2 cache must exist to use the L3 cache; the cache hierarchy must be +indicated correctly with "next-level-cache" properties. + +Example 1 (system with L2): + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + cache-unified; + cache-size = <0x80000>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + +Example 2 (system with L2 and L3): + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + cache-unified; + cache-size = <0x400000>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt deleted file mode 100644 index d27a646f48a9..000000000000 --- a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt +++ /dev/null @@ -1,60 +0,0 @@ -UniPhier outer cache controller - -UniPhier SoCs are integrated with a full-custom outer cache controller system. -All of them have a level 2 cache controller, and some have a level 3 cache -controller as well. - -Required properties: -- compatible: should be "socionext,uniphier-system-cache" -- reg: offsets and lengths of the register sets for the device. It should - contain 3 regions: control register, revision register, operation register, - in this order. -- cache-unified: specifies the cache is a unified cache. -- cache-size: specifies the size in bytes of the cache -- cache-sets: specifies the number of associativity sets of the cache -- cache-line-size: specifies the line size in bytes -- cache-level: specifies the level in the cache hierarchy. The value should - be 2 for L2 cache, 3 for L3 cache, etc. - -Optional properties: -- next-level-cache: phandle to the next level cache if present. The next level - cache should be also compatible with "socionext,uniphier-system-cache". - -The L2 cache must exist to use the L3 cache; the cache hierarchy must be -indicated correctly with "next-level-cache" properties. - -Example 1 (system with L2): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x80000>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - -Example 2 (system with L2 and L3): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x200000>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, - <0x506c8000 0x400>; - cache-unified; - cache-size = <0x400000>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; -- cgit v1.2.3 From 34e8b809bf136c0554ba1131c6671ae6339543e0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:18:37 +0100 Subject: dt-bindings: thermal: tegra-bpmp: Add Tegra194 support The thermal controller implementation on Tegra194 is very similar to the implementation on Tegra186. Add a compatible string for the new generation. Signed-off-by: Thierry Reding --- .../bindings/thermal/nvidia,tegra186-bpmp-thermal.txt | 3 ++- include/dt-bindings/thermal/tegra194-bpmp-thermal.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/thermal/tegra194-bpmp-thermal.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt index 276387dd6815..e17c07be270b 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt @@ -15,7 +15,8 @@ Required properties: - compatible: Array of strings. One of: - - "nvidia,tegra186-bpmp-thermal". + - "nvidia,tegra186-bpmp-thermal" + - "nvidia,tegra194-bpmp-thermal" - #thermal-sensor-cells: Cell for sensor index. Single-cell integer. Must be <1>. diff --git a/include/dt-bindings/thermal/tegra194-bpmp-thermal.h b/include/dt-bindings/thermal/tegra194-bpmp-thermal.h new file mode 100644 index 000000000000..aa7fb08135ca --- /dev/null +++ b/include/dt-bindings/thermal/tegra194-bpmp-thermal.h @@ -0,0 +1,15 @@ +/* + * This header provides constants for binding nvidia,tegra194-bpmp-thermal. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H +#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H + +#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2 +#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3 +#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4 +#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5 +#define TEGRA194_BPMP_THERMAL_ZONE_AO 6 +#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7 + +#endif -- cgit v1.2.3 From 7038250756c42b2bbe02b04223da14aac3a6f641 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 15:28:28 +0100 Subject: ARM: dts: sunxi: Change default CMA pool node name The CMA node has a unit address, but no reg property which generates a warning in DTC. Change the node name to reflect its usage and drop the unit address. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/media/cedrus.txt | 2 +- arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- arch/arm/boot/dts/sun8i-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt index a089a0c1ff05..33833a43fff8 100644 --- a/Documentation/devicetree/bindings/media/cedrus.txt +++ b/Documentation/devicetree/bindings/media/cedrus.txt @@ -31,7 +31,7 @@ reserved-memory { ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index ac287a0685b2..b957b141e502 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -114,7 +114,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index b4fd4f5ca66b..f7dcf8d21fd2 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -181,7 +181,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 502de6f44a9a..a8b2c4d14f99 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -196,7 +196,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 3ecfabb10151..b3921c5171ed 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -124,7 +124,7 @@ #size-cells = <1>; ranges; - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; -- cgit v1.2.3 From b4c7bf003cb57220af64b59e887581e74f0ce527 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 21 Sep 2018 12:03:54 +0200 Subject: dt-bindings: tegra186-pmc: Add interrupt controller properties The PMC can be a top-level interrupt controller that provides the top- level controls for wake events. Add optional properties to mark the PMC as interrupt controller. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index c9fd6d1de57e..2d89cdc39eb0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -15,6 +15,9 @@ Required properties: Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. Example: -- cgit v1.2.3 From ef29fcc381814f56b7a6dfef5cb498edee176003 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:53:51 +0100 Subject: Documentation: bindings: Add missing Amlogic SCPI sensor bindings amlogic,meson-gxbb-scpi-sensors is both the driver and DT but is not documented. Just add it to amlogic's scpi documentation Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic,scpi.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt index 7b9a861e9306..5ab59da052df 100644 --- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt +++ b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt @@ -17,4 +17,11 @@ Required sub-node properties: - compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared memory on Amlogic GXBB SoC. +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +SCPI provides an API to access the various sensors on the SoC. + +Required properties: +- compatible : should be "amlogic,meson-gxbb-scpi-sensors". + [0] Documentation/devicetree/bindings/arm/arm,scpi.txt -- cgit v1.2.3 From 2078231510714578d044b39109f0ab622bf49582 Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Sat, 10 Nov 2018 11:39:03 +0800 Subject: dt-bindings: Add vendor prefix for PHICOMM Co., Ltd. PHICOMM Co., Ltd. is a hardware provider headquartered in Shanghai, it's product includes router and smart devices. Signed-off-by: He Yangxuan Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..8c413d8cc2a5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -296,6 +296,7 @@ panasonic Panasonic Corporation parade Parade Technologies Inc. pericom Pericom Technology Inc. pervasive Pervasive Displays, Inc. +phicomm PHICOMM Co., Ltd. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd pine64 Pine64 -- cgit v1.2.3 From bf0fbc8f0f06b9aaef81a42c3223b8998fb33eab Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Sat, 10 Nov 2018 11:39:04 +0800 Subject: dt-bindings: arm: amlogic: Add Phicomm N1 Add bindings documentation for the Phicomm N1. Signed-off-by: He Yangxuan Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 4498292b833d..93177f38ec19 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -91,6 +91,7 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,p230" (Meson gxl s905d) - "amlogic,p231" (Meson gxl s905d) + - "phicomm,n1" (Meson gxl s905d) - "amlogic,p241" (Meson gxl s805x) -- cgit v1.2.3 From bc3285052afb7f8405b56831b028e14545d08891 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 16 Nov 2018 16:15:38 +0100 Subject: dt-bindings: arm: amlogic: add libretech aml-s805x-ac bindings Add bindings for the Libretech aml-s805x-ac board, aka 'La Frite'. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 93177f38ec19..8dbc259081e4 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -94,6 +94,7 @@ Board compatible values (alphabetically, grouped by SoC): - "phicomm,n1" (Meson gxl s905d) - "amlogic,p241" (Meson gxl s805x) + - "libretech,aml-s805x-ac" (Meson gxl s805x) - "amlogic,p281" (Meson gxl s905w) - "oranth,tx3-mini" (Meson gxl s905w) -- cgit v1.2.3 From ca40d2bd813efcee058760c63c9eae043d2939d9 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:05 +0100 Subject: dt-bindings: mrvl,mmp-timer: add clock The timer needs the timer clock to be enabled, otherwise it stops ticking. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt index 9a6e251462e7..b8f02c663521 100644 --- a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt +++ b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt @@ -5,9 +5,13 @@ Required properties: - reg : Address and length of the register set of timer controller. - interrupts : Should be the interrupt number. +Optional properties: +- clocks : Should contain a single entry describing the clock input. + Example: timer0: timer@d4014000 { compatible = "mrvl,mmp-timer"; reg = <0xd4014000 0x100>; interrupts = <13>; + clocks = <&coreclk 2>; }; -- cgit v1.2.3 From fa3abfb6943ef2976deda78d83788a1352963f47 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:38 +0100 Subject: dt-bindings: clk: meson: add ao controller clock inputs Add the clock inputs of amlogic AO clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- .../devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a880528030e..79511d7bb321 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -11,6 +11,13 @@ Required Properties: - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" +- clocks: list of clock phandle, one for each entry clock-names. +- clock-names: should contain the following: + * "xtal" : the platform xtal + * "mpeg-clk" : the main clock controller mother clock (aka clk81) + * "ext-32k-0" : external 32kHz reference #0 if any (optional) + * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) + * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) - #clock-cells: should be 1. @@ -40,8 +47,9 @@ ao_sysctrl: sys-ctrl@0 { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; -}; Example: UART controller node that consumes the clock and reset generated by the clock controller: -- cgit v1.2.3 From b1d02a84b552fde1232dc11b3c8465433fa1339d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:39 +0100 Subject: dt-bindings: clk: meson: add main controller clock input Add the clock input of the main clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599566a9..a6871953bf04 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,9 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. +- clocks : list of clock phandle, one for each entry clock-names. +- clock-names : should contain the following: + * "xtal": the platform xtal - #clock-cells: should be 1. @@ -31,6 +34,8 @@ sysctrl: system-controller@0 { clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; }; }; -- cgit v1.2.3 From 36ead91499160b459d66cd70949511cde829204f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 28 Aug 2018 08:45:54 +0200 Subject: ARM: dts: rockchip: add BQ Edison 2 QC devicetree The Edison 2 Quad-Core was a Tablet device released in 2013 by MundoReader using a rk3188 soc. Add a devicetree for it. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3188-bqedison2qc.dts | 711 +++++++++++++++++++++ 3 files changed, 716 insertions(+) create mode 100644 arch/arm/boot/dts/rk3188-bqedison2qc.dts (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 0cc71236d639..4e37938edbe9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -33,6 +33,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; +- bq Edison 2 Quad-Core tablet: + Required root node properties: + - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + - ChipSPARK Rayeager PX2 board: Required root node properties: - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..71d6c015f246 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -854,6 +854,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-marsboard.dtb \ rk3066a-mk808.dtb \ rk3066a-rayeager.dtb \ + rk3188-bqedison2qc.dtb \ rk3188-px3-evb.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts new file mode 100644 index 000000000000..a7477a09fbe8 --- /dev/null +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -0,0 +1,711 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 MundoReader S.L. + * Author: Heiko Stuebner + */ + +/dts-v1/; +#include +#include +#include "rk3188.dtsi" + +/ { + model = "BQ Edison2 Quad-Core"; + compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vsys>; + pwms = <&pwm1 0 25000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key &usb_int>; + + power { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + + wake_on_usb: wake-on-usb { + label = "Wake-on-USB"; + gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_hold>; + /* only drive the pin low until device is off */ + active-delay-ms = <3000>; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in_vop0: endpoint { + remote-endpoint = <&vop0_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + + panel { + compatible = "innolux,ee101ia-01d", "panel-lvds"; + backlight = <&backlight>; + + /* pin LCD_CS, Nshtdn input of lvds-encoder */ + enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_cs>; + power-supply = <&vcc_lcd>; + + data-mapping = "vesa-24"; + height-mm = <163>; + width-mm = <261>; + + panel-timing { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <160>; + hfront-porch = <16>; + hsync-len = <10>; + vback-porch = <23>; + vfront-porch = <12>; + vsync-len = <3>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; + }; + + avdd_cif: cif-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd-cif"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_avdd_en>; + startup-delay-us = <100000>; + vin-supply = <&vcc28_cif>; + }; + + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&v5_drv>; + vin-supply = <&vsys>; + }; + + vcc_lcd: lcd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-lcd"; + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + startup-delay-us = <50000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_drv>; + startup-delay-us = <100000>; + vin-supply = <&vcc_5v>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vccq_emmc: emmc-vccq-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccq-emmc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + /* supplied from the bq24196 */ + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cru { + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <504000000>, + <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccq_emmc>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + lis3de: accelerometer@29 { + compatible = "st,lis3de"; + reg = <0x29>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + rotation-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + vdd-supply = <&vcc_io>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + tmp108@48 { + compatible = "ti,tmp108"; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tmp_alrt>; + #thermal-sensor-cells = <0>; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + bat: battery@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + power-supplies = <&bq24196>; + }; + + act8846: pmic@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&dvs0_ctl &pmic_int>; + + vp1-supply = <&vsys>; + vp2-supply = <&vsys>; + vp3-supply = <&vsys>; + vp4-supply = <&vsys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vsys>; + inl3-supply = <&vsys>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_log: REG2 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_arm: REG3 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vcc_io: vcc_hdmi: REG4 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_10: REG5 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_12: REG6 { + regulator-name = "VDD_12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc18_cif: REG7 { + regulator-name = "VCC18_CIF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_tp: REG9 { + regulator-name = "VCC_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_wl: REG10 { + regulator-name = "VCCIO_WL"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc28_cif: REG12 { + regulator-name = "VCC28_CIF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; + + bq24196: charger@6b { + compatible = "ti,bq24196"; + reg = <0x6b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_int &chg_ctl &otg_en>; + ti,system-minimum-microvolt = <3200000>; + monitored-battery = <&bat>; + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + rt5616: codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + clocks = <&cru SCLK_I2S0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; + vmmcq-supply = <&vccio_wl>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio3>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + dvs0_ctl: dvs0-ctl { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + bq24196 { + charger_int: charger-int { + rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* pin hog to make it select usb profile */ + chg_ctl: chg-ctl { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + /* low: charging, high: complete, fault: blinking */ + chg_det: chg-det { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* charging enabled when pin low and register set */ + chg_en: chg-en { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + /* bq29196 powergood (when low) signal */ + dc_det: dc-det { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* wire bq24196 otg pin to high, to enable 500mA charging */ + otg_en: otg-en { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + camera { + cif0_pdn: cif0-pdn { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif1_pdn: cif1-pdn { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif_avdd_en: cif-avdd-en { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + display { + lcd_cs: lcd-cs { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_en: lcd-en { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ft5606 { + tp_int: tp-int { + rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst: tp-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_int: hdmi-int { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdmi_rst: hdmi-rst { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_hold: pwr-hold { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lis3de { + gsensor_int: gsensor-int { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tmp108 { + tmp_alrt: tmp-alrt { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + v5_drv: v5-drv { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_drv: otg-drv { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_int: usb-int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rk903 { + bt_host_wake: bt-host-wake { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_reg_on: bt-reg-on { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* pin hog to pull the reset high */ + bt_rst: bt-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop0 { + status = "okay"; +}; + +&vop0_out { + vop0_out_lvds: endpoint { + remote-endpoint = <&lvds_in_vop0>; + }; +}; + +&vop1 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync + &lcdc1_vsync &lcdc1_rgb24>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit v1.2.3 From 1deb430d291270f9d0067061a5dc7409819dfcfb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 26 Sep 2018 09:21:44 +0100 Subject: dt-bindings: arm: renesas: Document iWave RZ/G1N SOM Document the iW-RainboW-G20M-RZ/G1N Qseven device tree bindings, listing it as a supported system on module. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index f5e0f82fd503..4cfb56787a90 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -101,6 +101,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) + compatible = "iwave,g20m", "renesas,r8a7744" - Kingfisher (SBEV-RCAR-KF-M03) compatible = "shimafuji,kingfisher" - Koelsch (RTP0RC7791SEB00010S) -- cgit v1.2.3 From ea456bf918e31a0f755c5c02963b4e10513fa82c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 26 Sep 2018 11:44:46 +0100 Subject: dt-bindings: arm: renesas: Document iW-RainboW-G20D-Qseven-RZG1N board Document the iW-RainboW-G20D-Qseven-RZG1N device tree bindings, listing it as a supported board. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 4cfb56787a90..144f045a9f4b 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -101,6 +101,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744" - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7744" - Kingfisher (SBEV-RCAR-KF-M03) -- cgit v1.2.3 From 74791d15fd7c405511e3cc097c2f043171ecbdb0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 3 Dec 2018 15:32:14 -0600 Subject: dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Signed-off-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../devicetree/bindings/arm/renesas,prr.txt | 20 ++++++++++++++++++++ Documentation/devicetree/bindings/arm/shmobile.txt | 18 ------------------ 2 files changed, 20 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt new file mode 100644 index 000000000000..08e482e953ca --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.txt @@ -0,0 +1,20 @@ +Renesas Product Register + +Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that +allows to retrieve SoC product and revision information. If present, a device +node for this register should be added. + +Required properties: + - compatible: Must be one of: + "renesas,prr" + "renesas,bsid" + - reg: Base address and length of the register block. + + +Examples +-------- + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 144f045a9f4b..92cda17870d3 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -153,21 +153,3 @@ Boards: compatible = "renesas,v3msk", "renesas,r8a77970" - Wheat (RTP0RC7792ASKB0000JE) compatible = "renesas,wheat", "renesas,r8a7792" - - -Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that -allows to retrieve SoC product and revision information. If present, a device -node for this register should be added. - -Required properties: - - compatible: Must be "renesas,prr" or "renesas,bsid" - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; -- cgit v1.2.3 From 8ff7754ae1f57c50a977aab7565ab84376ed6af6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:17 +0000 Subject: dt-bindings: pci: layerscape-pci: add compatible strings "fsl,ls1043a-pcie" The PCIe compatible string for LS1043A was lost, so add it. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 66df1e81e0b8..5eb1c202932f 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -18,6 +18,7 @@ Required properties: "fsl,ls2088a-pcie" "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" + "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an -- cgit v1.2.3 From ac8ed2824e8d7655bbf4eb6d22ee08ca3f1f63d4 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:22 +0000 Subject: dt-bindings: pci: layerscape-pci: removed compatible string "snps,dw-pcie" Removed the compatible string "snps,dw-pcie", it is for the reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP, so it is not suitable for all platform with designware PCIe controller, and platform vendors have themselves' drivers. The compatible string "snsp,dw-pcie" was added by mistake and it's not matched that time, but it is matched because PCIe drivers has been collected recently. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 5eb1c202932f..9b2b8d66d1f4 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -13,8 +13,8 @@ information. Required properties: - compatible: should contain the platform identifier such as: - "fsl,ls1021a-pcie", "snps,dw-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" + "fsl,ls1021a-pcie" + "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" "fsl,ls2088a-pcie" "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" @@ -36,7 +36,7 @@ Required properties: Example: pcie@3400000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1021a-pcie"; reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; -- cgit v1.2.3 From d87cf8ce52820256dcff3a52871d67e3994e39e0 Mon Sep 17 00:00:00 2001 From: Jan Tuerk Date: Tue, 27 Nov 2018 16:04:02 +0100 Subject: dt-bindings: arm: Document emtrion emCON-MX6 bindings Document the compatible strings for emtrion emCON-MX6 SoM's. Signed-off-by: Jan Tuerk Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/emtrion.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..83329aefc483 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,12 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base -- cgit v1.2.3 From 2bf5751726e8face217a39f2132df643b995d8bc Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:12:56 +0000 Subject: dt-bindings: fsl: add compatible for imx7ulp evk Add compatible string for imx7ulp evk board. Cc: devicetree@vger.kernel.org Cc: Shawn Guo Acked-by: Rob Herring Signed-off-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 5074aeecd327..7fbc42484001 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -101,6 +101,10 @@ i.MX7 SabreSD Board Required root node properties: - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; +i.MX7ULP Evaluation Kit +Required root node properties: + - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; + Generic i.MX boards ------------------- @@ -123,6 +127,10 @@ i.MX6q generic board Required root node properties: - compatible = "fsl,imx6q"; +i.MX7ULP generic board +Required root node properties: + - compatible = "fsl,imx7ulp"; + Freescale Vybrid Platform Device Tree Bindings ---------------------------------------------- -- cgit v1.2.3 From 61ccb001534b7d555e01d013ecb7f94bbf3d1bbe Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:13:00 +0000 Subject: dt-bindings: fsl: add imx7ulp pm related components bindings Add imx7ulp pm related components bindings. Cc: Shawn Guo Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../bindings/arm/freescale/fsl,imx7ulp-pm.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt new file mode 100644 index 000000000000..75195bee116f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt @@ -0,0 +1,23 @@ +Freescale i.MX7ULP Power Management Components +---------------------------------------------- + +The Multi-System Mode Controller (MSMC) is responsible for sequencing +the MCU into and out of all stop and run power modes. Specifically, it +monitors events to trigger transitions between power modes while +controlling the power, clocks, and memories of the MCU to achieve the +power consumption and functionality of that mode. + +The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or +Standby modes for either Cortex family. Run, Wait, and Stop are the +common terms used for the primary operating modes of Kinetis +microcontrollers. + +Required properties: +- compatible: Should be "fsl,imx7ulp-smc1". +- reg: Specifies base physical address and size of the register sets. + +Example: +smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; +}; -- cgit v1.2.3 From 7841b88a8fdddc0e7f3377fc42efe4cb3be1ed8b Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 26 Nov 2018 15:35:06 -0200 Subject: ARM: dts: rockchip: Add internal timer support for rv1108 Add support for the internal timer peripheral on RV1108. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt | 1 + arch/arm/boot/dts/rv1108.dtsi | 8 ++++++++ 2 files changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt index 16a5f4577a61..d65fdce7c7f0 100644 --- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt +++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt @@ -2,6 +2,7 @@ Rockchip rk timer Required properties: - compatible: should be: + "rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108 "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036 "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066 "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188 diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 17dbcf2571fd..d31370ff28f4 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -293,6 +293,14 @@ }; }; + timer: timer@10350000 { + compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; + reg = <0x10350000 0x20>; + interrupts = ; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + watchdog: wdt@10360000 { compatible = "snps,dw-wdt"; reg = <0x10360000 0x100>; -- cgit v1.2.3 From a323a513c7128e1597e59f6d3db38c426d229cb9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Dec 2018 09:50:11 +0100 Subject: dt-bindings: arm: Convert Rockchip board/soc bindings to json-schema Convert Rockchip SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Heiko Stuebner Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring [move to per-board entries after confirming with Rob and added recently added boards] Signed-off-by: Heiko Stuebner Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/rockchip.txt | 278 -------------- .../devicetree/bindings/arm/rockchip.yaml | 423 +++++++++++++++++++++ 2 files changed, 423 insertions(+), 278 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/rockchip.txt create mode 100644 Documentation/devicetree/bindings/arm/rockchip.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt deleted file mode 100644 index 6445dbc25c29..000000000000 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ /dev/null @@ -1,278 +0,0 @@ -Rockchip platforms device tree bindings ---------------------------------------- - -- 96boards RK3399 Ficus (ROCK960 Enterprise Edition) - Required root node properties: - - compatible = "vamrs,ficus", "rockchip,rk3399"; - -- 96boards RK3399 Rock960 (ROCK960 Consumer Edition) - Required root node properties: - - compatible = "vamrs,rock960", "rockchip,rk3399"; - -- Amarula Vyasa RK3288 board - Required root node properties: - - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - -- Asus Tinker board - Required root node properties: - - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; - -- Asus Tinker board S - Required root node properties: - - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; - -- Kylin RK3036 board: - Required root node properties: - - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036"; - -- MarsBoard RK3066 board: - Required root node properties: - - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - -- bq Curie 2 tablet: - Required root node properties: - - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - -- bq Edison 2 Quad-Core tablet: - Required root node properties: - - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; - -- ChipSPARK Rayeager PX2 board: - Required root node properties: - - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - -- Radxa Rock board: - Required root node properties: - - compatible = "radxa,rock", "rockchip,rk3188"; - -- Radxa Rock2 Square board: - Required root node properties: - - compatible = "radxa,rock2-square", "rockchip,rk3288"; - -- Rikomagic MK808 v1 board: - Required root node properties: - - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - -- Firefly Firefly-RK3288 board: - Required root node properties: - - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; - or - - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; - -- Firefly Firefly-RK3288 Reload board: - Required root node properties: - - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - -- Firefly Firefly-RK3399 board: - Required root node properties: - - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; - -- Firefly roc-rk3328-cc board: - Required root node properties: - - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - -- Firefly ROC-RK3399-PC board: - Required root node properties: - - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - -- ChipSPARK PopMetal-RK3288 board: - Required root node properties: - - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - -- Netxeon R89 board: - Required root node properties: - - compatible = "netxeon,r89", "rockchip,rk3288"; - -- GeekBuying GeekBox: - Required root node properties: - - compatible = "geekbuying,geekbox", "rockchip,rk3368"; - -- Google Bob (Asus Chromebook Flip C101PA): - Required root node properties: - compatible = "google,bob-rev13", "google,bob-rev12", - "google,bob-rev11", "google,bob-rev10", - "google,bob-rev9", "google,bob-rev8", - "google,bob-rev7", "google,bob-rev6", - "google,bob-rev5", "google,bob-rev4", - "google,bob", "google,gru", "rockchip,rk3399"; - -- Google Brain (dev-board): - Required root node properties: - - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - -- Google Gru (dev-board): - Required root node properties: - - compatible = "google,gru-rev15", "google,gru-rev14", - "google,gru-rev13", "google,gru-rev12", - "google,gru-rev11", "google,gru-rev10", - "google,gru-rev9", "google,gru-rev8", - "google,gru-rev7", "google,gru-rev6", - "google,gru-rev5", "google,gru-rev4", - "google,gru-rev3", "google,gru-rev2", - "google,gru", "rockchip,rk3399"; - -- Google Jaq (Haier Chromebook 11 and more): - Required root node properties: - - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; - -- Google Jerry (Hisense Chromebook C11 and more): - Required root node properties: - - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - -- Google Kevin (Samsung Chromebook Plus): - Required root node properties: - - compatible = "google,kevin-rev15", "google,kevin-rev14", - "google,kevin-rev13", "google,kevin-rev12", - "google,kevin-rev11", "google,kevin-rev10", - "google,kevin-rev9", "google,kevin-rev8", - "google,kevin-rev7", "google,kevin-rev6", - "google,kevin", "google,gru", "rockchip,rk3399"; - -- Google Mickey (Asus Chromebit CS10): - Required root node properties: - - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - -- Google Minnie (Asus Chromebook Flip C100P): - Required root node properties: - - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - -- Google Pinky (dev-board): - Required root node properties: - - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - -- Google Scarlet - with display from Kingdisplay - Required root node properties: - - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", - "google,scarlet-rev14-sku7", "google,scarlet-rev14", - "google,scarlet-rev13-sku7", "google,scarlet-rev13", - "google,scarlet-rev12-sku7", "google,scarlet-rev12", - "google,scarlet-rev11-sku7", "google,scarlet-rev11", - "google,scarlet-rev10-sku7", "google,scarlet-rev10", - "google,scarlet-rev9-sku7", "google,scarlet-rev9", - "google,scarlet-rev8-sku7", "google,scarlet-rev8", - "google,scarlet-rev7-sku7", "google,scarlet-rev7", - "google,scarlet-rev6-sku7", "google,scarlet-rev6", - "google,scarlet-rev5-sku7", "google,scarlet-rev5", - "google,scarlet-rev4-sku7", "google,scarlet-rev4", - "google,scarlet-rev3-sku7", "google,scarlet-rev3", - "google,scarlet", "google,gru", "rockchip,rk3399"; - -- Google Scarlet - with display from Innolux - Required root node properties: - - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", - "google,scarlet-rev14-sku6", "google,scarlet-rev14", - "google,scarlet-rev13-sku6", "google,scarlet-rev13", - "google,scarlet-rev12-sku6", "google,scarlet-rev12", - "google,scarlet-rev11-sku6", "google,scarlet-rev11", - "google,scarlet-rev10-sku6", "google,scarlet-rev10", - "google,scarlet-rev9-sku6", "google,scarlet-rev9", - "google,scarlet-rev8-sku6", "google,scarlet-rev8", - "google,scarlet-rev7-sku6", "google,scarlet-rev7", - "google,scarlet-rev6-sku6", "google,scarlet-rev6", - "google,scarlet-rev5-sku6", "google,scarlet-rev5", - "google,scarlet-rev4-sku6", "google,scarlet-rev4", - "google,scarlet", "google,gru", "rockchip,rk3399"; - - -- Google Speedy (Asus C201 Chromebook): - Required root node properties: - - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - -- mqmaker MiQi: - Required root node properties: - - compatible = "mqmaker,miqi", "rockchip,rk3288"; - -- Phytec phyCORE-RK3288: Rapid Development Kit - Required root node properties: - - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; - -- Pine64 Rock64 board: - Required root node properties: - - compatible = "pine64,rock64", "rockchip,rk3328"; - -- Pine64 RockPro64 board: - Required root node properties: - - compatible = "pine64,rockpro64", "rockchip,rk3399"; - -- Rockchip PX3 Evaluation board: - Required root node properties: - - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; - -- Rockchip PX5 Evaluation board: - Required root node properties: - - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; - -- Rockchip PX30 Evaluation board: - Required root node properties: - - compatible = "rockchip,px30-evb", "rockchip,px30"; - -- Rockchip RV1108 Evaluation board - Required root node properties: - - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - -- Rockchip RK3368 evb: - Required root node properties: - - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; - -- Rockchip R88 board: - Required root node properties: - - compatible = "rockchip,r88", "rockchip,rk3368"; - -- Rockchip RK3228 Evaluation board: - Required root node properties: - - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - -- Rockchip RK3229 Evaluation board: - - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - -- Rockchip RK3288 Fennec board: - Required root node properties: - - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - -- Rockchip RK3328 evb: - Required root node properties: - - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - -- Rockchip RK3399 evb: - Required root node properties: - - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire board standalone: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire Excavator board: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; - -- Theobroma Systems RK3368-uQ7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368"; - -- Theobroma Systems RK3399-Q7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399"; - -- Tronsmart Orion R68 Meta - Required root node properties: - - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml new file mode 100644 index 000000000000..b12958bda09c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -0,0 +1,423 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/rockchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip platforms device tree bindings + +maintainers: + - Heiko Stuebner + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition) + items: + - const: vamrs,ficus + - const: rockchip,rk3399 + + - description: 96boards RK3399 Rock960 (ROCK960 Consumer Edition) + items: + - const: vamrs,rock960 + - const: rockchip,rk3399 + + - description: Amarula Vyasa RK3288 + items: + - const: amarula,vyasa-rk3288 + - const: rockchip,rk3288 + + - description: Asus Tinker board + items: + - const: asus,rk3288-tinker + - const: rockchip,rk3288 + + - description: Asus Tinker board S + items: + - const: asus,rk3288-tinker-s + - const: rockchip,rk3288 + + - description: bq Curie 2 tablet + items: + - const: mundoreader,bq-curie2 + - const: rockchip,rk3066a + + - description: bq Edison 2 Quad-Core tablet + items: + - const: mundoreader,bq-edison2qc + - const: rockchip,rk3188 + + - description: ChipSPARK PopMetal-RK3288 + items: + - const: chipspark,popmetal-rk3288 + - const: rockchip,rk3288 + + - description: ChipSPARK Rayeager PX2 + items: + - const: chipspark,rayeager-px2 + - const: rockchip,rk3066a + + - description: Firefly Firefly-RK3288 + items: + - enum: + - firefly,firefly-rk3288 + - firefly,firefly-rk3288-beta + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3288 Reload + items: + - const: firefly,firefly-rk3288-reload + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3399 + items: + - const: firefly,firefly-rk3399 + - const: rockchip,rk3399 + + - description: Firefly roc-rk3328-cc + items: + - const: firefly,roc-rk3328-cc + - const: rockchip,rk3328 + + - description: Firefly ROC-RK3399-PC + items: + - const: firefly,roc-rk3399-pc + - const: rockchip,rk3399 + + - description: GeekBuying GeekBox + items: + - const: geekbuying,geekbox + - const: rockchip,rk3368 + + - description: Google Bob (Asus Chromebook Flip C101PA) + items: + - const: google,bob-rev13 + - const: google,bob-rev12 + - const: google,bob-rev11 + - const: google,bob-rev10 + - const: google,bob-rev9 + - const: google,bob-rev8 + - const: google,bob-rev7 + - const: google,bob-rev6 + - const: google,bob-rev5 + - const: google,bob-rev4 + - const: google,bob + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Brain (dev-board) + items: + - const: google,veyron-brain-rev0 + - const: google,veyron-brain + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Gru (dev-board) + items: + - const: google,gru-rev15 + - const: google,gru-rev14 + - const: google,gru-rev13 + - const: google,gru-rev12 + - const: google,gru-rev11 + - const: google,gru-rev10 + - const: google,gru-rev9 + - const: google,gru-rev8 + - const: google,gru-rev7 + - const: google,gru-rev6 + - const: google,gru-rev5 + - const: google,gru-rev4 + - const: google,gru-rev3 + - const: google,gru-rev2 + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Jaq (Haier Chromebook 11 and more) + items: + - const: google,veyron-jaq-rev5 + - const: google,veyron-jaq-rev4 + - const: google,veyron-jaq-rev3 + - const: google,veyron-jaq-rev2 + - const: google,veyron-jaq-rev1 + - const: google,veyron-jaq + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Jerry (Hisense Chromebook C11 and more) + items: + - const: google,veyron-jerry-rev7 + - const: google,veyron-jerry-rev6 + - const: google,veyron-jerry-rev5 + - const: google,veyron-jerry-rev4 + - const: google,veyron-jerry-rev3 + - const: google,veyron-jerry + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Kevin (Samsung Chromebook Plus) + items: + - const: google,kevin-rev15 + - const: google,kevin-rev14 + - const: google,kevin-rev13 + - const: google,kevin-rev12 + - const: google,kevin-rev11 + - const: google,kevin-rev10 + - const: google,kevin-rev9 + - const: google,kevin-rev8 + - const: google,kevin-rev7 + - const: google,kevin-rev6 + - const: google,kevin + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Mickey (Asus Chromebit CS10) + items: + - const: google,veyron-mickey-rev8 + - const: google,veyron-mickey-rev7 + - const: google,veyron-mickey-rev6 + - const: google,veyron-mickey-rev5 + - const: google,veyron-mickey-rev4 + - const: google,veyron-mickey-rev3 + - const: google,veyron-mickey-rev2 + - const: google,veyron-mickey-rev1 + - const: google,veyron-mickey-rev0 + - const: google,veyron-mickey + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Minnie (Asus Chromebook Flip C100P) + items: + - const: google,veyron-minnie-rev4 + - const: google,veyron-minnie-rev3 + - const: google,veyron-minnie-rev2 + - const: google,veyron-minnie-rev1 + - const: google,veyron-minnie-rev0 + - const: google,veyron-minnie + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Pinky (dev-board) + items: + - const: google,veyron-pinky-rev2 + - const: google,veyron-pinky + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku7 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku7 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku7 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku7 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku7 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku7 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku7 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku7 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku7 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku7 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku7 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku7 + - const: google,scarlet-rev4 + - const: google,scarlet-rev3-sku7 + - const: google,scarlet-rev3 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku6 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku6 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku6 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku6 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku6 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku6 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku6 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku6 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku6 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku6 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku6 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku6 + - const: google,scarlet-rev4 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Speedy (Asus C201 Chromebook) + items: + - const: google,veyron-speedy-rev9 + - const: google,veyron-speedy-rev8 + - const: google,veyron-speedy-rev7 + - const: google,veyron-speedy-rev6 + - const: google,veyron-speedy-rev5 + - const: google,veyron-speedy-rev4 + - const: google,veyron-speedy-rev3 + - const: google,veyron-speedy-rev2 + - const: google,veyron-speedy + - const: google,veyron + - const: rockchip,rk3288 + + - description: Haoyu MarsBoard RK3066 + items: + - const: haoyu,marsboard-rk3066 + - const: rockchip,rk3066a + + - description: mqmaker MiQi + items: + - const: mqmaker,miqi + - const: rockchip,rk3288 + + - description: Netxeon R89 board + items: + - const: netxeon,r89 + - const: rockchip,rk3288 + + - description: Phytec phyCORE-RK3288 Rapid Development Kit + items: + - const: phytec,rk3288-pcm-947 + - const: phytec,rk3288-phycore-som + - const: rockchip,rk3288 + + - description: Pine64 Rock64 + items: + - const: pine64,rock64 + - const: rockchip,rk3328 + + - description: Pine64 RockPro64 + items: + - const: pine64,rockpro64 + - const: rockchip,rk3399 + + - description: Radxa Rock + items: + - const: radxa,rock + - const: rockchip,rk3188 + + - description: Radxa Rock2 Square + items: + - const: radxa,rock2-square + - const: rockchip,rk3288 + + - description: Rikomagic MK808 v1 + items: + - const: rikomagic,mk808 + - const: rockchip,rk3066a + + - description: Rockchip Kylin + items: + - const: rockchip,kylin-rk3036 + - const: rockchip,rk3036 + + - description: Rockchip PX3 Evaluation board + items: + - const: rockchip,px3-evb + - const: rockchip,px3 + - const: rockchip,rk3188 + + - description: Rockchip PX30 Evaluation board + items: + - const: rockchip,px30-evb + - const: rockchip,px30 + + - description: Rockchip PX5 Evaluation board + items: + - const: rockchip,px5-evb + - const: rockchip,px5 + - const: rockchip,rk3368 + + - description: Rockchip R88 + items: + - const: rockchip,r88 + - const: rockchip,rk3368 + + - description: Rockchip RK3228 Evaluation board + items: + - const: rockchip,rk3228-evb + - const: rockchip,rk3228 + + - description: Rockchip RK3229 Evaluation board + items: + - const: rockchip,rk3229-evb + - const: rockchip,rk3229 + + - description: Rockchip RK3288 Evaluation board + items: + - enum: + - rockchip,rk3288-evb-act8846 + - rockchip,rk3288-evb-rk808 + - const: rockchip,rk3288 + + - description: Rockchip RK3288 Fennec + items: + - const: rockchip,rk3288-fennec + - const: rockchip,rk3288 + + - description: Rockchip RK3328 Evaluation board + items: + - const: rockchip,rk3328-evb + - const: rockchip,rk3328 + + - description: Rockchip RK3368 Evaluation board (act8846 pmic) + items: + - const: rockchip,rk3368-evb-act8846 + - const: rockchip,rk3368 + + - description: Rockchip RK3399 Evaluation board + items: + - const: rockchip,rk3399-evb + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire standalone + items: + - const: rockchip,rk3399-sapphire + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire with Excavator Baseboard + items: + - const: rockchip,rk3399-sapphire-excavator + - const: rockchip,rk3399 + + - description: Rockchip RV1108 Evaluation board + items: + - const: rockchip,rv1108-evb + - const: rockchip,rv1108 + + - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard + items: + - const: tsd,rk3368-uq7-haikou + - const: rockchip,rk3368 + + - description: Theobroma Systems RK3399-Q7 with Haikou baseboard + items: + - const: tsd,rk3399-q7-haikou + - const: rockchip,rk3399 + + - description: Tronsmart Orion R68 Meta + items: + - const: tronsmart,orion-r68-meta + - const: rockchip,rk3368 +... -- cgit v1.2.3