From ff46c610abd62a3dc120dc05ad726b2a47d347ea Mon Sep 17 00:00:00 2001 From: Gerhard Engleder Date: Tue, 27 Sep 2022 21:58:37 +0200 Subject: dt-bindings: net: tsnep: Allow dma-coherent Within SoCs like ZynqMP, FPGA logic can be connected to different kinds of AXI master ports. Also cache coherent AXI master ports are available. The property "dma-coherent" is used to signal that DMA is cache coherent. Add "dma-coherent" property to allow the configuration of cache coherent DMA. Signed-off-by: Gerhard Engleder Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml index d0e1476e15b5..37e08ee744a8 100644 --- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml +++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml @@ -22,6 +22,8 @@ properties: interrupts: maxItems: 1 + dma-coherent: true + local-mac-address: true mac-address: true -- cgit v1.2.3