From 77f969a717b953296c036004b1a96f9d1087cef6 Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Thu, 13 Jul 2023 16:07:13 -0700 Subject: MAINTAINERS: treat Documentation/maintainer as process docs A handful of people got caught out by the recent changes in git which changed the format of Message-ID and broke our recommended applyhook for adding lore links. This was fixed in the docs by commit 2bb19e740e9b ("Documentation: update git configuration for Link: tag") but it seems like few people have noticed. Add maintainer directory to the process entry so that workflows@ gets CCed. Signed-off-by: Jakub Kicinski Reviewed-by: Randy Dunlap Signed-off-by: Jonathan Corbet Message-ID: <20230713230713.1505561-1-kuba@kernel.org> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 3be1bdfe8ecc..fff7e50948b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6206,6 +6206,7 @@ DOCUMENTATION PROCESS M: Jonathan Corbet L: workflows@vger.kernel.org S: Maintained +F: Documentation/maintainer/ F: Documentation/process/ DOCUMENTATION REPORTING ISSUES -- cgit v1.2.3 From 44a54e25b1dd2dec9810064406c1d0839e709e63 Mon Sep 17 00:00:00 2001 From: Hu Haowen Date: Sat, 8 Jul 2023 00:01:19 +0800 Subject: docs/zh_CN: change my own email address The previous email address was abandoned due to some reasons by myself, and thus shift the email contents mentioned from the old email address (src.res@email.cn) to the current version (src.res.211@gmail.com). Signed-off-by: Hu Haowen Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20230707160119.26873-1-src.res.211@gmail.com --- Documentation/translations/zh_CN/dev-tools/testing-overview.rst | 2 +- Documentation/translations/zh_TW/IRQ.txt | 8 ++++---- Documentation/translations/zh_TW/admin-guide/README.rst | 2 +- Documentation/translations/zh_TW/admin-guide/bug-bisect.rst | 2 +- Documentation/translations/zh_TW/admin-guide/bug-hunting.rst | 2 +- .../translations/zh_TW/admin-guide/clearing-warn-once.rst | 2 +- Documentation/translations/zh_TW/admin-guide/cpu-load.rst | 2 +- Documentation/translations/zh_TW/admin-guide/index.rst | 2 +- Documentation/translations/zh_TW/admin-guide/init.rst | 2 +- Documentation/translations/zh_TW/admin-guide/reporting-issues.rst | 2 +- Documentation/translations/zh_TW/admin-guide/security-bugs.rst | 2 +- Documentation/translations/zh_TW/admin-guide/tainted-kernels.rst | 2 +- Documentation/translations/zh_TW/admin-guide/unicode.rst | 2 +- Documentation/translations/zh_TW/arch/arm64/amu.rst | 2 +- Documentation/translations/zh_TW/arch/arm64/booting.txt | 4 ++-- Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst | 2 +- Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst | 2 +- Documentation/translations/zh_TW/arch/arm64/index.rst | 2 +- .../translations/zh_TW/arch/arm64/legacy_instructions.txt | 4 ++-- Documentation/translations/zh_TW/arch/arm64/memory.txt | 4 ++-- Documentation/translations/zh_TW/arch/arm64/perf.rst | 2 +- Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt | 4 ++-- Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt | 4 ++-- Documentation/translations/zh_TW/cpu-freq/core.rst | 2 +- Documentation/translations/zh_TW/cpu-freq/cpu-drivers.rst | 2 +- Documentation/translations/zh_TW/cpu-freq/cpufreq-stats.rst | 2 +- Documentation/translations/zh_TW/cpu-freq/index.rst | 2 +- Documentation/translations/zh_TW/disclaimer-zh_TW.rst | 2 +- Documentation/translations/zh_TW/filesystems/debugfs.rst | 4 ++-- Documentation/translations/zh_TW/filesystems/index.rst | 2 +- Documentation/translations/zh_TW/filesystems/sysfs.txt | 2 +- Documentation/translations/zh_TW/filesystems/tmpfs.rst | 2 +- Documentation/translations/zh_TW/filesystems/virtiofs.rst | 2 +- Documentation/translations/zh_TW/gpio.txt | 8 ++++---- Documentation/translations/zh_TW/index.rst | 2 +- Documentation/translations/zh_TW/io_ordering.txt | 8 ++++---- Documentation/translations/zh_TW/process/1.Intro.rst | 2 +- Documentation/translations/zh_TW/process/2.Process.rst | 2 +- Documentation/translations/zh_TW/process/3.Early-stage.rst | 2 +- Documentation/translations/zh_TW/process/4.Coding.rst | 2 +- Documentation/translations/zh_TW/process/5.Posting.rst | 2 +- Documentation/translations/zh_TW/process/6.Followthrough.rst | 2 +- Documentation/translations/zh_TW/process/7.AdvancedTopics.rst | 2 +- Documentation/translations/zh_TW/process/8.Conclusion.rst | 2 +- .../translations/zh_TW/process/code-of-conduct-interpretation.rst | 2 +- Documentation/translations/zh_TW/process/code-of-conduct.rst | 2 +- Documentation/translations/zh_TW/process/coding-style.rst | 2 +- Documentation/translations/zh_TW/process/development-process.rst | 2 +- Documentation/translations/zh_TW/process/email-clients.rst | 2 +- .../translations/zh_TW/process/embargoed-hardware-issues.rst | 2 +- Documentation/translations/zh_TW/process/howto.rst | 2 +- Documentation/translations/zh_TW/process/index.rst | 2 +- .../translations/zh_TW/process/kernel-driver-statement.rst | 2 +- .../translations/zh_TW/process/kernel-enforcement-statement.rst | 2 +- Documentation/translations/zh_TW/process/license-rules.rst | 2 +- Documentation/translations/zh_TW/process/magic-number.rst | 2 +- Documentation/translations/zh_TW/process/management-style.rst | 2 +- Documentation/translations/zh_TW/process/programming-language.rst | 2 +- Documentation/translations/zh_TW/process/stable-api-nonsense.rst | 2 +- Documentation/translations/zh_TW/process/stable-kernel-rules.rst | 2 +- Documentation/translations/zh_TW/process/submit-checklist.rst | 2 +- Documentation/translations/zh_TW/process/submitting-patches.rst | 2 +- .../translations/zh_TW/process/volatile-considered-harmful.rst | 2 +- Documentation/translations/zh_TW/sparse.txt | 6 +++--- MAINTAINERS | 2 +- 65 files changed, 82 insertions(+), 82 deletions(-) (limited to 'MAINTAINERS') diff --git a/Documentation/translations/zh_CN/dev-tools/testing-overview.rst b/Documentation/translations/zh_CN/dev-tools/testing-overview.rst index af65e7e93c02..69e7e4cb2002 100644 --- a/Documentation/translations/zh_CN/dev-tools/testing-overview.rst +++ b/Documentation/translations/zh_CN/dev-tools/testing-overview.rst @@ -3,7 +3,7 @@ .. include:: ../disclaimer-zh_CN.rst :Original: Documentation/dev-tools/testing-overview.rst -:Translator: 胡皓文 Hu Haowen +:Translator: 胡皓文 Hu Haowen ============ 内核测试指南 diff --git a/Documentation/translations/zh_TW/IRQ.txt b/Documentation/translations/zh_TW/IRQ.txt index 73d435a0d1e7..fd78ca720298 100644 --- a/Documentation/translations/zh_TW/IRQ.txt +++ b/Documentation/translations/zh_TW/IRQ.txt @@ -7,7 +7,7 @@ help. Contact the Chinese maintainer if this translation is outdated or if there is a problem with the translation. Maintainer: Eric W. Biederman -Traditional Chinese maintainer: Hu Haowen +Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- Documentation/core-api/irq/index.rst 的繁體中文翻譯 @@ -16,9 +16,9 @@ Documentation/core-api/irq/index.rst 的繁體中文翻譯 者翻譯存在問題，請聯繫繁體中文版維護者。 英文版維護者： Eric W. Biederman -繁體中文版維護者： 胡皓文 Hu Haowen -繁體中文版翻譯者： 胡皓文 Hu Haowen -繁體中文版校譯者： 胡皓文 Hu Haowen +繁體中文版維護者： 胡皓文 Hu Haowen +繁體中文版翻譯者： 胡皓文 Hu Haowen +繁體中文版校譯者： 胡皓文 Hu Haowen 以下爲正文 diff --git a/Documentation/translations/zh_TW/admin-guide/README.rst b/Documentation/translations/zh_TW/admin-guide/README.rst index 6ce97edbab37..7fc56e1e3348 100644 --- a/Documentation/translations/zh_TW/admin-guide/README.rst +++ b/Documentation/translations/zh_TW/admin-guide/README.rst @@ -7,7 +7,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen Linux內核5.x版本 ========================================= diff --git a/Documentation/translations/zh_TW/admin-guide/bug-bisect.rst b/Documentation/translations/zh_TW/admin-guide/bug-bisect.rst index 41a39aebb8d6..b448dbf5ac87 100644 --- a/Documentation/translations/zh_TW/admin-guide/bug-bisect.rst +++ b/Documentation/translations/zh_TW/admin-guide/bug-bisect.rst @@ -7,7 +7,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 二分（bisect）缺陷 +++++++++++++++++++ diff --git a/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst b/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst index 4d813aec77d2..9a3de3bff5e7 100644 --- a/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst +++ b/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst @@ -7,7 +7,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 追蹤缺陷 ========= diff --git a/Documentation/translations/zh_TW/admin-guide/clearing-warn-once.rst b/Documentation/translations/zh_TW/admin-guide/clearing-warn-once.rst index bdc1a22046cf..bd0c08aab8ea 100644 --- a/Documentation/translations/zh_TW/admin-guide/clearing-warn-once.rst +++ b/Documentation/translations/zh_TW/admin-guide/clearing-warn-once.rst @@ -2,7 +2,7 @@ .. include:: ../disclaimer-zh_TW.rst -:Translator: 胡皓文 Hu Haowen +:Translator: 胡皓文 Hu Haowen 清除 WARN_ONCE -------------- diff --git a/Documentation/translations/zh_TW/admin-guide/cpu-load.rst b/Documentation/translations/zh_TW/admin-guide/cpu-load.rst index be087cef1967..9e04aeac1a5c 100644 --- a/Documentation/translations/zh_TW/admin-guide/cpu-load.rst +++ b/Documentation/translations/zh_TW/admin-guide/cpu-load.rst @@ -2,7 +2,7 @@ .. include:: ../disclaimer-zh_TW.rst -:Translator: 胡皓文 Hu Haowen +:Translator: 胡皓文 Hu Haowen ======== CPU 負載 diff --git a/Documentation/translations/zh_TW/admin-guide/index.rst b/Documentation/translations/zh_TW/admin-guide/index.rst index 293c20245783..2804d619201d 100644 --- a/Documentation/translations/zh_TW/admin-guide/index.rst +++ b/Documentation/translations/zh_TW/admin-guide/index.rst @@ -3,7 +3,7 @@ .. include:: ../disclaimer-zh_TW.rst :Original: :doc:`../../../admin-guide/index` -:Translator: 胡皓文 Hu Haowen +:Translator: 胡皓文 Hu Haowen Linux 內核用戶和管理員指南 ========================== diff --git a/Documentation/translations/zh_TW/admin-guide/init.rst b/Documentation/translations/zh_TW/admin-guide/init.rst index 32cdf134948f..db3fdf611080 100644 --- a/Documentation/translations/zh_TW/admin-guide/init.rst +++ b/Documentation/translations/zh_TW/admin-guide/init.rst @@ -7,7 +7,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 解釋「No working init found.」啓動掛起消息 ========================================== diff --git a/Documentation/translations/zh_TW/admin-guide/reporting-issues.rst b/Documentation/translations/zh_TW/admin-guide/reporting-issues.rst index 27638e199f13..ea51342879c0 100644 --- a/Documentation/translations/zh_TW/admin-guide/reporting-issues.rst +++ b/Documentation/translations/zh_TW/admin-guide/reporting-issues.rst @@ -16,7 +16,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 報告問題 diff --git a/Documentation/translations/zh_TW/admin-guide/security-bugs.rst b/Documentation/translations/zh_TW/admin-guide/security-bugs.rst index 15f8e9005071..65c8dd24c96d 100644 --- a/Documentation/translations/zh_TW/admin-guide/security-bugs.rst +++ b/Documentation/translations/zh_TW/admin-guide/security-bugs.rst @@ -7,7 +7,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 安全缺陷 ========= diff --git a/Documentation/translations/zh_TW/admin-guide/tainted-kernels.rst b/Documentation/translations/zh_TW/admin-guide/tainted-kernels.rst index d7b3c4276417..ebe3812ead82 100644 --- a/Documentation/translations/zh_TW/admin-guide/tainted-kernels.rst +++ b/Documentation/translations/zh_TW/admin-guide/tainted-kernels.rst @@ -7,7 +7,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 受汙染的內核 ------------- diff --git a/Documentation/translations/zh_TW/admin-guide/unicode.rst b/Documentation/translations/zh_TW/admin-guide/unicode.rst index 720875be5ef8..7908b369b85b 100644 --- a/Documentation/translations/zh_TW/admin-guide/unicode.rst +++ b/Documentation/translations/zh_TW/admin-guide/unicode.rst @@ -7,7 +7,7 @@ :譯者: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen Unicode（統一碼）支持 ====================== diff --git a/Documentation/translations/zh_TW/arch/arm64/amu.rst b/Documentation/translations/zh_TW/arch/arm64/amu.rst index f947a6c7369f..21ac0db63889 100644 --- a/Documentation/translations/zh_TW/arch/arm64/amu.rst +++ b/Documentation/translations/zh_TW/arch/arm64/amu.rst @@ -5,7 +5,7 @@ :Original: :ref:`Documentation/arch/arm64/amu.rst ` Translator: Bailu Lin - Hu Haowen + Hu Haowen ================================== AArch64 Linux 中擴展的活動監控單元 diff --git a/Documentation/translations/zh_TW/arch/arm64/booting.txt b/Documentation/translations/zh_TW/arch/arm64/booting.txt index 24817b8b70cd..3cc8f593e006 100644 --- a/Documentation/translations/zh_TW/arch/arm64/booting.txt +++ b/Documentation/translations/zh_TW/arch/arm64/booting.txt @@ -10,7 +10,7 @@ or if there is a problem with the translation. M: Will Deacon zh_CN: Fu Wei -zh_TW: Hu Haowen +zh_TW: Hu Haowen C: 55f058e7574c3615dea4615573a19bdb258696c6 --------------------------------------------------------------------- Documentation/arch/arm64/booting.rst 的中文翻譯 @@ -23,7 +23,7 @@ Documentation/arch/arm64/booting.rst 的中文翻譯 中文版維護者： 傅煒 Fu Wei 中文版翻譯者： 傅煒 Fu Wei 中文版校譯者： 傅煒 Fu Wei -繁體中文版校譯者： 胡皓文 Hu Haowen +繁體中文版校譯者： 胡皓文 Hu Haowen 本文翻譯提交時的 Git 檢出點爲： 55f058e7574c3615dea4615573a19bdb258696c6 以下爲正文 diff --git a/Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst b/Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst index fca3c6ff7b93..ca7ff749a67b 100644 --- a/Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst +++ b/Documentation/translations/zh_TW/arch/arm64/elf_hwcaps.rst @@ -5,7 +5,7 @@ :Original: :ref:`Documentation/arch/arm64/elf_hwcaps.rst ` Translator: Bailu Lin - Hu Haowen + Hu Haowen ================ ARM64 ELF hwcaps diff --git a/Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst b/Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst index 10feb329dfb8..a17858c978d6 100644 --- a/Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst +++ b/Documentation/translations/zh_TW/arch/arm64/hugetlbpage.rst @@ -5,7 +5,7 @@ :Original: :ref:`Documentation/arch/arm64/hugetlbpage.rst ` Translator: Bailu Lin - Hu Haowen + Hu Haowen ===================== ARM64中的 HugeTLBpage diff --git a/Documentation/translations/zh_TW/arch/arm64/index.rst b/Documentation/translations/zh_TW/arch/arm64/index.rst index 68befee14b99..a62b5f06b66c 100644 --- a/Documentation/translations/zh_TW/arch/arm64/index.rst +++ b/Documentation/translations/zh_TW/arch/arm64/index.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/arch/arm64/index.rst ` :Translator: Bailu Lin - Hu Haowen + Hu Haowen .. _tw_arm64_index: diff --git a/Documentation/translations/zh_TW/arch/arm64/legacy_instructions.txt b/Documentation/translations/zh_TW/arch/arm64/legacy_instructions.txt index 3c915df9836c..c2d02cd5017d 100644 --- a/Documentation/translations/zh_TW/arch/arm64/legacy_instructions.txt +++ b/Documentation/translations/zh_TW/arch/arm64/legacy_instructions.txt @@ -11,7 +11,7 @@ or if there is a problem with the translation. Maintainer: Punit Agrawal Suzuki K. Poulose Chinese maintainer: Fu Wei -Traditional Chinese maintainer: Hu Haowen +Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- Documentation/arch/arm64/legacy_instructions.rst 的中文翻譯 @@ -26,7 +26,7 @@ Documentation/arch/arm64/legacy_instructions.rst 的中文翻譯 中文版維護者： 傅煒 Fu Wei 中文版翻譯者： 傅煒 Fu Wei 中文版校譯者： 傅煒 Fu Wei -繁體中文版校譯者：胡皓文 Hu Haowen +繁體中文版校譯者：胡皓文 Hu Haowen 以下爲正文 --------------------------------------------------------------------- diff --git a/Documentation/translations/zh_TW/arch/arm64/memory.txt b/Documentation/translations/zh_TW/arch/arm64/memory.txt index 2437380a26d8..0280200e791f 100644 --- a/Documentation/translations/zh_TW/arch/arm64/memory.txt +++ b/Documentation/translations/zh_TW/arch/arm64/memory.txt @@ -10,7 +10,7 @@ or if there is a problem with the translation. Maintainer: Catalin Marinas Chinese maintainer: Fu Wei -Traditional Chinese maintainer: Hu Haowen +Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- Documentation/arch/arm64/memory.rst 的中文翻譯 @@ -24,7 +24,7 @@ Documentation/arch/arm64/memory.rst 的中文翻譯 中文版維護者： 傅煒 Fu Wei 中文版翻譯者： 傅煒 Fu Wei 中文版校譯者： 傅煒 Fu Wei -繁體中文版校譯者： 胡皓文 Hu Haowen +繁體中文版校譯者： 胡皓文 Hu Haowen 以下爲正文 --------------------------------------------------------------------- diff --git a/Documentation/translations/zh_TW/arch/arm64/perf.rst b/Documentation/translations/zh_TW/arch/arm64/perf.rst index 3b39997a52eb..645f3944a0f4 100644 --- a/Documentation/translations/zh_TW/arch/arm64/perf.rst +++ b/Documentation/translations/zh_TW/arch/arm64/perf.rst @@ -5,7 +5,7 @@ :Original: :ref:`Documentation/arch/arm64/perf.rst ` Translator: Bailu Lin - Hu Haowen + Hu Haowen ============= Perf 事件屬性 diff --git a/Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt b/Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt index 66c3a3506458..f6f41835a54a 100644 --- a/Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt +++ b/Documentation/translations/zh_TW/arch/arm64/silicon-errata.txt @@ -10,7 +10,7 @@ or if there is a problem with the translation. M: Will Deacon zh_CN: Fu Wei -zh_TW: Hu Haowen +zh_TW: Hu Haowen C: 1926e54f115725a9248d0c4c65c22acaf94de4c4 --------------------------------------------------------------------- Documentation/arch/arm64/silicon-errata.rst 的中文翻譯 @@ -23,7 +23,7 @@ Documentation/arch/arm64/silicon-errata.rst 的中文翻譯 中文版維護者： 傅煒 Fu Wei 中文版翻譯者： 傅煒 Fu Wei 中文版校譯者： 傅煒 Fu Wei -繁體中文版校譯者： 胡皓文 Hu Haowen +繁體中文版校譯者： 胡皓文 Hu Haowen 本文翻譯提交時的 Git 檢出點爲： 1926e54f115725a9248d0c4c65c22acaf94de4c4 以下爲正文 diff --git a/Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt b/Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt index b7f683f20ed1..c0be1d1e0d01 100644 --- a/Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt +++ b/Documentation/translations/zh_TW/arch/arm64/tagged-pointers.txt @@ -10,7 +10,7 @@ or if there is a problem with the translation. Maintainer: Will Deacon Chinese maintainer: Fu Wei -Traditional Chinese maintainer: Hu Haowen +Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- Documentation/arch/arm64/tagged-pointers.rst 的中文翻譯 @@ -22,7 +22,7 @@ Documentation/arch/arm64/tagged-pointers.rst 的中文翻譯 中文版維護者： 傅煒 Fu Wei 中文版翻譯者： 傅煒 Fu Wei 中文版校譯者： 傅煒 Fu Wei -繁體中文版校譯者： 胡皓文 Hu Haowen +繁體中文版校譯者： 胡皓文 Hu Haowen 以下爲正文 --------------------------------------------------------------------- diff --git a/Documentation/translations/zh_TW/cpu-freq/core.rst b/Documentation/translations/zh_TW/cpu-freq/core.rst index 3d890c2f2a61..f1951e1b23bb 100644 --- a/Documentation/translations/zh_TW/cpu-freq/core.rst +++ b/Documentation/translations/zh_TW/cpu-freq/core.rst @@ -4,7 +4,7 @@ :Original: :doc:`../../../cpu-freq/core` :Translator: Yanteng Si - Hu Haowen + Hu Haowen .. _tw_core.rst: diff --git a/Documentation/translations/zh_TW/cpu-freq/cpu-drivers.rst b/Documentation/translations/zh_TW/cpu-freq/cpu-drivers.rst index 2bb8197cd320..671b1bf0e2c5 100644 --- a/Documentation/translations/zh_TW/cpu-freq/cpu-drivers.rst +++ b/Documentation/translations/zh_TW/cpu-freq/cpu-drivers.rst @@ -4,7 +4,7 @@ :Original: :doc:`../../../cpu-freq/cpu-drivers` :Translator: Yanteng Si - Hu Haowen + Hu Haowen .. _tw_cpu-drivers.rst: diff --git a/Documentation/translations/zh_TW/cpu-freq/cpufreq-stats.rst b/Documentation/translations/zh_TW/cpu-freq/cpufreq-stats.rst index d80bfed50e8c..49088becd5fa 100644 --- a/Documentation/translations/zh_TW/cpu-freq/cpufreq-stats.rst +++ b/Documentation/translations/zh_TW/cpu-freq/cpufreq-stats.rst @@ -4,7 +4,7 @@ :Original: :doc:`../../../cpu-freq/cpufreq-stats` :Translator: Yanteng Si - Hu Haowen + Hu Haowen .. _tw_cpufreq-stats.rst: diff --git a/Documentation/translations/zh_TW/cpu-freq/index.rst b/Documentation/translations/zh_TW/cpu-freq/index.rst index 1a8e680f95ed..c6cf825b57a5 100644 --- a/Documentation/translations/zh_TW/cpu-freq/index.rst +++ b/Documentation/translations/zh_TW/cpu-freq/index.rst @@ -4,7 +4,7 @@ :Original: :doc:`../../../cpu-freq/index` :Translator: Yanteng Si - Hu Haowen + Hu Haowen .. _tw_index.rst: diff --git a/Documentation/translations/zh_TW/disclaimer-zh_TW.rst b/Documentation/translations/zh_TW/disclaimer-zh_TW.rst index f4cf87d03dc5..0d0ffb1ca4e8 100644 --- a/Documentation/translations/zh_TW/disclaimer-zh_TW.rst +++ b/Documentation/translations/zh_TW/disclaimer-zh_TW.rst @@ -7,5 +7,5 @@ .. note:: 如果您發現本文檔與原始文件有任何不同或者有翻譯問題，請聯繫該文件的譯者， - 或者發送電子郵件給胡皓文以獲取幫助：。 + 或者發送電子郵件給胡皓文以獲取幫助：。 diff --git a/Documentation/translations/zh_TW/filesystems/debugfs.rst b/Documentation/translations/zh_TW/filesystems/debugfs.rst index 270dd94fddf1..ddf801943c92 100644 --- a/Documentation/translations/zh_TW/filesystems/debugfs.rst +++ b/Documentation/translations/zh_TW/filesystems/debugfs.rst @@ -14,12 +14,12 @@ Debugfs 中文版維護者：羅楚成 Chucheng Luo 中文版翻譯者：羅楚成 Chucheng Luo 中文版校譯者: 羅楚成 Chucheng Luo - 繁體中文版校譯者: 胡皓文 Hu Haowen + 繁體中文版校譯者: 胡皓文 Hu Haowen 版權所有2020 羅楚成 -版權所有2021 胡皓文 Hu Haowen +版權所有2021 胡皓文 Hu Haowen Debugfs是內核開發人員在用戶空間獲取信息的簡單方法。與/proc不同，proc只提供進程 diff --git a/Documentation/translations/zh_TW/filesystems/index.rst b/Documentation/translations/zh_TW/filesystems/index.rst index 4e5dde0dca3c..789e742fa3c5 100644 --- a/Documentation/translations/zh_TW/filesystems/index.rst +++ b/Documentation/translations/zh_TW/filesystems/index.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/filesystems/index.rst ` :Translator: Wang Wenhu - Hu Haowen + Hu Haowen .. _tw_filesystems_index: diff --git a/Documentation/translations/zh_TW/filesystems/sysfs.txt b/Documentation/translations/zh_TW/filesystems/sysfs.txt index 280824cc7e5d..a84eba2af9d3 100644 --- a/Documentation/translations/zh_TW/filesystems/sysfs.txt +++ b/Documentation/translations/zh_TW/filesystems/sysfs.txt @@ -22,7 +22,7 @@ Documentation/filesystems/sysfs.rst 的中文翻譯 中文版維護者： 傅煒 Fu Wei 中文版翻譯者： 傅煒 Fu Wei 中文版校譯者： 傅煒 Fu Wei -繁體中文版校譯者：胡皓文 Hu Haowen +繁體中文版校譯者：胡皓文 Hu Haowen 以下爲正文 diff --git a/Documentation/translations/zh_TW/filesystems/tmpfs.rst b/Documentation/translations/zh_TW/filesystems/tmpfs.rst index 8d753a34785b..2c8439b2b77e 100644 --- a/Documentation/translations/zh_TW/filesystems/tmpfs.rst +++ b/Documentation/translations/zh_TW/filesystems/tmpfs.rst @@ -5,7 +5,7 @@ :Original: Documentation/filesystems/tmpfs.rst Translated by Wang Qing -and Hu Haowen +and Hu Haowen ===== Tmpfs diff --git a/Documentation/translations/zh_TW/filesystems/virtiofs.rst b/Documentation/translations/zh_TW/filesystems/virtiofs.rst index 2b05e84375dd..086fce5839dd 100644 --- a/Documentation/translations/zh_TW/filesystems/virtiofs.rst +++ b/Documentation/translations/zh_TW/filesystems/virtiofs.rst @@ -11,7 +11,7 @@ 中文版翻譯者： 王文虎 Wang Wenhu 中文版校譯者： 王文虎 Wang Wenhu 中文版校譯者： 王文虎 Wang Wenhu - 繁體中文版校譯者：胡皓文 Hu Haowen + 繁體中文版校譯者：胡皓文 Hu Haowen =========================================== virtiofs: virtio-fs 主機<->客機共享文件系統 diff --git a/Documentation/translations/zh_TW/gpio.txt b/Documentation/translations/zh_TW/gpio.txt index b93788a2628b..555e4b11a5c7 100644 --- a/Documentation/translations/zh_TW/gpio.txt +++ b/Documentation/translations/zh_TW/gpio.txt @@ -8,7 +8,7 @@ or if there is a problem with the translation. Maintainer: Grant Likely Linus Walleij -Traditional Chinese maintainer: Hu Haowen +Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- Documentation/admin-guide/gpio 的繁體中文翻譯 @@ -18,9 +18,9 @@ Documentation/admin-guide/gpio 的繁體中文翻譯 英文版維護者： Grant Likely Linus Walleij -繁體中文版維護者： 胡皓文 Hu Haowen -繁體中文版翻譯者： 胡皓文 Hu Haowen -繁體中文版校譯者： 胡皓文 Hu Haowen +繁體中文版維護者： 胡皓文 Hu Haowen +繁體中文版翻譯者： 胡皓文 Hu Haowen +繁體中文版校譯者： 胡皓文 Hu Haowen 以下爲正文 --------------------------------------------------------------------- diff --git a/Documentation/translations/zh_TW/index.rst b/Documentation/translations/zh_TW/index.rst index e7c83868e780..5e7e3b117b42 100644 --- a/Documentation/translations/zh_TW/index.rst +++ b/Documentation/translations/zh_TW/index.rst @@ -15,7 +15,7 @@ .. note:: 內核文檔繁體中文版的翻譯工作正在進行中。如果您願意並且有時間參與這項工 - 作，歡迎提交補丁給胡皓文 。 + 作，歡迎提交補丁給胡皓文 。 許可證文檔 ---------- diff --git a/Documentation/translations/zh_TW/io_ordering.txt b/Documentation/translations/zh_TW/io_ordering.txt index 1e99206c8421..03f86840c139 100644 --- a/Documentation/translations/zh_TW/io_ordering.txt +++ b/Documentation/translations/zh_TW/io_ordering.txt @@ -6,7 +6,7 @@ communicating in English you can also ask the Chinese maintainer for help. Contact the Chinese maintainer if this translation is outdated or if there is a problem with the translation. -Traditional Chinese maintainer: Hu Haowen +Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- Documentation/driver-api/io_ordering.rst 的繁體中文翻譯 @@ -14,9 +14,9 @@ Documentation/driver-api/io_ordering.rst 的繁體中文翻譯 交流有困難的話，也可以向繁體中文版維護者求助。如果本翻譯更新不及時或 者翻譯存在問題，請聯繫繁體中文版維護者。 -繁體中文版維護者： 胡皓文 Hu Haowen -繁體中文版翻譯者： 胡皓文 Hu Haowen -繁體中文版校譯者： 胡皓文 Hu Haowen +繁體中文版維護者： 胡皓文 Hu Haowen +繁體中文版翻譯者： 胡皓文 Hu Haowen +繁體中文版校譯者： 胡皓文 Hu Haowen 以下爲正文 diff --git a/Documentation/translations/zh_TW/process/1.Intro.rst b/Documentation/translations/zh_TW/process/1.Intro.rst index ca2b931be6c5..f236fe95a6c6 100644 --- a/Documentation/translations/zh_TW/process/1.Intro.rst +++ b/Documentation/translations/zh_TW/process/1.Intro.rst @@ -11,7 +11,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_process_intro: diff --git a/Documentation/translations/zh_TW/process/2.Process.rst b/Documentation/translations/zh_TW/process/2.Process.rst index 9d465df1f6c3..17bb4e07d171 100644 --- a/Documentation/translations/zh_TW/process/2.Process.rst +++ b/Documentation/translations/zh_TW/process/2.Process.rst @@ -11,7 +11,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_process: diff --git a/Documentation/translations/zh_TW/process/3.Early-stage.rst b/Documentation/translations/zh_TW/process/3.Early-stage.rst index 076873ca0905..636e506fd196 100644 --- a/Documentation/translations/zh_TW/process/3.Early-stage.rst +++ b/Documentation/translations/zh_TW/process/3.Early-stage.rst @@ -11,7 +11,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_early_stage: diff --git a/Documentation/translations/zh_TW/process/4.Coding.rst b/Documentation/translations/zh_TW/process/4.Coding.rst index 7fc0344ed16b..adb5339aab6a 100644 --- a/Documentation/translations/zh_TW/process/4.Coding.rst +++ b/Documentation/translations/zh_TW/process/4.Coding.rst @@ -11,7 +11,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_coding: diff --git a/Documentation/translations/zh_TW/process/5.Posting.rst b/Documentation/translations/zh_TW/process/5.Posting.rst index 280a8832ecc0..27015622ad63 100644 --- a/Documentation/translations/zh_TW/process/5.Posting.rst +++ b/Documentation/translations/zh_TW/process/5.Posting.rst @@ -11,7 +11,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_posting: diff --git a/Documentation/translations/zh_TW/process/6.Followthrough.rst b/Documentation/translations/zh_TW/process/6.Followthrough.rst index 4af782742db3..5073b6e77c1c 100644 --- a/Documentation/translations/zh_TW/process/6.Followthrough.rst +++ b/Documentation/translations/zh_TW/process/6.Followthrough.rst @@ -11,7 +11,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_followthrough: diff --git a/Documentation/translations/zh_TW/process/7.AdvancedTopics.rst b/Documentation/translations/zh_TW/process/7.AdvancedTopics.rst index 4fbc104a37ca..2cbd16bfed29 100644 --- a/Documentation/translations/zh_TW/process/7.AdvancedTopics.rst +++ b/Documentation/translations/zh_TW/process/7.AdvancedTopics.rst @@ -11,7 +11,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_advancedtopics: diff --git a/Documentation/translations/zh_TW/process/8.Conclusion.rst b/Documentation/translations/zh_TW/process/8.Conclusion.rst index 044fcc118bef..1207991d1570 100644 --- a/Documentation/translations/zh_TW/process/8.Conclusion.rst +++ b/Documentation/translations/zh_TW/process/8.Conclusion.rst @@ -10,7 +10,7 @@ :校譯: 吳想成 Wu XiangCheng - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen .. _tw_development_conclusion: diff --git a/Documentation/translations/zh_TW/process/code-of-conduct-interpretation.rst b/Documentation/translations/zh_TW/process/code-of-conduct-interpretation.rst index 949d831aaf6c..920bb0f36974 100644 --- a/Documentation/translations/zh_TW/process/code-of-conduct-interpretation.rst +++ b/Documentation/translations/zh_TW/process/code-of-conduct-interpretation.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/process/code-of-conduct-interpretation.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_code_of_conduct_interpretation: diff --git a/Documentation/translations/zh_TW/process/code-of-conduct.rst b/Documentation/translations/zh_TW/process/code-of-conduct.rst index 716e5843b6e9..e3087112f0bc 100644 --- a/Documentation/translations/zh_TW/process/code-of-conduct.rst +++ b/Documentation/translations/zh_TW/process/code-of-conduct.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/process/code-of-conduct.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_code_of_conduct: diff --git a/Documentation/translations/zh_TW/process/coding-style.rst b/Documentation/translations/zh_TW/process/coding-style.rst index 61e614aad6a7..83862e4d3b64 100644 --- a/Documentation/translations/zh_TW/process/coding-style.rst +++ b/Documentation/translations/zh_TW/process/coding-style.rst @@ -15,7 +15,7 @@ 管旭東 Xudong Guan Li Zefan Wang Chen - Hu Haowen + Hu Haowen Linux 內核代碼風格 ========================= diff --git a/Documentation/translations/zh_TW/process/development-process.rst b/Documentation/translations/zh_TW/process/development-process.rst index 45e6385647cd..f4cf5c2bbc82 100644 --- a/Documentation/translations/zh_TW/process/development-process.rst +++ b/Documentation/translations/zh_TW/process/development-process.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/process/development-process.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_development_process_main: diff --git a/Documentation/translations/zh_TW/process/email-clients.rst b/Documentation/translations/zh_TW/process/email-clients.rst index 4ba543d06f3b..ae63e41d9cee 100644 --- a/Documentation/translations/zh_TW/process/email-clients.rst +++ b/Documentation/translations/zh_TW/process/email-clients.rst @@ -14,7 +14,7 @@ 中文版校譯者： Yinglin Luan Xiaochen Wang yaxinsn - Hu Haowen + Hu Haowen Linux郵件客戶端配置信息 ======================= diff --git a/Documentation/translations/zh_TW/process/embargoed-hardware-issues.rst b/Documentation/translations/zh_TW/process/embargoed-hardware-issues.rst index fbde3e26eda5..8e4db8baa0d1 100644 --- a/Documentation/translations/zh_TW/process/embargoed-hardware-issues.rst +++ b/Documentation/translations/zh_TW/process/embargoed-hardware-issues.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/process/embargoed-hardware-issues.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen 被限制的硬體問題 ================ diff --git a/Documentation/translations/zh_TW/process/howto.rst b/Documentation/translations/zh_TW/process/howto.rst index ea2f468d3e58..306f5b77b4b8 100644 --- a/Documentation/translations/zh_TW/process/howto.rst +++ b/Documentation/translations/zh_TW/process/howto.rst @@ -16,7 +16,7 @@ 鍾宇 TripleX Chung 陳琦 Maggie Chen 王聰 Wang Cong - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 如何參與Linux內核開發 ===================== diff --git a/Documentation/translations/zh_TW/process/index.rst b/Documentation/translations/zh_TW/process/index.rst index c5c59b4fd595..d742642dab01 100644 --- a/Documentation/translations/zh_TW/process/index.rst +++ b/Documentation/translations/zh_TW/process/index.rst @@ -9,7 +9,7 @@ :Original: :ref:`Documentation/process/index.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_process_index: diff --git a/Documentation/translations/zh_TW/process/kernel-driver-statement.rst b/Documentation/translations/zh_TW/process/kernel-driver-statement.rst index 8f225379b12c..963ecece3db1 100644 --- a/Documentation/translations/zh_TW/process/kernel-driver-statement.rst +++ b/Documentation/translations/zh_TW/process/kernel-driver-statement.rst @@ -6,7 +6,7 @@ :Original: :ref:`Documentation/process/kernel-driver-statement.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen 內核驅動聲明 ------------ diff --git a/Documentation/translations/zh_TW/process/kernel-enforcement-statement.rst b/Documentation/translations/zh_TW/process/kernel-enforcement-statement.rst index 99e21d22800d..2861f4a15721 100644 --- a/Documentation/translations/zh_TW/process/kernel-enforcement-statement.rst +++ b/Documentation/translations/zh_TW/process/kernel-enforcement-statement.rst @@ -6,7 +6,7 @@ :Original: :ref:`Documentation/process/kernel-enforcement-statement.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen Linux 內核執行聲明 ------------------ diff --git a/Documentation/translations/zh_TW/process/license-rules.rst b/Documentation/translations/zh_TW/process/license-rules.rst index ad2b80f97123..503b6701bde4 100644 --- a/Documentation/translations/zh_TW/process/license-rules.rst +++ b/Documentation/translations/zh_TW/process/license-rules.rst @@ -6,7 +6,7 @@ :Original: :ref:`Documentation/process/license-rules.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_kernel_licensing: diff --git a/Documentation/translations/zh_TW/process/magic-number.rst b/Documentation/translations/zh_TW/process/magic-number.rst index c9e3db12c3f9..5657d5cd18d4 100644 --- a/Documentation/translations/zh_TW/process/magic-number.rst +++ b/Documentation/translations/zh_TW/process/magic-number.rst @@ -12,7 +12,7 @@ 中文版維護者： 賈威威 Jia Wei Wei 中文版翻譯者： 賈威威 Jia Wei Wei 中文版校譯者： 賈威威 Jia Wei Wei - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen Linux 魔術數 ============ diff --git a/Documentation/translations/zh_TW/process/management-style.rst b/Documentation/translations/zh_TW/process/management-style.rst index dce248470063..e9d29024f4c9 100644 --- a/Documentation/translations/zh_TW/process/management-style.rst +++ b/Documentation/translations/zh_TW/process/management-style.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/process/management-style.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_managementstyle: diff --git a/Documentation/translations/zh_TW/process/programming-language.rst b/Documentation/translations/zh_TW/process/programming-language.rst index 144bdaf81a41..e33389676eed 100644 --- a/Documentation/translations/zh_TW/process/programming-language.rst +++ b/Documentation/translations/zh_TW/process/programming-language.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/process/programming-language.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_programming_language: diff --git a/Documentation/translations/zh_TW/process/stable-api-nonsense.rst b/Documentation/translations/zh_TW/process/stable-api-nonsense.rst index 22caa5b8d422..33fc85c2cc51 100644 --- a/Documentation/translations/zh_TW/process/stable-api-nonsense.rst +++ b/Documentation/translations/zh_TW/process/stable-api-nonsense.rst @@ -12,7 +12,7 @@ 中文版維護者： 鍾宇 TripleX Chung 中文版翻譯者： 鍾宇 TripleX Chung 中文版校譯者： 李陽 Li Yang - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen Linux 內核驅動接口 ================== diff --git a/Documentation/translations/zh_TW/process/stable-kernel-rules.rst b/Documentation/translations/zh_TW/process/stable-kernel-rules.rst index 9bb0d9b4f3ac..29d9a70a1868 100644 --- a/Documentation/translations/zh_TW/process/stable-kernel-rules.rst +++ b/Documentation/translations/zh_TW/process/stable-kernel-rules.rst @@ -15,7 +15,7 @@ 中文版校譯者： - 李陽 Li Yang - Kangkai Yin - - 胡皓文 Hu Haowen + - 胡皓文 Hu Haowen 所有你想知道的事情 - 關於linux穩定版發布 ======================================== diff --git a/Documentation/translations/zh_TW/process/submit-checklist.rst b/Documentation/translations/zh_TW/process/submit-checklist.rst index ff2f89cba83f..12bf6f5ca5c6 100644 --- a/Documentation/translations/zh_TW/process/submit-checklist.rst +++ b/Documentation/translations/zh_TW/process/submit-checklist.rst @@ -4,7 +4,7 @@ :Original: :ref:`Documentation/process/submit-checklist.rst ` :Translator: Alex Shi - Hu Haowen + Hu Haowen .. _tw_submitchecklist: diff --git a/Documentation/translations/zh_TW/process/submitting-patches.rst b/Documentation/translations/zh_TW/process/submitting-patches.rst index 3f77ef5d48a0..0746809c31a2 100644 --- a/Documentation/translations/zh_TW/process/submitting-patches.rst +++ b/Documentation/translations/zh_TW/process/submitting-patches.rst @@ -13,7 +13,7 @@ 時奎亮 Alex Shi 中文版校譯者： 李陽 Li Yang 王聰 Wang Cong - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 如何讓你的改動進入內核 diff --git a/Documentation/translations/zh_TW/process/volatile-considered-harmful.rst b/Documentation/translations/zh_TW/process/volatile-considered-harmful.rst index 097fe80352cb..469cb5b3a07c 100644 --- a/Documentation/translations/zh_TW/process/volatile-considered-harmful.rst +++ b/Documentation/translations/zh_TW/process/volatile-considered-harmful.rst @@ -17,7 +17,7 @@ 中文版校譯者： 張漢輝 Eugene Teo 楊瑞 Dave Young 時奎亮 Alex Shi - 胡皓文 Hu Haowen + 胡皓文 Hu Haowen 爲什麼不應該使用「volatile」類型 ================================ diff --git a/Documentation/translations/zh_TW/sparse.txt b/Documentation/translations/zh_TW/sparse.txt index c9acb2c926cb..56fb17fd1359 100644 --- a/Documentation/translations/zh_TW/sparse.txt +++ b/Documentation/translations/zh_TW/sparse.txt @@ -6,7 +6,7 @@ communicating in English you can also ask the Chinese maintainer for help. Contact the Chinese maintainer if this translation is outdated or if there is a problem with the translation. -Traditional Chinese maintainer: Hu Haowen +Traditional Chinese maintainer: Hu Haowen --------------------------------------------------------------------- Documentation/dev-tools/sparse.rst 的繁體中文翻譯 @@ -14,8 +14,8 @@ Documentation/dev-tools/sparse.rst 的繁體中文翻譯 交流有困難的話，也可以向繁體中文版維護者求助。如果本翻譯更新不及時或 者翻譯存在問題，請聯繫繁體中文版維護者。 -繁體中文版維護者： 胡皓文 Hu Haowen -繁體中文版翻譯者： 胡皓文 Hu Haowen +繁體中文版維護者： 胡皓文 Hu Haowen +繁體中文版翻譯者： 胡皓文 Hu Haowen 以下爲正文 --------------------------------------------------------------------- diff --git a/MAINTAINERS b/MAINTAINERS index fff7e50948b6..16e9088c0c8f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21619,7 +21619,7 @@ F: kernel/trace/trace_osnoise.c F: kernel/trace/trace_sched_wakeup.c TRADITIONAL CHINESE DOCUMENTATION -M: Hu Haowen +M: Hu Haowen L: linux-doc-tw-discuss@lists.sourceforge.net (moderated for non-subscribers) S: Maintained W: https://github.com/srcres258/linux-doc -- cgit v1.2.3 From afcca9b9ce4e88fe3d002c633efaaafc60d30009 Mon Sep 17 00:00:00 2001 From: Hu Haowen Date: Thu, 20 Jul 2023 22:18:46 +0800 Subject: docs/zh_TW: remove the mailing list entry for zh_TW Due to some reasons the current mailing list will be revoked and new one will replace it in the future, hence remove the entry from MAINTAINERS ahead of time. Signed-off-by: Hu Haowen Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20230720141846.1787-1-src.res.211@gmail.com --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index 16e9088c0c8f..66582e300406 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21620,7 +21620,6 @@ F: kernel/trace/trace_sched_wakeup.c TRADITIONAL CHINESE DOCUMENTATION M: Hu Haowen -L: linux-doc-tw-discuss@lists.sourceforge.net (moderated for non-subscribers) S: Maintained W: https://github.com/srcres258/linux-doc T: git git://github.com/srcres258/linux-doc.git doc-zh-tw -- cgit v1.2.3 From 51712e49b434950b6317188f88696556c277b10d Mon Sep 17 00:00:00 2001 From: Costa Shulyupin Date: Mon, 17 Jul 2023 22:24:27 +0300 Subject: docs: move loongarch under arch and fix all in-tree references. Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Signed-off-by: Costa Shulyupin Acked-by: Huacai Chen Reviewed-by: Yanteng Si Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20230717192456.453124-1-costa.shul@redhat.com --- Documentation/arch/index.rst | 2 +- Documentation/arch/loongarch/booting.rst | 42 +++ Documentation/arch/loongarch/features.rst | 3 + Documentation/arch/loongarch/index.rst | 22 ++ Documentation/arch/loongarch/introduction.rst | 390 +++++++++++++++++++++ Documentation/arch/loongarch/irq-chip-model.rst | 160 +++++++++ Documentation/loongarch/booting.rst | 42 --- Documentation/loongarch/features.rst | 3 - Documentation/loongarch/index.rst | 22 -- Documentation/loongarch/introduction.rst | 390 --------------------- Documentation/loongarch/irq-chip-model.rst | 160 --------- Documentation/translations/zh_CN/arch/index.rst | 2 +- .../translations/zh_CN/arch/loongarch/booting.rst | 48 +++ .../translations/zh_CN/arch/loongarch/features.rst | 8 + .../translations/zh_CN/arch/loongarch/index.rst | 27 ++ .../zh_CN/arch/loongarch/introduction.rst | 353 +++++++++++++++++++ .../zh_CN/arch/loongarch/irq-chip-model.rst | 157 +++++++++ .../translations/zh_CN/loongarch/booting.rst | 48 --- .../translations/zh_CN/loongarch/features.rst | 8 - .../translations/zh_CN/loongarch/index.rst | 27 -- .../translations/zh_CN/loongarch/introduction.rst | 353 ------------------- .../zh_CN/loongarch/irq-chip-model.rst | 157 --------- MAINTAINERS | 4 +- drivers/irqchip/Kconfig | 2 +- 24 files changed, 1215 insertions(+), 1215 deletions(-) create mode 100644 Documentation/arch/loongarch/booting.rst create mode 100644 Documentation/arch/loongarch/features.rst create mode 100644 Documentation/arch/loongarch/index.rst create mode 100644 Documentation/arch/loongarch/introduction.rst create mode 100644 Documentation/arch/loongarch/irq-chip-model.rst delete mode 100644 Documentation/loongarch/booting.rst delete mode 100644 Documentation/loongarch/features.rst delete mode 100644 Documentation/loongarch/index.rst delete mode 100644 Documentation/loongarch/introduction.rst delete mode 100644 Documentation/loongarch/irq-chip-model.rst create mode 100644 Documentation/translations/zh_CN/arch/loongarch/booting.rst create mode 100644 Documentation/translations/zh_CN/arch/loongarch/features.rst create mode 100644 Documentation/translations/zh_CN/arch/loongarch/index.rst create mode 100644 Documentation/translations/zh_CN/arch/loongarch/introduction.rst create mode 100644 Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst delete mode 100644 Documentation/translations/zh_CN/loongarch/booting.rst delete mode 100644 Documentation/translations/zh_CN/loongarch/features.rst delete mode 100644 Documentation/translations/zh_CN/loongarch/index.rst delete mode 100644 Documentation/translations/zh_CN/loongarch/introduction.rst delete mode 100644 Documentation/translations/zh_CN/loongarch/irq-chip-model.rst (limited to 'MAINTAINERS') diff --git a/Documentation/arch/index.rst b/Documentation/arch/index.rst index 8458b88e9b79..4b6b1beebad6 100644 --- a/Documentation/arch/index.rst +++ b/Documentation/arch/index.rst @@ -13,7 +13,7 @@ implementation. arm/index arm64/index ia64/index - ../loongarch/index + loongarch/index m68k/index ../mips/index nios2/index diff --git a/Documentation/arch/loongarch/booting.rst b/Documentation/arch/loongarch/booting.rst new file mode 100644 index 000000000000..91eccd410478 --- /dev/null +++ b/Documentation/arch/loongarch/booting.rst @@ -0,0 +1,42 @@ +.. SPDX-License-Identifier: GPL-2.0 + +======================= +Booting Linux/LoongArch +======================= + +:Author: Yanteng Si +:Date: 18 Nov 2022 + +Information passed from BootLoader to kernel +============================================ + +LoongArch supports ACPI and FDT. The information that needs to be passed +to the kernel includes the memmap, the initrd, the command line, optionally +the ACPI/FDT tables, and so on. + +The kernel is passed the following arguments on `kernel_entry` : + + - a0 = efi_boot: `efi_boot` is a flag indicating whether + this boot environment is fully UEFI-compliant. + + - a1 = cmdline: `cmdline` is a pointer to the kernel command line. + + - a2 = systemtable: `systemtable` points to the EFI system table. + All pointers involved at this stage are in physical addresses. + +Header of Linux/LoongArch kernel images +======================================= + +Linux/LoongArch kernel images are EFI images. Being PE files, they have +a 64-byte header structured like:: + + u32 MZ_MAGIC /* "MZ", MS-DOS header */ + u32 res0 = 0 /* Reserved */ + u64 kernel_entry /* Kernel entry point */ + u64 _end - _text /* Kernel image effective size */ + u64 load_offset /* Kernel image load offset from start of RAM */ + u64 res1 = 0 /* Reserved */ + u64 res2 = 0 /* Reserved */ + u64 res3 = 0 /* Reserved */ + u32 LINUX_PE_MAGIC /* Magic number */ + u32 pe_header - _head /* Offset to the PE header */ diff --git a/Documentation/arch/loongarch/features.rst b/Documentation/arch/loongarch/features.rst new file mode 100644 index 000000000000..ebacade3ea45 --- /dev/null +++ b/Documentation/arch/loongarch/features.rst @@ -0,0 +1,3 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. kernel-feat:: $srctree/Documentation/features loongarch diff --git a/Documentation/arch/loongarch/index.rst b/Documentation/arch/loongarch/index.rst new file mode 100644 index 000000000000..c779bfa00c05 --- /dev/null +++ b/Documentation/arch/loongarch/index.rst @@ -0,0 +1,22 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================== +LoongArch Architecture +====================== + +.. toctree:: + :maxdepth: 2 + :numbered: + + introduction + booting + irq-chip-model + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/arch/loongarch/introduction.rst b/Documentation/arch/loongarch/introduction.rst new file mode 100644 index 000000000000..49135d451ced --- /dev/null +++ b/Documentation/arch/loongarch/introduction.rst @@ -0,0 +1,390 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================= +Introduction to LoongArch +========================= + +LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are +currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit +version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels +(PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0 +while applications run at PLV3. This document introduces the registers, basic +instruction set, virtual memory and some other topics of LoongArch. + +Registers +========= + +LoongArch registers include general purpose registers (GPRs), floating point +registers (FPRs), vector registers (VRs) and control status registers (CSRs) +used in privileged mode (PLV0). + +GPRs +---- + +LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32 +and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers +are not architecturally special. (Except ``$r1``, which is hard-wired as the +link register of the BL instruction.) + +The kernel uses a variant of the LoongArch register convention, as described in +the LoongArch ELF psABI spec, in :ref:`References `: + +================= =============== =================== ============ +Name Alias Usage Preserved + across calls +================= =============== =================== ============ +``$r0`` ``$zero`` Constant zero Unused +``$r1`` ``$ra`` Return address No +``$r2`` ``$tp`` TLS/Thread pointer Unused +``$r3`` ``$sp`` Stack pointer Yes +``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No +``$r4``-``$r5`` ``$v0``-``$v1`` Return value No +``$r12``-``$r20`` ``$t0``-``$t8`` Temp registers No +``$r21`` ``$u0`` Percpu base address Unused +``$r22`` ``$fp`` Frame pointer Yes +``$r23``-``$r31`` ``$s0``-``$s8`` Static registers Yes +================= =============== =================== ============ + +.. Note:: + The register ``$r21`` is reserved in the ELF psABI, but used by the Linux + kernel for storing the percpu base address. It normally has no ABI name, + but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1`` + in some old code,however they are deprecated aliases of ``$a0`` and ``$a1`` + respectively. + +FPRs +---- + +LoongArch has 32 FPRs ( ``$f0`` ~ ``$f31`` ) when FPU is present. Each one is +64-bit wide on the LA64 cores. + +The floating-point register convention is the same as described in the +LoongArch ELF psABI spec: + +================= ================== =================== ============ +Name Alias Usage Preserved + across calls +================= ================== =================== ============ +``$f0``-``$f7`` ``$fa0``-``$fa7`` Argument registers No +``$f0``-``$f1`` ``$fv0``-``$fv1`` Return value No +``$f8``-``$f23`` ``$ft0``-``$ft15`` Temp registers No +``$f24``-``$f31`` ``$fs0``-``$fs7`` Static registers Yes +================= ================== =================== ============ + +.. Note:: + You may see ``$fv0`` or ``$fv1`` in some old code, however they are + deprecated aliases of ``$fa0`` and ``$fa1`` respectively. + +VRs +---- + +There are currently 2 vector extensions to LoongArch: + +- LSX (Loongson SIMD eXtension) with 128-bit vectors, +- LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors. + +LSX brings ``$v0`` ~ ``$v31`` while LASX brings ``$x0`` ~ ``$x31`` as the vector +registers. + +The VRs overlap with FPRs: for example, on a core implementing LSX and LASX, +the lower 128 bits of ``$x0`` is shared with ``$v0``, and the lower 64 bits of +``$v0`` is shared with ``$f0``; same with all other VRs. + +CSRs +---- + +CSRs can only be accessed from privileged mode (PLV0): + +================= ===================================== ============== +Address Full Name Abbrev Name +================= ===================================== ============== +0x0 Current Mode Information CRMD +0x1 Pre-exception Mode Information PRMD +0x2 Extension Unit Enable EUEN +0x3 Miscellaneous Control MISC +0x4 Exception Configuration ECFG +0x5 Exception Status ESTAT +0x6 Exception Return Address ERA +0x7 Bad (Faulting) Virtual Address BADV +0x8 Bad (Faulting) Instruction Word BADI +0xC Exception Entrypoint Address EENTRY +0x10 TLB Index TLBIDX +0x11 TLB Entry High-order Bits TLBEHI +0x12 TLB Entry Low-order Bits 0 TLBELO0 +0x13 TLB Entry Low-order Bits 1 TLBELO1 +0x18 Address Space Identifier ASID +0x19 Page Global Directory Address for PGDL + Lower-half Address Space +0x1A Page Global Directory Address for PGDH + Higher-half Address Space +0x1B Page Global Directory Address PGD +0x1C Page Walk Control for Lower- PWCL + half Address Space +0x1D Page Walk Control for Higher- PWCH + half Address Space +0x1E STLB Page Size STLBPS +0x1F Reduced Virtual Address Configuration RVACFG +0x20 CPU Identifier CPUID +0x21 Privileged Resource Configuration 1 PRCFG1 +0x22 Privileged Resource Configuration 2 PRCFG2 +0x23 Privileged Resource Configuration 3 PRCFG3 +0x30+n (0≤n≤15) Saved Data register SAVEn +0x40 Timer Identifier TID +0x41 Timer Configuration TCFG +0x42 Timer Value TVAL +0x43 Compensation of Timer Count CNTC +0x44 Timer Interrupt Clearing TICLR +0x60 LLBit Control LLBCTL +0x80 Implementation-specific Control 1 IMPCTL1 +0x81 Implementation-specific Control 2 IMPCTL2 +0x88 TLB Refill Exception Entrypoint TLBRENTRY + Address +0x89 TLB Refill Exception BAD (Faulting) TLBRBADV + Virtual Address +0x8A TLB Refill Exception Return Address TLBRERA +0x8B TLB Refill Exception Saved Data TLBRSAVE + Register +0x8C TLB Refill Exception Entry Low-order TLBRELO0 + Bits 0 +0x8D TLB Refill Exception Entry Low-order TLBRELO1 + Bits 1 +0x8E TLB Refill Exception Entry High-order TLBEHI + Bits +0x8F TLB Refill Exception Pre-exception TLBRPRMD + Mode Information +0x90 Machine Error Control MERRCTL +0x91 Machine Error Information 1 MERRINFO1 +0x92 Machine Error Information 2 MERRINFO2 +0x93 Machine Error Exception Entrypoint MERRENTRY + Address +0x94 Machine Error Exception Return MERRERA + Address +0x95 Machine Error Exception Saved Data MERRSAVE + Register +0x98 Cache TAGs CTAG +0x180+n (0≤n≤3) Direct Mapping Configuration Window n DMWn +0x200+2n (0≤n≤31) Performance Monitor Configuration n PMCFGn +0x201+2n (0≤n≤31) Performance Monitor Overall Counter n PMCNTn +0x300 Memory Load/Store WatchPoint MWPC + Overall Control +0x301 Memory Load/Store WatchPoint MWPS + Overall Status +0x310+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG1 + Configuration 1 +0x311+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG2 + Configuration 2 +0x312+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG3 + Configuration 3 +0x313+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG4 + Configuration 4 +0x380 Instruction Fetch WatchPoint FWPC + Overall Control +0x381 Instruction Fetch WatchPoint FWPS + Overall Status +0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1 + Configuration 1 +0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2 + Configuration 2 +0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3 + Configuration 3 +0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4 + Configuration 4 +0x500 Debug Register DBG +0x501 Debug Exception Return Address DERA +0x502 Debug Exception Saved Data Register DSAVE +================= ===================================== ============== + +ERA, TLBRERA, MERRERA and DERA are sometimes also known as EPC, TLBREPC, MERREPC +and DEPC respectively. + +Basic Instruction Set +===================== + +Instruction formats +------------------- + +LoongArch instructions are 32 bits wide, belonging to 9 basic instruction +formats (and variants of them): + +=========== ========================== +Format name Composition +=========== ========================== +2R Opcode + Rj + Rd +3R Opcode + Rk + Rj + Rd +4R Opcode + Ra + Rk + Rj + Rd +2RI8 Opcode + I8 + Rj + Rd +2RI12 Opcode + I12 + Rj + Rd +2RI14 Opcode + I14 + Rj + Rd +2RI16 Opcode + I16 + Rj + Rd +1RI21 Opcode + I21L + Rj + I21H +I26 Opcode + I26L + I26H +=========== ========================== + +Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for +"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are +immediate operands of respective width. The longer I21 and I26 are stored +in separate higher and lower parts in the instruction word, denoted by the "L" +and "H" suffixes. + +List of Instructions +-------------------- + +For brevity, only instruction names (mnemonics) are listed here; please see the +:ref:`References ` for details. + + +1. Arithmetic Instructions:: + + ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D + SLT SLTU SLTI SLTUI + AND OR NOR XOR ANDN ORN ANDI ORI XORI + MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU + MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU + PCADDI PCADDU12I PCADDU18I + LU12I.W LU32I.D LU52I.D ADDU16I.D + +2. Bit-shift Instructions:: + + SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W + SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D + +3. Bit-manipulation Instructions:: + + EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D + BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D + REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D + MASKEQZ MASKNEZ + +4. Branch Instructions:: + + BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL + +5. Load/Store Instructions:: + + LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D + LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D + LDPTR.W LDPTR.D STPTR.W STPTR.D + PRELD PRELDX + +6. Atomic Operation Instructions:: + + LL.W SC.W LL.D SC.D + AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D + AMMAX.W AMMAX.D AMMIN.W AMMIN.D + +7. Barrier Instructions:: + + IBAR DBAR + +8. Special Instructions:: + + SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D + ASRTLE.D ASRTGT.D + +9. Privileged Instructions:: + + CSRRD CSRWR CSRXCHG + IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D + CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE + +Virtual Memory +============== + +LoongArch supports direct-mapped virtual memory and page-mapped virtual memory. + +Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple +relationship between virtual address (VA) and physical address (PA):: + + VA = PA + FixedOffset + +Page-mapped virtual memory has arbitrary relationship between VA and PA, which +is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative +MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB). + +By default, the whole virtual address space of LA32 is configured like this: + +============ =========================== ============================= +Name Address Range Attributes +============ =========================== ============================= +``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3 +``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0 +``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0 +``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0 +============ =========================== ============================= + +User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and +KPRANGE1, PA is equal to VA with bit30~31 cleared. For example, the uncached +direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped +VA of 0x00001000 is 0xA0001000. + +By default, the whole virtual address space of LA64 is configured like this: + +============ ====================== ====================================== +Name Address Range Attributes +============ ====================== ====================================== +``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3 + 0x3FFFFFFFFFFFFFFF`` +``XSPRANGE`` ``0x4000000000000000 - Direct-mapped, Cached / Uncached, PLV0 + 0x7FFFFFFFFFFFFFFF`` +``XKPRANGE`` ``0x8000000000000000 - Direct-mapped, Cached / Uncached, PLV0 + 0xBFFFFFFFFFFFFFFF`` +``XKVRANGE`` ``0xC000000000000000 - Page-mapped, Cached, PLV0 + 0xFFFFFFFFFFFFFFFF`` +============ ====================== ====================================== + +User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and +XKPRANGE, PA is equal to VA with bits 60~63 cleared, and the cache attribute +is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is +for coherent cached, and 2 is for weakly-ordered uncached. + +Currently we only use XKPRANGE for direct mapping and XSPRANGE is reserved. + +To put this in action: the strongly-ordered uncached direct-mapped VA (in +XKPRANGE) of 0x00000000_00001000 is 0x80000000_00001000, the coherent cached +direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000, +and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000 +_00001000 is 0xA0000000_00001000. + +Relationship of Loongson and LoongArch +====================================== + +LoongArch is a RISC ISA which is different from any other existing ones, while +Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is +the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series, +and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on +MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example: +Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson- +3A5000 (and future revisions) are all based on LoongArch. + +.. _loongarch-references: + +References +========== + +Official web site of Loongson Technology Corp. Ltd.: + + http://www.loongson.cn/ + +Developer web site of Loongson and LoongArch (Software and Documentation): + + http://www.loongnix.cn/ + + https://github.com/loongson/ + + https://loongson.github.io/LoongArch-Documentation/ + +Documentation of LoongArch ISA: + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf (in Chinese) + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf (in English) + +Documentation of LoongArch ELF psABI: + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf (in Chinese) + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf (in English) + +Linux kernel repository of Loongson and LoongArch: + + https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst new file mode 100644 index 000000000000..7988f4192363 --- /dev/null +++ b/Documentation/arch/loongarch/irq-chip-model.rst @@ -0,0 +1,160 @@ +.. SPDX-License-Identifier: GPL-2.0 + +======================================= +IRQ chip model (hierarchy) of LoongArch +======================================= + +Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together +with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core +Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended +I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), +PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller +in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). + +CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package +controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., +in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, +and there are two models of hierarchy (legacy model and extended model). + +Legacy IRQ model +================ + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go +to LIOINTC, and then CPUINTC:: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ + | + +---------+ +-------+ + | LIOINTC | <-- | UARTs | + +---------+ +-------+ + ^ + | + +-----------+ + | HTVECINTC | + +-----------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + +Extended IRQ model +================== + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to +to CPUINTC directly:: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ +-------+ + | EIOINTC | | LIOINTC | <-- | UARTs | + +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + +ACPI-related definitions +======================== + +CPUINTC:: + + ACPI_MADT_TYPE_CORE_PIC; + struct acpi_madt_core_pic; + enum acpi_madt_core_pic_version; + +LIOINTC:: + + ACPI_MADT_TYPE_LIO_PIC; + struct acpi_madt_lio_pic; + enum acpi_madt_lio_pic_version; + +EIOINTC:: + + ACPI_MADT_TYPE_EIO_PIC; + struct acpi_madt_eio_pic; + enum acpi_madt_eio_pic_version; + +HTVECINTC:: + + ACPI_MADT_TYPE_HT_PIC; + struct acpi_madt_ht_pic; + enum acpi_madt_ht_pic_version; + +PCH-PIC:: + + ACPI_MADT_TYPE_BIO_PIC; + struct acpi_madt_bio_pic; + enum acpi_madt_bio_pic_version; + +PCH-MSI:: + + ACPI_MADT_TYPE_MSI_PIC; + struct acpi_madt_msi_pic; + enum acpi_madt_msi_pic_version; + +PCH-LPC:: + + ACPI_MADT_TYPE_LPC_PIC; + struct acpi_madt_lpc_pic; + enum acpi_madt_lpc_pic_version; + +References +========== + +Documentation of Loongson-3A5000: + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese) + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English) + +Documentation of Loongson's LS7A chipset: + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese) + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English) + +.. Note:: + - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described + in Section 7.4 of "LoongArch Reference Manual, Vol 1"; + - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of + "Loongson 3A5000 Processor Reference Manual"; + - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of + "Loongson 3A5000 Processor Reference Manual"; + - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of + "Loongson 3A5000 Processor Reference Manual"; + - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of + "Loongson 7A1000 Bridge User Manual"; + - PCH-LPC is "LPC Interrupts" described in Section 24.3 of + "Loongson 7A1000 Bridge User Manual". diff --git a/Documentation/loongarch/booting.rst b/Documentation/loongarch/booting.rst deleted file mode 100644 index 91eccd410478..000000000000 --- a/Documentation/loongarch/booting.rst +++ /dev/null @@ -1,42 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -======================= -Booting Linux/LoongArch -======================= - -:Author: Yanteng Si -:Date: 18 Nov 2022 - -Information passed from BootLoader to kernel -============================================ - -LoongArch supports ACPI and FDT. The information that needs to be passed -to the kernel includes the memmap, the initrd, the command line, optionally -the ACPI/FDT tables, and so on. - -The kernel is passed the following arguments on `kernel_entry` : - - - a0 = efi_boot: `efi_boot` is a flag indicating whether - this boot environment is fully UEFI-compliant. - - - a1 = cmdline: `cmdline` is a pointer to the kernel command line. - - - a2 = systemtable: `systemtable` points to the EFI system table. - All pointers involved at this stage are in physical addresses. - -Header of Linux/LoongArch kernel images -======================================= - -Linux/LoongArch kernel images are EFI images. Being PE files, they have -a 64-byte header structured like:: - - u32 MZ_MAGIC /* "MZ", MS-DOS header */ - u32 res0 = 0 /* Reserved */ - u64 kernel_entry /* Kernel entry point */ - u64 _end - _text /* Kernel image effective size */ - u64 load_offset /* Kernel image load offset from start of RAM */ - u64 res1 = 0 /* Reserved */ - u64 res2 = 0 /* Reserved */ - u64 res3 = 0 /* Reserved */ - u32 LINUX_PE_MAGIC /* Magic number */ - u32 pe_header - _head /* Offset to the PE header */ diff --git a/Documentation/loongarch/features.rst b/Documentation/loongarch/features.rst deleted file mode 100644 index ebacade3ea45..000000000000 --- a/Documentation/loongarch/features.rst +++ /dev/null @@ -1,3 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. kernel-feat:: $srctree/Documentation/features loongarch diff --git a/Documentation/loongarch/index.rst b/Documentation/loongarch/index.rst deleted file mode 100644 index c779bfa00c05..000000000000 --- a/Documentation/loongarch/index.rst +++ /dev/null @@ -1,22 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -====================== -LoongArch Architecture -====================== - -.. toctree:: - :maxdepth: 2 - :numbered: - - introduction - booting - irq-chip-model - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/loongarch/introduction.rst b/Documentation/loongarch/introduction.rst deleted file mode 100644 index 49135d451ced..000000000000 --- a/Documentation/loongarch/introduction.rst +++ /dev/null @@ -1,390 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -========================= -Introduction to LoongArch -========================= - -LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are -currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit -version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels -(PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0 -while applications run at PLV3. This document introduces the registers, basic -instruction set, virtual memory and some other topics of LoongArch. - -Registers -========= - -LoongArch registers include general purpose registers (GPRs), floating point -registers (FPRs), vector registers (VRs) and control status registers (CSRs) -used in privileged mode (PLV0). - -GPRs ----- - -LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32 -and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers -are not architecturally special. (Except ``$r1``, which is hard-wired as the -link register of the BL instruction.) - -The kernel uses a variant of the LoongArch register convention, as described in -the LoongArch ELF psABI spec, in :ref:`References `: - -================= =============== =================== ============ -Name Alias Usage Preserved - across calls -================= =============== =================== ============ -``$r0`` ``$zero`` Constant zero Unused -``$r1`` ``$ra`` Return address No -``$r2`` ``$tp`` TLS/Thread pointer Unused -``$r3`` ``$sp`` Stack pointer Yes -``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No -``$r4``-``$r5`` ``$v0``-``$v1`` Return value No -``$r12``-``$r20`` ``$t0``-``$t8`` Temp registers No -``$r21`` ``$u0`` Percpu base address Unused -``$r22`` ``$fp`` Frame pointer Yes -``$r23``-``$r31`` ``$s0``-``$s8`` Static registers Yes -================= =============== =================== ============ - -.. Note:: - The register ``$r21`` is reserved in the ELF psABI, but used by the Linux - kernel for storing the percpu base address. It normally has no ABI name, - but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1`` - in some old code,however they are deprecated aliases of ``$a0`` and ``$a1`` - respectively. - -FPRs ----- - -LoongArch has 32 FPRs ( ``$f0`` ~ ``$f31`` ) when FPU is present. Each one is -64-bit wide on the LA64 cores. - -The floating-point register convention is the same as described in the -LoongArch ELF psABI spec: - -================= ================== =================== ============ -Name Alias Usage Preserved - across calls -================= ================== =================== ============ -``$f0``-``$f7`` ``$fa0``-``$fa7`` Argument registers No -``$f0``-``$f1`` ``$fv0``-``$fv1`` Return value No -``$f8``-``$f23`` ``$ft0``-``$ft15`` Temp registers No -``$f24``-``$f31`` ``$fs0``-``$fs7`` Static registers Yes -================= ================== =================== ============ - -.. Note:: - You may see ``$fv0`` or ``$fv1`` in some old code, however they are - deprecated aliases of ``$fa0`` and ``$fa1`` respectively. - -VRs ----- - -There are currently 2 vector extensions to LoongArch: - -- LSX (Loongson SIMD eXtension) with 128-bit vectors, -- LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors. - -LSX brings ``$v0`` ~ ``$v31`` while LASX brings ``$x0`` ~ ``$x31`` as the vector -registers. - -The VRs overlap with FPRs: for example, on a core implementing LSX and LASX, -the lower 128 bits of ``$x0`` is shared with ``$v0``, and the lower 64 bits of -``$v0`` is shared with ``$f0``; same with all other VRs. - -CSRs ----- - -CSRs can only be accessed from privileged mode (PLV0): - -================= ===================================== ============== -Address Full Name Abbrev Name -================= ===================================== ============== -0x0 Current Mode Information CRMD -0x1 Pre-exception Mode Information PRMD -0x2 Extension Unit Enable EUEN -0x3 Miscellaneous Control MISC -0x4 Exception Configuration ECFG -0x5 Exception Status ESTAT -0x6 Exception Return Address ERA -0x7 Bad (Faulting) Virtual Address BADV -0x8 Bad (Faulting) Instruction Word BADI -0xC Exception Entrypoint Address EENTRY -0x10 TLB Index TLBIDX -0x11 TLB Entry High-order Bits TLBEHI -0x12 TLB Entry Low-order Bits 0 TLBELO0 -0x13 TLB Entry Low-order Bits 1 TLBELO1 -0x18 Address Space Identifier ASID -0x19 Page Global Directory Address for PGDL - Lower-half Address Space -0x1A Page Global Directory Address for PGDH - Higher-half Address Space -0x1B Page Global Directory Address PGD -0x1C Page Walk Control for Lower- PWCL - half Address Space -0x1D Page Walk Control for Higher- PWCH - half Address Space -0x1E STLB Page Size STLBPS -0x1F Reduced Virtual Address Configuration RVACFG -0x20 CPU Identifier CPUID -0x21 Privileged Resource Configuration 1 PRCFG1 -0x22 Privileged Resource Configuration 2 PRCFG2 -0x23 Privileged Resource Configuration 3 PRCFG3 -0x30+n (0≤n≤15) Saved Data register SAVEn -0x40 Timer Identifier TID -0x41 Timer Configuration TCFG -0x42 Timer Value TVAL -0x43 Compensation of Timer Count CNTC -0x44 Timer Interrupt Clearing TICLR -0x60 LLBit Control LLBCTL -0x80 Implementation-specific Control 1 IMPCTL1 -0x81 Implementation-specific Control 2 IMPCTL2 -0x88 TLB Refill Exception Entrypoint TLBRENTRY - Address -0x89 TLB Refill Exception BAD (Faulting) TLBRBADV - Virtual Address -0x8A TLB Refill Exception Return Address TLBRERA -0x8B TLB Refill Exception Saved Data TLBRSAVE - Register -0x8C TLB Refill Exception Entry Low-order TLBRELO0 - Bits 0 -0x8D TLB Refill Exception Entry Low-order TLBRELO1 - Bits 1 -0x8E TLB Refill Exception Entry High-order TLBEHI - Bits -0x8F TLB Refill Exception Pre-exception TLBRPRMD - Mode Information -0x90 Machine Error Control MERRCTL -0x91 Machine Error Information 1 MERRINFO1 -0x92 Machine Error Information 2 MERRINFO2 -0x93 Machine Error Exception Entrypoint MERRENTRY - Address -0x94 Machine Error Exception Return MERRERA - Address -0x95 Machine Error Exception Saved Data MERRSAVE - Register -0x98 Cache TAGs CTAG -0x180+n (0≤n≤3) Direct Mapping Configuration Window n DMWn -0x200+2n (0≤n≤31) Performance Monitor Configuration n PMCFGn -0x201+2n (0≤n≤31) Performance Monitor Overall Counter n PMCNTn -0x300 Memory Load/Store WatchPoint MWPC - Overall Control -0x301 Memory Load/Store WatchPoint MWPS - Overall Status -0x310+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG1 - Configuration 1 -0x311+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG2 - Configuration 2 -0x312+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG3 - Configuration 3 -0x313+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG4 - Configuration 4 -0x380 Instruction Fetch WatchPoint FWPC - Overall Control -0x381 Instruction Fetch WatchPoint FWPS - Overall Status -0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1 - Configuration 1 -0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2 - Configuration 2 -0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3 - Configuration 3 -0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4 - Configuration 4 -0x500 Debug Register DBG -0x501 Debug Exception Return Address DERA -0x502 Debug Exception Saved Data Register DSAVE -================= ===================================== ============== - -ERA, TLBRERA, MERRERA and DERA are sometimes also known as EPC, TLBREPC, MERREPC -and DEPC respectively. - -Basic Instruction Set -===================== - -Instruction formats -------------------- - -LoongArch instructions are 32 bits wide, belonging to 9 basic instruction -formats (and variants of them): - -=========== ========================== -Format name Composition -=========== ========================== -2R Opcode + Rj + Rd -3R Opcode + Rk + Rj + Rd -4R Opcode + Ra + Rk + Rj + Rd -2RI8 Opcode + I8 + Rj + Rd -2RI12 Opcode + I12 + Rj + Rd -2RI14 Opcode + I14 + Rj + Rd -2RI16 Opcode + I16 + Rj + Rd -1RI21 Opcode + I21L + Rj + I21H -I26 Opcode + I26L + I26H -=========== ========================== - -Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for -"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are -immediate operands of respective width. The longer I21 and I26 are stored -in separate higher and lower parts in the instruction word, denoted by the "L" -and "H" suffixes. - -List of Instructions --------------------- - -For brevity, only instruction names (mnemonics) are listed here; please see the -:ref:`References ` for details. - - -1. Arithmetic Instructions:: - - ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D - SLT SLTU SLTI SLTUI - AND OR NOR XOR ANDN ORN ANDI ORI XORI - MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU - MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU - PCADDI PCADDU12I PCADDU18I - LU12I.W LU32I.D LU52I.D ADDU16I.D - -2. Bit-shift Instructions:: - - SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W - SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D - -3. Bit-manipulation Instructions:: - - EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D - BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D - REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D - MASKEQZ MASKNEZ - -4. Branch Instructions:: - - BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL - -5. Load/Store Instructions:: - - LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D - LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D - LDPTR.W LDPTR.D STPTR.W STPTR.D - PRELD PRELDX - -6. Atomic Operation Instructions:: - - LL.W SC.W LL.D SC.D - AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D - AMMAX.W AMMAX.D AMMIN.W AMMIN.D - -7. Barrier Instructions:: - - IBAR DBAR - -8. Special Instructions:: - - SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D - ASRTLE.D ASRTGT.D - -9. Privileged Instructions:: - - CSRRD CSRWR CSRXCHG - IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D - CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE - -Virtual Memory -============== - -LoongArch supports direct-mapped virtual memory and page-mapped virtual memory. - -Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple -relationship between virtual address (VA) and physical address (PA):: - - VA = PA + FixedOffset - -Page-mapped virtual memory has arbitrary relationship between VA and PA, which -is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative -MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB). - -By default, the whole virtual address space of LA32 is configured like this: - -============ =========================== ============================= -Name Address Range Attributes -============ =========================== ============================= -``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3 -``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0 -``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0 -``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0 -============ =========================== ============================= - -User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and -KPRANGE1, PA is equal to VA with bit30~31 cleared. For example, the uncached -direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped -VA of 0x00001000 is 0xA0001000. - -By default, the whole virtual address space of LA64 is configured like this: - -============ ====================== ====================================== -Name Address Range Attributes -============ ====================== ====================================== -``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3 - 0x3FFFFFFFFFFFFFFF`` -``XSPRANGE`` ``0x4000000000000000 - Direct-mapped, Cached / Uncached, PLV0 - 0x7FFFFFFFFFFFFFFF`` -``XKPRANGE`` ``0x8000000000000000 - Direct-mapped, Cached / Uncached, PLV0 - 0xBFFFFFFFFFFFFFFF`` -``XKVRANGE`` ``0xC000000000000000 - Page-mapped, Cached, PLV0 - 0xFFFFFFFFFFFFFFFF`` -============ ====================== ====================================== - -User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and -XKPRANGE, PA is equal to VA with bits 60~63 cleared, and the cache attribute -is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is -for coherent cached, and 2 is for weakly-ordered uncached. - -Currently we only use XKPRANGE for direct mapping and XSPRANGE is reserved. - -To put this in action: the strongly-ordered uncached direct-mapped VA (in -XKPRANGE) of 0x00000000_00001000 is 0x80000000_00001000, the coherent cached -direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000, -and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000 -_00001000 is 0xA0000000_00001000. - -Relationship of Loongson and LoongArch -====================================== - -LoongArch is a RISC ISA which is different from any other existing ones, while -Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is -the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series, -and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on -MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example: -Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson- -3A5000 (and future revisions) are all based on LoongArch. - -.. _loongarch-references: - -References -========== - -Official web site of Loongson Technology Corp. Ltd.: - - http://www.loongson.cn/ - -Developer web site of Loongson and LoongArch (Software and Documentation): - - http://www.loongnix.cn/ - - https://github.com/loongson/ - - https://loongson.github.io/LoongArch-Documentation/ - -Documentation of LoongArch ISA: - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf (in Chinese) - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf (in English) - -Documentation of LoongArch ELF psABI: - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf (in Chinese) - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf (in English) - -Linux kernel repository of Loongson and LoongArch: - - https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git diff --git a/Documentation/loongarch/irq-chip-model.rst b/Documentation/loongarch/irq-chip-model.rst deleted file mode 100644 index 7988f4192363..000000000000 --- a/Documentation/loongarch/irq-chip-model.rst +++ /dev/null @@ -1,160 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -======================================= -IRQ chip model (hierarchy) of LoongArch -======================================= - -Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together -with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core -Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended -I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller), -PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller -in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). - -CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package -controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., -in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy, -and there are two models of hierarchy (legacy model and extended model). - -Legacy IRQ model -================ - -In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go -to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices -interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go -to LIOINTC, and then CPUINTC:: - - +-----+ +---------+ +-------+ - | IPI | --> | CPUINTC | <-- | Timer | - +-----+ +---------+ +-------+ - ^ - | - +---------+ +-------+ - | LIOINTC | <-- | UARTs | - +---------+ +-------+ - ^ - | - +-----------+ - | HTVECINTC | - +-----------+ - ^ ^ - | | - +---------+ +---------+ - | PCH-PIC | | PCH-MSI | - +---------+ +---------+ - ^ ^ ^ - | | | - +---------+ +---------+ +---------+ - | PCH-LPC | | Devices | | Devices | - +---------+ +---------+ +---------+ - ^ - | - +---------+ - | Devices | - +---------+ - -Extended IRQ model -================== - -In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go -to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices -interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to -to CPUINTC directly:: - - +-----+ +---------+ +-------+ - | IPI | --> | CPUINTC | <-- | Timer | - +-----+ +---------+ +-------+ - ^ ^ - | | - +---------+ +---------+ +-------+ - | EIOINTC | | LIOINTC | <-- | UARTs | - +---------+ +---------+ +-------+ - ^ ^ - | | - +---------+ +---------+ - | PCH-PIC | | PCH-MSI | - +---------+ +---------+ - ^ ^ ^ - | | | - +---------+ +---------+ +---------+ - | PCH-LPC | | Devices | | Devices | - +---------+ +---------+ +---------+ - ^ - | - +---------+ - | Devices | - +---------+ - -ACPI-related definitions -======================== - -CPUINTC:: - - ACPI_MADT_TYPE_CORE_PIC; - struct acpi_madt_core_pic; - enum acpi_madt_core_pic_version; - -LIOINTC:: - - ACPI_MADT_TYPE_LIO_PIC; - struct acpi_madt_lio_pic; - enum acpi_madt_lio_pic_version; - -EIOINTC:: - - ACPI_MADT_TYPE_EIO_PIC; - struct acpi_madt_eio_pic; - enum acpi_madt_eio_pic_version; - -HTVECINTC:: - - ACPI_MADT_TYPE_HT_PIC; - struct acpi_madt_ht_pic; - enum acpi_madt_ht_pic_version; - -PCH-PIC:: - - ACPI_MADT_TYPE_BIO_PIC; - struct acpi_madt_bio_pic; - enum acpi_madt_bio_pic_version; - -PCH-MSI:: - - ACPI_MADT_TYPE_MSI_PIC; - struct acpi_madt_msi_pic; - enum acpi_madt_msi_pic_version; - -PCH-LPC:: - - ACPI_MADT_TYPE_LPC_PIC; - struct acpi_madt_lpc_pic; - enum acpi_madt_lpc_pic_version; - -References -========== - -Documentation of Loongson-3A5000: - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese) - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English) - -Documentation of Loongson's LS7A chipset: - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese) - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English) - -.. Note:: - - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described - in Section 7.4 of "LoongArch Reference Manual, Vol 1"; - - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of - "Loongson 3A5000 Processor Reference Manual"; - - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of - "Loongson 3A5000 Processor Reference Manual"; - - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of - "Loongson 3A5000 Processor Reference Manual"; - - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of - "Loongson 7A1000 Bridge User Manual"; - - PCH-LPC is "LPC Interrupts" described in Section 24.3 of - "Loongson 7A1000 Bridge User Manual". diff --git a/Documentation/translations/zh_CN/arch/index.rst b/Documentation/translations/zh_CN/arch/index.rst index 6fa0cb671009..d4c1c729dde2 100644 --- a/Documentation/translations/zh_CN/arch/index.rst +++ b/Documentation/translations/zh_CN/arch/index.rst @@ -13,7 +13,7 @@ ../riscv/index openrisc/index parisc/index - ../loongarch/index + loongarch/index TODOList: diff --git a/Documentation/translations/zh_CN/arch/loongarch/booting.rst b/Documentation/translations/zh_CN/arch/loongarch/booting.rst new file mode 100644 index 000000000000..d2f55872904e --- /dev/null +++ b/Documentation/translations/zh_CN/arch/loongarch/booting.rst @@ -0,0 +1,48 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/loongarch/booting.rst + +:翻译: + + 司延腾 Yanteng Si + +==================== +启动 Linux/LoongArch +==================== + +:作者: 司延腾 +:日期: 2022年11月18日 + +BootLoader传递给内核的信息 +========================== + +LoongArch支持ACPI和FDT启动，需要传递给内核的信息包括memmap、initrd、cmdline、可 +选的ACPI/FDT表等。 + +内核在 `kernel_entry` 入口处被传递以下参数: + + - a0 = efi_boot: `efi_boot` 是一个标志，表示这个启动环境是否完全符合UEFI + 的要求。 + + - a1 = cmdline: `cmdline` 是一个指向内核命令行的指针。 + + - a2 = systemtable: `systemtable` 指向EFI的系统表，在这个阶段涉及的所有 + 指针都是物理地址。 + +Linux/LoongArch内核镜像文件头 +============================= + +内核镜像是EFI镜像。作为PE文件，它们有一个64字节的头部结构体，如下所示:: + + u32 MZ_MAGIC /* "MZ", MS-DOS 头 */ + u32 res0 = 0 /* 保留 */ + u64 kernel_entry /* 内核入口点 */ + u64 _end - _text /* 内核镜像有效大小 */ + u64 load_offset /* 加载内核镜像相对内存起始地址的偏移量 */ + u64 res1 = 0 /* 保留 */ + u64 res2 = 0 /* 保留 */ + u64 res3 = 0 /* 保留 */ + u32 LINUX_PE_MAGIC /* 魔术数 */ + u32 pe_header - _head /* 到PE头的偏移量 */ diff --git a/Documentation/translations/zh_CN/arch/loongarch/features.rst b/Documentation/translations/zh_CN/arch/loongarch/features.rst new file mode 100644 index 000000000000..82bfac180bdc --- /dev/null +++ b/Documentation/translations/zh_CN/arch/loongarch/features.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/loongarch/features.rst +:Translator: Huacai Chen + +.. kernel-feat:: $srctree/Documentation/features loongarch diff --git a/Documentation/translations/zh_CN/arch/loongarch/index.rst b/Documentation/translations/zh_CN/arch/loongarch/index.rst new file mode 100644 index 000000000000..4bd24f5ffed1 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/loongarch/index.rst @@ -0,0 +1,27 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/loongarch/index.rst +:Translator: Huacai Chen + +================= +LoongArch体系结构 +================= + +.. toctree:: + :maxdepth: 2 + :numbered: + + introduction + booting + irq-chip-model + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/arch/loongarch/introduction.rst b/Documentation/translations/zh_CN/arch/loongarch/introduction.rst new file mode 100644 index 000000000000..cba04befc950 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/loongarch/introduction.rst @@ -0,0 +1,353 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/loongarch/introduction.rst +:Translator: Huacai Chen + +============= +LoongArch介绍 +============= + +LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集 +包括一个精简32位版（LA32R）、一个标准32位版（LA32S）、一个64位版（LA64）。 +LoongArch定义了四个特权级（PLV0~PLV3），其中PLV0是最高特权级，用于内核；而PLV3 +是最低特权级，用于应用程序。本文档介绍了LoongArch的寄存器、基础指令集、虚拟内 +存以及其他一些主题。 + +寄存器 +====== + +LoongArch的寄存器包括通用寄存器（GPRs）、浮点寄存器（FPRs）、向量寄存器（VRs） +和用于特权模式（PLV0）的控制状态寄存器（CSRs）。 + +通用寄存器 +---------- + +LoongArch包括32个通用寄存器（ ``$r0`` ~ ``$r31`` ），LA32中每个寄存器为32位宽， +LA64中每个寄存器为64位宽。 ``$r0`` 的内容总是固定为0，而其他寄存器在体系结构层面 +没有特殊功能。（ ``$r1`` 算是一个例外，在BL指令中固定用作链接返回寄存器。） + +内核使用了一套LoongArch寄存器约定，定义在LoongArch ELF psABI规范中，详细描述参见 +:ref:`参考文献 `: + +================= =============== =================== ========== +寄存器名 别名 用途 跨调用保持 +================= =============== =================== ========== +``$r0`` ``$zero`` 常量0 不使用 +``$r1`` ``$ra`` 返回地址 否 +``$r2`` ``$tp`` TLS/线程信息指针 不使用 +``$r3`` ``$sp`` 栈指针 是 +``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否 +``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否 +``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否 +``$r21`` ``$u0`` 每CPU变量基地址 不使用 +``$r22`` ``$fp`` 帧指针 是 +``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是 +================= =============== =================== ========== + +.. note:: + 注意： ``$r21`` 寄存器在ELF psABI中保留未使用，但是在Linux内核用于保 + 存每CPU变量基地址。该寄存器没有ABI命名，不过在内核中称为 ``$u0`` 。在 + 一些遗留代码中有时可能见到 ``$v0`` 和 ``$v1`` ，它们是 ``$a0`` 和 + ``$a1`` 的别名，属于已经废弃的用法。 + +浮点寄存器 +---------- + +当系统中存在FPU时，LoongArch有32个浮点寄存器（ ``$f0`` ~ ``$f31`` ）。在LA64 +的CPU核上，每个寄存器均为64位宽。 + +浮点寄存器的使用约定与LoongArch ELF psABI规范的描述相同： + +================= ================== =================== ========== +寄存器名 别名 用途 跨调用保持 +================= ================== =================== ========== +``$f0``-``$f7`` ``$fa0``-``$fa7`` 参数寄存器 否 +``$f0``-``$f1`` ``$fv0``-``$fv1`` 返回值 否 +``$f8``-``$f23`` ``$ft0``-``$ft15`` 临时寄存器 否 +``$f24``-``$f31`` ``$fs0``-``$fs7`` 静态寄存器 是 +================= ================== =================== ========== + +.. note:: + 注意：在一些遗留代码中有时可能见到 ``$fv0`` 和 ``$fv1`` ，它们是 + ``$fa0`` 和 ``$fa1`` 的别名，属于已经废弃的用法。 + + +向量寄存器 +---------- + +LoongArch现有两种向量扩展： + +- 128位向量扩展LSX（全称Loongson SIMD eXtention）， +- 256位向量扩展LASX（全称Loongson Advanced SIMD eXtention）。 + +LSX使用 ``$v0`` ~ ``$v31`` 向量寄存器，而LASX则使用 ``$x0`` ~ ``$x31`` 。 + +浮点寄存器和向量寄存器是复用的，比如：在一个实现了LSX和LASX的核上， ``$x0`` 的 +低128位与 ``$v0`` 共用， ``$v0`` 的低64位与 ``$f0`` 共用，其他寄存器依此类推。 + +控制状态寄存器 +-------------- + +控制状态寄存器只能在特权模式（PLV0）下访问: + +================= ==================================== ========== +地址 全称描述 简称 +================= ==================================== ========== +0x0 当前模式信息 CRMD +0x1 异常前模式信息 PRMD +0x2 扩展部件使能 EUEN +0x3 杂项控制 MISC +0x4 异常配置 ECFG +0x5 异常状态 ESTAT +0x6 异常返回地址 ERA +0x7 出错(Faulting)虚拟地址 BADV +0x8 出错(Faulting)指令字 BADI +0xC 异常入口地址 EENTRY +0x10 TLB索引 TLBIDX +0x11 TLB表项高位 TLBEHI +0x12 TLB表项低位0 TLBELO0 +0x13 TLB表项低位1 TLBELO1 +0x18 地址空间标识符 ASID +0x19 低半地址空间页全局目录基址 PGDL +0x1A 高半地址空间页全局目录基址 PGDH +0x1B 页全局目录基址 PGD +0x1C 页表遍历控制低半部分 PWCL +0x1D 页表遍历控制高半部分 PWCH +0x1E STLB页大小 STLBPS +0x1F 缩减虚地址配置 RVACFG +0x20 CPU编号 CPUID +0x21 特权资源配置信息1 PRCFG1 +0x22 特权资源配置信息2 PRCFG2 +0x23 特权资源配置信息3 PRCFG3 +0x30+n (0≤n≤15) 数据保存寄存器 SAVEn +0x40 定时器编号 TID +0x41 定时器配置 TCFG +0x42 定时器值 TVAL +0x43 计时器补偿 CNTC +0x44 定时器中断清除 TICLR +0x60 LLBit相关控制 LLBCTL +0x80 实现相关控制1 IMPCTL1 +0x81 实现相关控制2 IMPCTL2 +0x88 TLB重填异常入口地址 TLBRENTRY +0x89 TLB重填异常出错(Faulting)虚地址 TLBRBADV +0x8A TLB重填异常返回地址 TLBRERA +0x8B TLB重填异常数据保存 TLBRSAVE +0x8C TLB重填异常表项低位0 TLBRELO0 +0x8D TLB重填异常表项低位1 TLBRELO1 +0x8E TLB重填异常表项高位 TLBEHI +0x8F TLB重填异常前模式信息 TLBRPRMD +0x90 机器错误控制 MERRCTL +0x91 机器错误信息1 MERRINFO1 +0x92 机器错误信息2 MERRINFO2 +0x93 机器错误异常入口地址 MERRENTRY +0x94 机器错误异常返回地址 MERRERA +0x95 机器错误异常数据保存 MERRSAVE +0x98 高速缓存标签 CTAG +0x180+n (0≤n≤3) 直接映射配置窗口n DMWn +0x200+2n (0≤n≤31) 性能监测配置n PMCFGn +0x201+2n (0≤n≤31) 性能监测计数器n PMCNTn +0x300 内存读写监视点整体控制 MWPC +0x301 内存读写监视点整体状态 MWPS +0x310+8n (0≤n≤7) 内存读写监视点n配置1 MWPnCFG1 +0x311+8n (0≤n≤7) 内存读写监视点n配置2 MWPnCFG2 +0x312+8n (0≤n≤7) 内存读写监视点n配置3 MWPnCFG3 +0x313+8n (0≤n≤7) 内存读写监视点n配置4 MWPnCFG4 +0x380 取指监视点整体控制 FWPC +0x381 取指监视点整体状态 FWPS +0x390+8n (0≤n≤7) 取指监视点n配置1 FWPnCFG1 +0x391+8n (0≤n≤7) 取指监视点n配置2 FWPnCFG2 +0x392+8n (0≤n≤7) 取指监视点n配置3 FWPnCFG3 +0x393+8n (0≤n≤7) 取指监视点n配置4 FWPnCFG4 +0x500 调试寄存器 DBG +0x501 调试异常返回地址 DERA +0x502 调试数据保存 DSAVE +================= ==================================== ========== + +ERA，TLBRERA，MERRERA和DERA有时也分别称为EPC，TLBREPC，MERREPC和DEPC。 + +基础指令集 +========== + +指令格式 +-------- + +LoongArch的指令字长为32位，一共有9种基本指令格式（以及一些变体）: + +=========== ========================== +格式名称 指令构成 +=========== ========================== +2R Opcode + Rj + Rd +3R Opcode + Rk + Rj + Rd +4R Opcode + Ra + Rk + Rj + Rd +2RI8 Opcode + I8 + Rj + Rd +2RI12 Opcode + I12 + Rj + Rd +2RI14 Opcode + I14 + Rj + Rd +2RI16 Opcode + I16 + Rj + Rd +1RI21 Opcode + I21L + Rj + I21H +I26 Opcode + I26L + I26H +=========== ========================== + +Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是 +4R-type格式特有的附加操作数（寄存器）。I8/I12/I14/I16/I21/I26分别是8位/12位/14位/ +16位/21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位 +部分，所以你们在这里的格式描述中能够看到I21L/I21H和I26L/I26H这样带后缀的表述。 + +指令列表 +-------- + +为了简便起见，我们在此只罗列一下指令名称（助记符），需要详细信息请阅读 +:ref:`参考文献 ` 中的文档。 + +1. 算术运算指令:: + + ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D + SLT SLTU SLTI SLTUI + AND OR NOR XOR ANDN ORN ANDI ORI XORI + MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU + MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU + PCADDI PCADDU12I PCADDU18I + LU12I.W LU32I.D LU52I.D ADDU16I.D + +2. 移位运算指令:: + + SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W + SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D + +3. 位域操作指令:: + + EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D + BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D + REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D + MASKEQZ MASKNEZ + +4. 分支转移指令:: + + BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL + +5. 访存读写指令:: + + LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D + LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D + LDPTR.W LDPTR.D STPTR.W STPTR.D + PRELD PRELDX + +6. 原子操作指令:: + + LL.W SC.W LL.D SC.D + AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D + AMMAX.W AMMAX.D AMMIN.W AMMIN.D + +7. 栅障指令:: + + IBAR DBAR + +8. 特殊指令:: + + SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D + ASRTLE.D ASRTGT.D + +9. 特权指令:: + + CSRRD CSRWR CSRXCHG + IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D + CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE + +虚拟内存 +======== + +LoongArch可以使用直接映射虚拟内存和分页映射虚拟内存。 + +直接映射虚拟内存通过CSR.DMWn（n=0~3）来进行配置，虚拟地址（VA）和物理地址（PA） +之间有简单的映射关系:: + + VA = PA + 固定偏移 + +分页映射的虚拟地址（VA）和物理地址（PA）有任意的映射关系，这种关系记录在TLB和页 +表中。LoongArch的TLB包括一个全相联的MTLB（Multiple Page Size TLB，多样页大小TLB） +和一个组相联的STLB（Single Page Size TLB，单一页大小TLB）。 + +缺省状态下，LA32的整个虚拟地址空间配置如下： + +============ =========================== =========================== +区段名 地址范围 属性 +============ =========================== =========================== +``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` 分页映射, 可缓存, PLV0~3 +``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` 直接映射, 非缓存, PLV0 +``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` 直接映射, 可缓存, PLV0 +``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` 分页映射, 可缓存, PLV0 +============ =========================== =========================== + +用户态（PLV3）只能访问UVRANGE，对于直接映射的KPRANGE0和KPRANGE1，将虚拟地址的第 +30~31位清零就等于物理地址。例如：物理地址0x00001000对应的非缓存直接映射虚拟地址 +是0x80001000，而其可缓存直接映射虚拟地址是0xA0001000。 + +缺省状态下，LA64的整个虚拟地址空间配置如下： + +============ ====================== ================================== +区段名 地址范围 属性 +============ ====================== ================================== +``XUVRANGE`` ``0x0000000000000000 - 分页映射, 可缓存, PLV0~3 + 0x3FFFFFFFFFFFFFFF`` +``XSPRANGE`` ``0x4000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0 + 0x7FFFFFFFFFFFFFFF`` +``XKPRANGE`` ``0x8000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0 + 0xBFFFFFFFFFFFFFFF`` +``XKVRANGE`` ``0xC000000000000000 - 分页映射, 可缓存, PLV0 + 0xFFFFFFFFFFFFFFFF`` +============ ====================== ================================== + +用户态（PLV3）只能访问XUVRANGE，对于直接映射的XSPRANGE和XKPRANGE，将虚拟地址的第 +60~63位清零就等于物理地址，而其缓存属性是通过虚拟地址的第60~61位配置的（0表示强序 +非缓存，1表示一致可缓存，2表示弱序非缓存）。 + +目前，我们仅用XKPRANGE来进行直接映射，XSPRANGE保留给以后用。 + +此处给出一个直接映射的例子：物理地址0x00000000_00001000的强序非缓存直接映射虚拟地址 +（在XKPRANGE中）是0x80000000_00001000，其一致可缓存直接映射虚拟地址（在XKPRANGE中） +是0x90000000_00001000，而其弱序非缓存直接映射虚拟地址（在XKPRANGE中）是0xA0000000_ +00001000。 + +Loongson与LoongArch的关系 +========================= + +LoongArch是一种RISC指令集架构（ISA），不同于现存的任何一种ISA，而Loongson（即龙 +芯）是一个处理器家族。龙芯包括三个系列：Loongson-1（龙芯1号）是32位处理器系列， +Loongson-2（龙芯2号）是低端64位处理器系列，而Loongson-3（龙芯3号）是高端64位处理 +器系列。旧的龙芯处理器基于MIPS架构，而新的龙芯处理器基于LoongArch架构。以龙芯3号 +为例：龙芯3A1000/3B1500/3A2000/3A3000/3A4000都是兼容MIPS的，而龙芯3A5000（以及将 +来的型号）都是基于LoongArch的。 + +.. _loongarch-references-zh_CN: + +参考文献 +======== + +Loongson官方网站（龙芯中科技术股份有限公司）： + + http://www.loongson.cn/ + +Loongson与LoongArch的开发者网站（软件与文档资源）： + + http://www.loongnix.cn/ + + https://github.com/loongson/ + + https://loongson.github.io/LoongArch-Documentation/ + +LoongArch指令集架构的文档： + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf （中文版） + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf （英文版） + +LoongArch的ELF psABI文档： + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf （中文版） + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf （英文版） + +Loongson与LoongArch的Linux内核源码仓库： + + https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst new file mode 100644 index 000000000000..f1e9ab18206c --- /dev/null +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst @@ -0,0 +1,157 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/loongarch/irq-chip-model.rst +:Translator: Huacai Chen + +================================== +LoongArch的IRQ芯片模型（层级关系） +================================== + +目前，基于LoongArch的处理器（如龙芯3A5000）只能与LS7A芯片组配合工作。LoongArch计算机 +中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（ +Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、 +HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中 +断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。 + +CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的 +全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中 +断控制器（在配套芯片组里面）。这些中断控制器（或者说IRQ芯片）以一种层次树的组织形式 +级联在一起，一共有两种层级关系模型（传统IRQ模型和扩展IRQ模型）。 + +传统IRQ模型 +=========== + +在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC， +CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/ +PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC:: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ + | + +---------+ +-------+ + | LIOINTC | <-- | UARTs | + +---------+ +-------+ + ^ + | + +-----------+ + | HTVECINTC | + +-----------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + +扩展IRQ模型 +=========== + +在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC， +CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/ +PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC:: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ +-------+ + | EIOINTC | | LIOINTC | <-- | UARTs | + +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + +ACPI相关的定义 +============== + +CPUINTC:: + + ACPI_MADT_TYPE_CORE_PIC; + struct acpi_madt_core_pic; + enum acpi_madt_core_pic_version; + +LIOINTC:: + + ACPI_MADT_TYPE_LIO_PIC; + struct acpi_madt_lio_pic; + enum acpi_madt_lio_pic_version; + +EIOINTC:: + + ACPI_MADT_TYPE_EIO_PIC; + struct acpi_madt_eio_pic; + enum acpi_madt_eio_pic_version; + +HTVECINTC:: + + ACPI_MADT_TYPE_HT_PIC; + struct acpi_madt_ht_pic; + enum acpi_madt_ht_pic_version; + +PCH-PIC:: + + ACPI_MADT_TYPE_BIO_PIC; + struct acpi_madt_bio_pic; + enum acpi_madt_bio_pic_version; + +PCH-MSI:: + + ACPI_MADT_TYPE_MSI_PIC; + struct acpi_madt_msi_pic; + enum acpi_madt_msi_pic_version; + +PCH-LPC:: + + ACPI_MADT_TYPE_LPC_PIC; + struct acpi_madt_lpc_pic; + enum acpi_madt_lpc_pic_version; + +参考文献 +======== + +龙芯3A5000的文档： + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (中文版) + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (英文版) + +龙芯LS7A芯片组的文档： + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (中文版) + + https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (英文版) + +.. note:: + - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其 + 中断控制逻辑； + - LIOINTC：即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”； + - EIOINTC：即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”； + - HTVECINTC：即《龙芯3A5000处理器使用手册》第14.3节所描述的“HyperTransport中断”； + - PCH-PIC/PCH-MSI：即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”； + - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。 diff --git a/Documentation/translations/zh_CN/loongarch/booting.rst b/Documentation/translations/zh_CN/loongarch/booting.rst deleted file mode 100644 index fb6440c438f0..000000000000 --- a/Documentation/translations/zh_CN/loongarch/booting.rst +++ /dev/null @@ -1,48 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/loongarch/booting.rst - -:翻译: - - 司延腾 Yanteng Si - -==================== -启动 Linux/LoongArch -==================== - -:作者: 司延腾 -:日期: 2022年11月18日 - -BootLoader传递给内核的信息 -========================== - -LoongArch支持ACPI和FDT启动，需要传递给内核的信息包括memmap、initrd、cmdline、可 -选的ACPI/FDT表等。 - -内核在 `kernel_entry` 入口处被传递以下参数: - - - a0 = efi_boot: `efi_boot` 是一个标志，表示这个启动环境是否完全符合UEFI - 的要求。 - - - a1 = cmdline: `cmdline` 是一个指向内核命令行的指针。 - - - a2 = systemtable: `systemtable` 指向EFI的系统表，在这个阶段涉及的所有 - 指针都是物理地址。 - -Linux/LoongArch内核镜像文件头 -============================= - -内核镜像是EFI镜像。作为PE文件，它们有一个64字节的头部结构体，如下所示:: - - u32 MZ_MAGIC /* "MZ", MS-DOS 头 */ - u32 res0 = 0 /* 保留 */ - u64 kernel_entry /* 内核入口点 */ - u64 _end - _text /* 内核镜像有效大小 */ - u64 load_offset /* 加载内核镜像相对内存起始地址的偏移量 */ - u64 res1 = 0 /* 保留 */ - u64 res2 = 0 /* 保留 */ - u64 res3 = 0 /* 保留 */ - u32 LINUX_PE_MAGIC /* 魔术数 */ - u32 pe_header - _head /* 到PE头的偏移量 */ diff --git a/Documentation/translations/zh_CN/loongarch/features.rst b/Documentation/translations/zh_CN/loongarch/features.rst deleted file mode 100644 index 3886e635ec06..000000000000 --- a/Documentation/translations/zh_CN/loongarch/features.rst +++ /dev/null @@ -1,8 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/loongarch/features.rst -:Translator: Huacai Chen - -.. kernel-feat:: $srctree/Documentation/features loongarch diff --git a/Documentation/translations/zh_CN/loongarch/index.rst b/Documentation/translations/zh_CN/loongarch/index.rst deleted file mode 100644 index 0273a08342f7..000000000000 --- a/Documentation/translations/zh_CN/loongarch/index.rst +++ /dev/null @@ -1,27 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/loongarch/index.rst -:Translator: Huacai Chen - -================= -LoongArch体系结构 -================= - -.. toctree:: - :maxdepth: 2 - :numbered: - - introduction - booting - irq-chip-model - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/loongarch/introduction.rst b/Documentation/translations/zh_CN/loongarch/introduction.rst deleted file mode 100644 index 470c38ae2caf..000000000000 --- a/Documentation/translations/zh_CN/loongarch/introduction.rst +++ /dev/null @@ -1,353 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/loongarch/introduction.rst -:Translator: Huacai Chen - -============= -LoongArch介绍 -============= - -LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集 -包括一个精简32位版（LA32R）、一个标准32位版（LA32S）、一个64位版（LA64）。 -LoongArch定义了四个特权级（PLV0~PLV3），其中PLV0是最高特权级，用于内核；而PLV3 -是最低特权级，用于应用程序。本文档介绍了LoongArch的寄存器、基础指令集、虚拟内 -存以及其他一些主题。 - -寄存器 -====== - -LoongArch的寄存器包括通用寄存器（GPRs）、浮点寄存器（FPRs）、向量寄存器（VRs） -和用于特权模式（PLV0）的控制状态寄存器（CSRs）。 - -通用寄存器 ----------- - -LoongArch包括32个通用寄存器（ ``$r0`` ~ ``$r31`` ），LA32中每个寄存器为32位宽， -LA64中每个寄存器为64位宽。 ``$r0`` 的内容总是固定为0，而其他寄存器在体系结构层面 -没有特殊功能。（ ``$r1`` 算是一个例外，在BL指令中固定用作链接返回寄存器。） - -内核使用了一套LoongArch寄存器约定，定义在LoongArch ELF psABI规范中，详细描述参见 -:ref:`参考文献 `: - -================= =============== =================== ========== -寄存器名 别名 用途 跨调用保持 -================= =============== =================== ========== -``$r0`` ``$zero`` 常量0 不使用 -``$r1`` ``$ra`` 返回地址 否 -``$r2`` ``$tp`` TLS/线程信息指针 不使用 -``$r3`` ``$sp`` 栈指针 是 -``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否 -``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否 -``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否 -``$r21`` ``$u0`` 每CPU变量基地址 不使用 -``$r22`` ``$fp`` 帧指针 是 -``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是 -================= =============== =================== ========== - -.. note:: - 注意： ``$r21`` 寄存器在ELF psABI中保留未使用，但是在Linux内核用于保 - 存每CPU变量基地址。该寄存器没有ABI命名，不过在内核中称为 ``$u0`` 。在 - 一些遗留代码中有时可能见到 ``$v0`` 和 ``$v1`` ，它们是 ``$a0`` 和 - ``$a1`` 的别名，属于已经废弃的用法。 - -浮点寄存器 ----------- - -当系统中存在FPU时，LoongArch有32个浮点寄存器（ ``$f0`` ~ ``$f31`` ）。在LA64 -的CPU核上，每个寄存器均为64位宽。 - -浮点寄存器的使用约定与LoongArch ELF psABI规范的描述相同： - -================= ================== =================== ========== -寄存器名 别名 用途 跨调用保持 -================= ================== =================== ========== -``$f0``-``$f7`` ``$fa0``-``$fa7`` 参数寄存器 否 -``$f0``-``$f1`` ``$fv0``-``$fv1`` 返回值 否 -``$f8``-``$f23`` ``$ft0``-``$ft15`` 临时寄存器 否 -``$f24``-``$f31`` ``$fs0``-``$fs7`` 静态寄存器 是 -================= ================== =================== ========== - -.. note:: - 注意：在一些遗留代码中有时可能见到 ``$fv0`` 和 ``$fv1`` ，它们是 - ``$fa0`` 和 ``$fa1`` 的别名，属于已经废弃的用法。 - - -向量寄存器 ----------- - -LoongArch现有两种向量扩展： - -- 128位向量扩展LSX（全称Loongson SIMD eXtention）， -- 256位向量扩展LASX（全称Loongson Advanced SIMD eXtention）。 - -LSX使用 ``$v0`` ~ ``$v31`` 向量寄存器，而LASX则使用 ``$x0`` ~ ``$x31`` 。 - -浮点寄存器和向量寄存器是复用的，比如：在一个实现了LSX和LASX的核上， ``$x0`` 的 -低128位与 ``$v0`` 共用， ``$v0`` 的低64位与 ``$f0`` 共用，其他寄存器依此类推。 - -控制状态寄存器 --------------- - -控制状态寄存器只能在特权模式（PLV0）下访问: - -================= ==================================== ========== -地址 全称描述 简称 -================= ==================================== ========== -0x0 当前模式信息 CRMD -0x1 异常前模式信息 PRMD -0x2 扩展部件使能 EUEN -0x3 杂项控制 MISC -0x4 异常配置 ECFG -0x5 异常状态 ESTAT -0x6 异常返回地址 ERA -0x7 出错(Faulting)虚拟地址 BADV -0x8 出错(Faulting)指令字 BADI -0xC 异常入口地址 EENTRY -0x10 TLB索引 TLBIDX -0x11 TLB表项高位 TLBEHI -0x12 TLB表项低位0 TLBELO0 -0x13 TLB表项低位1 TLBELO1 -0x18 地址空间标识符 ASID -0x19 低半地址空间页全局目录基址 PGDL -0x1A 高半地址空间页全局目录基址 PGDH -0x1B 页全局目录基址 PGD -0x1C 页表遍历控制低半部分 PWCL -0x1D 页表遍历控制高半部分 PWCH -0x1E STLB页大小 STLBPS -0x1F 缩减虚地址配置 RVACFG -0x20 CPU编号 CPUID -0x21 特权资源配置信息1 PRCFG1 -0x22 特权资源配置信息2 PRCFG2 -0x23 特权资源配置信息3 PRCFG3 -0x30+n (0≤n≤15) 数据保存寄存器 SAVEn -0x40 定时器编号 TID -0x41 定时器配置 TCFG -0x42 定时器值 TVAL -0x43 计时器补偿 CNTC -0x44 定时器中断清除 TICLR -0x60 LLBit相关控制 LLBCTL -0x80 实现相关控制1 IMPCTL1 -0x81 实现相关控制2 IMPCTL2 -0x88 TLB重填异常入口地址 TLBRENTRY -0x89 TLB重填异常出错(Faulting)虚地址 TLBRBADV -0x8A TLB重填异常返回地址 TLBRERA -0x8B TLB重填异常数据保存 TLBRSAVE -0x8C TLB重填异常表项低位0 TLBRELO0 -0x8D TLB重填异常表项低位1 TLBRELO1 -0x8E TLB重填异常表项高位 TLBEHI -0x8F TLB重填异常前模式信息 TLBRPRMD -0x90 机器错误控制 MERRCTL -0x91 机器错误信息1 MERRINFO1 -0x92 机器错误信息2 MERRINFO2 -0x93 机器错误异常入口地址 MERRENTRY -0x94 机器错误异常返回地址 MERRERA -0x95 机器错误异常数据保存 MERRSAVE -0x98 高速缓存标签 CTAG -0x180+n (0≤n≤3) 直接映射配置窗口n DMWn -0x200+2n (0≤n≤31) 性能监测配置n PMCFGn -0x201+2n (0≤n≤31) 性能监测计数器n PMCNTn -0x300 内存读写监视点整体控制 MWPC -0x301 内存读写监视点整体状态 MWPS -0x310+8n (0≤n≤7) 内存读写监视点n配置1 MWPnCFG1 -0x311+8n (0≤n≤7) 内存读写监视点n配置2 MWPnCFG2 -0x312+8n (0≤n≤7) 内存读写监视点n配置3 MWPnCFG3 -0x313+8n (0≤n≤7) 内存读写监视点n配置4 MWPnCFG4 -0x380 取指监视点整体控制 FWPC -0x381 取指监视点整体状态 FWPS -0x390+8n (0≤n≤7) 取指监视点n配置1 FWPnCFG1 -0x391+8n (0≤n≤7) 取指监视点n配置2 FWPnCFG2 -0x392+8n (0≤n≤7) 取指监视点n配置3 FWPnCFG3 -0x393+8n (0≤n≤7) 取指监视点n配置4 FWPnCFG4 -0x500 调试寄存器 DBG -0x501 调试异常返回地址 DERA -0x502 调试数据保存 DSAVE -================= ==================================== ========== - -ERA，TLBRERA，MERRERA和DERA有时也分别称为EPC，TLBREPC，MERREPC和DEPC。 - -基础指令集 -========== - -指令格式 --------- - -LoongArch的指令字长为32位，一共有9种基本指令格式（以及一些变体）: - -=========== ========================== -格式名称 指令构成 -=========== ========================== -2R Opcode + Rj + Rd -3R Opcode + Rk + Rj + Rd -4R Opcode + Ra + Rk + Rj + Rd -2RI8 Opcode + I8 + Rj + Rd -2RI12 Opcode + I12 + Rj + Rd -2RI14 Opcode + I14 + Rj + Rd -2RI16 Opcode + I16 + Rj + Rd -1RI21 Opcode + I21L + Rj + I21H -I26 Opcode + I26L + I26H -=========== ========================== - -Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是 -4R-type格式特有的附加操作数（寄存器）。I8/I12/I14/I16/I21/I26分别是8位/12位/14位/ -16位/21位/26位的立即数。其中较长的21位和26位立即数在指令字中被分割为高位部分与低位 -部分，所以你们在这里的格式描述中能够看到I21L/I21H和I26L/I26H这样带后缀的表述。 - -指令列表 --------- - -为了简便起见，我们在此只罗列一下指令名称（助记符），需要详细信息请阅读 -:ref:`参考文献 ` 中的文档。 - -1. 算术运算指令:: - - ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D - SLT SLTU SLTI SLTUI - AND OR NOR XOR ANDN ORN ANDI ORI XORI - MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU - MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU - PCADDI PCADDU12I PCADDU18I - LU12I.W LU32I.D LU52I.D ADDU16I.D - -2. 移位运算指令:: - - SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W - SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D - -3. 位域操作指令:: - - EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D - BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D - REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D - MASKEQZ MASKNEZ - -4. 分支转移指令:: - - BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL - -5. 访存读写指令:: - - LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D - LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D - LDPTR.W LDPTR.D STPTR.W STPTR.D - PRELD PRELDX - -6. 原子操作指令:: - - LL.W SC.W LL.D SC.D - AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D - AMMAX.W AMMAX.D AMMIN.W AMMIN.D - -7. 栅障指令:: - - IBAR DBAR - -8. 特殊指令:: - - SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D - ASRTLE.D ASRTGT.D - -9. 特权指令:: - - CSRRD CSRWR CSRXCHG - IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D - CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE - -虚拟内存 -======== - -LoongArch可以使用直接映射虚拟内存和分页映射虚拟内存。 - -直接映射虚拟内存通过CSR.DMWn（n=0~3）来进行配置，虚拟地址（VA）和物理地址（PA） -之间有简单的映射关系:: - - VA = PA + 固定偏移 - -分页映射的虚拟地址（VA）和物理地址（PA）有任意的映射关系，这种关系记录在TLB和页 -表中。LoongArch的TLB包括一个全相联的MTLB（Multiple Page Size TLB，多样页大小TLB） -和一个组相联的STLB（Single Page Size TLB，单一页大小TLB）。 - -缺省状态下，LA32的整个虚拟地址空间配置如下： - -============ =========================== =========================== -区段名 地址范围 属性 -============ =========================== =========================== -``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` 分页映射, 可缓存, PLV0~3 -``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` 直接映射, 非缓存, PLV0 -``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` 直接映射, 可缓存, PLV0 -``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` 分页映射, 可缓存, PLV0 -============ =========================== =========================== - -用户态（PLV3）只能访问UVRANGE，对于直接映射的KPRANGE0和KPRANGE1，将虚拟地址的第 -30~31位清零就等于物理地址。例如：物理地址0x00001000对应的非缓存直接映射虚拟地址 -是0x80001000，而其可缓存直接映射虚拟地址是0xA0001000。 - -缺省状态下，LA64的整个虚拟地址空间配置如下： - -============ ====================== ================================== -区段名 地址范围 属性 -============ ====================== ================================== -``XUVRANGE`` ``0x0000000000000000 - 分页映射, 可缓存, PLV0~3 - 0x3FFFFFFFFFFFFFFF`` -``XSPRANGE`` ``0x4000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0 - 0x7FFFFFFFFFFFFFFF`` -``XKPRANGE`` ``0x8000000000000000 - 直接映射, 可缓存 / 非缓存, PLV0 - 0xBFFFFFFFFFFFFFFF`` -``XKVRANGE`` ``0xC000000000000000 - 分页映射, 可缓存, PLV0 - 0xFFFFFFFFFFFFFFFF`` -============ ====================== ================================== - -用户态（PLV3）只能访问XUVRANGE，对于直接映射的XSPRANGE和XKPRANGE，将虚拟地址的第 -60~63位清零就等于物理地址，而其缓存属性是通过虚拟地址的第60~61位配置的（0表示强序 -非缓存，1表示一致可缓存，2表示弱序非缓存）。 - -目前，我们仅用XKPRANGE来进行直接映射，XSPRANGE保留给以后用。 - -此处给出一个直接映射的例子：物理地址0x00000000_00001000的强序非缓存直接映射虚拟地址 -（在XKPRANGE中）是0x80000000_00001000，其一致可缓存直接映射虚拟地址（在XKPRANGE中） -是0x90000000_00001000，而其弱序非缓存直接映射虚拟地址（在XKPRANGE中）是0xA0000000_ -00001000。 - -Loongson与LoongArch的关系 -========================= - -LoongArch是一种RISC指令集架构（ISA），不同于现存的任何一种ISA，而Loongson（即龙 -芯）是一个处理器家族。龙芯包括三个系列：Loongson-1（龙芯1号）是32位处理器系列， -Loongson-2（龙芯2号）是低端64位处理器系列，而Loongson-3（龙芯3号）是高端64位处理 -器系列。旧的龙芯处理器基于MIPS架构，而新的龙芯处理器基于LoongArch架构。以龙芯3号 -为例：龙芯3A1000/3B1500/3A2000/3A3000/3A4000都是兼容MIPS的，而龙芯3A5000（以及将 -来的型号）都是基于LoongArch的。 - -.. _loongarch-references-zh_CN: - -参考文献 -======== - -Loongson官方网站（龙芯中科技术股份有限公司）： - - http://www.loongson.cn/ - -Loongson与LoongArch的开发者网站（软件与文档资源）： - - http://www.loongnix.cn/ - - https://github.com/loongson/ - - https://loongson.github.io/LoongArch-Documentation/ - -LoongArch指令集架构的文档： - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-CN.pdf （中文版） - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.02-EN.pdf （英文版） - -LoongArch的ELF psABI文档： - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-CN.pdf （中文版） - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.00-EN.pdf （英文版） - -Loongson与LoongArch的Linux内核源码仓库： - - https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git diff --git a/Documentation/translations/zh_CN/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/loongarch/irq-chip-model.rst deleted file mode 100644 index fb5d23b49ed5..000000000000 --- a/Documentation/translations/zh_CN/loongarch/irq-chip-model.rst +++ /dev/null @@ -1,157 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/loongarch/irq-chip-model.rst -:Translator: Huacai Chen - -================================== -LoongArch的IRQ芯片模型（层级关系） -================================== - -目前，基于LoongArch的处理器（如龙芯3A5000）只能与LS7A芯片组配合工作。LoongArch计算机 -中的中断控制器（即IRQ芯片）包括CPUINTC（CPU Core Interrupt Controller）、LIOINTC（ -Legacy I/O Interrupt Controller）、EIOINTC（Extended I/O Interrupt Controller）、 -HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中 -断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。 - -CPUINTC是一种CPU内部的每个核本地的中断控制器，LIOINTC/EIOINTC/HTVECINTC是CPU内部的 -全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中 -断控制器（在配套芯片组里面）。这些中断控制器（或者说IRQ芯片）以一种层次树的组织形式 -级联在一起，一共有两种层级关系模型（传统IRQ模型和扩展IRQ模型）。 - -传统IRQ模型 -=========== - -在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC， -CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/ -PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC:: - - +-----+ +---------+ +-------+ - | IPI | --> | CPUINTC | <-- | Timer | - +-----+ +---------+ +-------+ - ^ - | - +---------+ +-------+ - | LIOINTC | <-- | UARTs | - +---------+ +-------+ - ^ - | - +-----------+ - | HTVECINTC | - +-----------+ - ^ ^ - | | - +---------+ +---------+ - | PCH-PIC | | PCH-MSI | - +---------+ +---------+ - ^ ^ ^ - | | | - +---------+ +---------+ +---------+ - | PCH-LPC | | Devices | | Devices | - +---------+ +---------+ +---------+ - ^ - | - +---------+ - | Devices | - +---------+ - -扩展IRQ模型 -=========== - -在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC， -CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/ -PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC:: - - +-----+ +---------+ +-------+ - | IPI | --> | CPUINTC | <-- | Timer | - +-----+ +---------+ +-------+ - ^ ^ - | | - +---------+ +---------+ +-------+ - | EIOINTC | | LIOINTC | <-- | UARTs | - +---------+ +---------+ +-------+ - ^ ^ - | | - +---------+ +---------+ - | PCH-PIC | | PCH-MSI | - +---------+ +---------+ - ^ ^ ^ - | | | - +---------+ +---------+ +---------+ - | PCH-LPC | | Devices | | Devices | - +---------+ +---------+ +---------+ - ^ - | - +---------+ - | Devices | - +---------+ - -ACPI相关的定义 -============== - -CPUINTC:: - - ACPI_MADT_TYPE_CORE_PIC; - struct acpi_madt_core_pic; - enum acpi_madt_core_pic_version; - -LIOINTC:: - - ACPI_MADT_TYPE_LIO_PIC; - struct acpi_madt_lio_pic; - enum acpi_madt_lio_pic_version; - -EIOINTC:: - - ACPI_MADT_TYPE_EIO_PIC; - struct acpi_madt_eio_pic; - enum acpi_madt_eio_pic_version; - -HTVECINTC:: - - ACPI_MADT_TYPE_HT_PIC; - struct acpi_madt_ht_pic; - enum acpi_madt_ht_pic_version; - -PCH-PIC:: - - ACPI_MADT_TYPE_BIO_PIC; - struct acpi_madt_bio_pic; - enum acpi_madt_bio_pic_version; - -PCH-MSI:: - - ACPI_MADT_TYPE_MSI_PIC; - struct acpi_madt_msi_pic; - enum acpi_madt_msi_pic_version; - -PCH-LPC:: - - ACPI_MADT_TYPE_LPC_PIC; - struct acpi_madt_lpc_pic; - enum acpi_madt_lpc_pic_version; - -参考文献 -======== - -龙芯3A5000的文档： - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (中文版) - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (英文版) - -龙芯LS7A芯片组的文档： - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (中文版) - - https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (英文版) - -.. note:: - - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其 - 中断控制逻辑； - - LIOINTC：即《龙芯3A5000处理器使用手册》第11.1节所描述的“传统I/O中断”； - - EIOINTC：即《龙芯3A5000处理器使用手册》第11.2节所描述的“扩展I/O中断”； - - HTVECINTC：即《龙芯3A5000处理器使用手册》第14.3节所描述的“HyperTransport中断”； - - PCH-PIC/PCH-MSI：即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”； - - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。 diff --git a/MAINTAINERS b/MAINTAINERS index 66582e300406..e481db8bd937 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12232,8 +12232,8 @@ R: WANG Xuerui L: loongarch@lists.linux.dev S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git -F: Documentation/loongarch/ -F: Documentation/translations/zh_CN/loongarch/ +F: Documentation/arch/loongarch/ +F: Documentation/translations/zh_CN/arch/loongarch/ F: arch/loongarch/ F: drivers/*/*loongarch* diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 09e422da482f..b2192f6cd1ed 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -566,7 +566,7 @@ config IRQ_LOONGARCH_CPU help Support for the LoongArch CPU Interrupt Controller. For details of irq chip hierarchy on LoongArch platforms please read the document - Documentation/loongarch/irq-chip-model.rst. + Documentation/arch/loongarch/irq-chip-model.rst. config LOONGSON_LIOINTC bool "Loongson Local I/O Interrupt Controller" -- cgit v1.2.3 From ec62a746b65363f6078fb1eefc7faffe1a4cdc38 Mon Sep 17 00:00:00 2001 From: Costa Shulyupin Date: Tue, 25 Jul 2023 07:38:03 +0300 Subject: docs: move mips under arch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit and fix all in-tree references. Architecture-specific documentation is being moved into Documentation/arch/ as a way of cleaning up the top-level documentation directory and making the docs hierarchy more closely match the source hierarchy. Signed-off-by: Costa Shulyupin Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20230725043835.2249678-1-costa.shul@redhat.com --- Documentation/arch/index.rst | 2 +- Documentation/arch/mips/booting.rst | 28 +++++++++ Documentation/arch/mips/features.rst | 3 + Documentation/arch/mips/index.rst | 21 +++++++ Documentation/arch/mips/ingenic-tcu.rst | 71 +++++++++++++++++++++ .../devicetree/bindings/timer/ingenic,tcu.yaml | 2 +- Documentation/mips/booting.rst | 28 --------- Documentation/mips/features.rst | 3 - Documentation/mips/index.rst | 21 ------- Documentation/mips/ingenic-tcu.rst | 71 --------------------- Documentation/translations/zh_CN/arch/index.rst | 2 +- .../translations/zh_CN/arch/mips/booting.rst | 34 ++++++++++ .../translations/zh_CN/arch/mips/features.rst | 13 ++++ .../translations/zh_CN/arch/mips/index.rst | 29 +++++++++ .../translations/zh_CN/arch/mips/ingenic-tcu.rst | 72 ++++++++++++++++++++++ Documentation/translations/zh_CN/mips/booting.rst | 34 ---------- Documentation/translations/zh_CN/mips/features.rst | 13 ---- Documentation/translations/zh_CN/mips/index.rst | 29 --------- .../translations/zh_CN/mips/ingenic-tcu.rst | 72 ---------------------- MAINTAINERS | 2 +- 20 files changed, 275 insertions(+), 275 deletions(-) create mode 100644 Documentation/arch/mips/booting.rst create mode 100644 Documentation/arch/mips/features.rst create mode 100644 Documentation/arch/mips/index.rst create mode 100644 Documentation/arch/mips/ingenic-tcu.rst delete mode 100644 Documentation/mips/booting.rst delete mode 100644 Documentation/mips/features.rst delete mode 100644 Documentation/mips/index.rst delete mode 100644 Documentation/mips/ingenic-tcu.rst create mode 100644 Documentation/translations/zh_CN/arch/mips/booting.rst create mode 100644 Documentation/translations/zh_CN/arch/mips/features.rst create mode 100644 Documentation/translations/zh_CN/arch/mips/index.rst create mode 100644 Documentation/translations/zh_CN/arch/mips/ingenic-tcu.rst delete mode 100644 Documentation/translations/zh_CN/mips/booting.rst delete mode 100644 Documentation/translations/zh_CN/mips/features.rst delete mode 100644 Documentation/translations/zh_CN/mips/index.rst delete mode 100644 Documentation/translations/zh_CN/mips/ingenic-tcu.rst (limited to 'MAINTAINERS') diff --git a/Documentation/arch/index.rst b/Documentation/arch/index.rst index 4b6b1beebad6..dc59634c5fbb 100644 --- a/Documentation/arch/index.rst +++ b/Documentation/arch/index.rst @@ -15,7 +15,7 @@ implementation. ia64/index loongarch/index m68k/index - ../mips/index + mips/index nios2/index openrisc/index parisc/index diff --git a/Documentation/arch/mips/booting.rst b/Documentation/arch/mips/booting.rst new file mode 100644 index 000000000000..7c18a4eab48b --- /dev/null +++ b/Documentation/arch/mips/booting.rst @@ -0,0 +1,28 @@ +.. SPDX-License-Identifier: GPL-2.0 + +BMIPS DeviceTree Booting +------------------------ + + Some bootloaders only support a single entry point, at the start of the + kernel image. Other bootloaders will jump to the ELF start address. + Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, + so the first instruction immediately jumps to kernel_entry(). + + Similar to the arch/arm case (b), a DT-aware bootloader is expected to + set up the following registers: + + a0 : 0 + + a1 : 0xffffffff + + a2 : Physical pointer to the device tree block (defined in chapter + II) in RAM. The device tree can be located anywhere in the first + 512MB of the physical address space (0x00000000 - 0x1fffffff), + aligned on a 64 bit boundary. + + Legacy bootloaders do not use this convention, and they do not pass in a + DT block. In this case, Linux will look for a builtin DTB, selected via + CONFIG_DT_*. + + This convention is defined for 32-bit systems only, as there are not + currently any 64-bit BMIPS implementations. diff --git a/Documentation/arch/mips/features.rst b/Documentation/arch/mips/features.rst new file mode 100644 index 000000000000..1973d729b29a --- /dev/null +++ b/Documentation/arch/mips/features.rst @@ -0,0 +1,3 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/arch/mips/index.rst b/Documentation/arch/mips/index.rst new file mode 100644 index 000000000000..037f85a08fe3 --- /dev/null +++ b/Documentation/arch/mips/index.rst @@ -0,0 +1,21 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=========================== +MIPS-specific Documentation +=========================== + +.. toctree:: + :maxdepth: 2 + :numbered: + + booting + ingenic-tcu + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/arch/mips/ingenic-tcu.rst b/Documentation/arch/mips/ingenic-tcu.rst new file mode 100644 index 000000000000..2ce4cb1314dc --- /dev/null +++ b/Documentation/arch/mips/ingenic-tcu.rst @@ -0,0 +1,71 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================== +Ingenic JZ47xx SoCs Timer/Counter Unit hardware +=============================================== + +The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function +hardware block. It features up to eight channels, that can be used as +counters, timers, or PWM. + +- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all + have eight channels. + +- JZ4725B introduced a separate channel, called Operating System Timer + (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is + 64-bit. + +- Each one of the TCU channels has its own clock, which can be reparented to three + different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. + + - The watchdog and OST hardware blocks also feature a TCSR register with the same + format in their register space. + - The TCU registers used to gate/ungate can also gate/ungate the watchdog and + OST clocks. + +- Each TCU channel works in one of two modes: + + - mode TCU1: channels cannot work in sleep mode, but are easier to + operate. + - mode TCU2: channels can work in sleep mode, but the operation is a bit + more complicated than with TCU1 channels. + +- The mode of each TCU channel depends on the SoC used: + + - On the oldest SoCs (up to JZ4740), all of the eight channels operate in + TCU1 mode. + - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. + - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the + others operate as TCU1. + +- Each channel can generate an interrupt. Some channels share an interrupt + line, some don't, and this changes between SoC versions: + + - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their + own interrupt line; channels 2-7 share the last interrupt line. + - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one + interrupt line; the OST uses the last interrupt line. + - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; + channels 0-4 and (if eight channels) 6-7 all share one interrupt line; + the OST uses the last interrupt line. + +Implementation +============== + +The functionalities of the TCU hardware are spread across multiple drivers: + +=========== ===== +clocks drivers/clk/ingenic/tcu.c +interrupts drivers/irqchip/irq-ingenic-tcu.c +timers drivers/clocksource/ingenic-timer.c +OST drivers/clocksource/ingenic-ost.c +PWM drivers/pwm/pwm-jz4740.c +watchdog drivers/watchdog/jz4740_wdt.c +=========== ===== + +Because various functionalities of the TCU that belong to different drivers +and frameworks can be controlled from the same registers, all of these +drivers access their registers through the same regmap. + +For more information regarding the devicetree bindings of the TCU drivers, +have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml index 2d14610888a7..585b5f5217c4 100644 --- a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml +++ b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml @@ -8,7 +8,7 @@ title: Ingenic SoCs Timer/Counter Unit (TCU) description: | For a description of the TCU hardware and drivers, have a look at - Documentation/mips/ingenic-tcu.rst. + Documentation/arch/mips/ingenic-tcu.rst. maintainers: - Paul Cercueil diff --git a/Documentation/mips/booting.rst b/Documentation/mips/booting.rst deleted file mode 100644 index 7c18a4eab48b..000000000000 --- a/Documentation/mips/booting.rst +++ /dev/null @@ -1,28 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -BMIPS DeviceTree Booting ------------------------- - - Some bootloaders only support a single entry point, at the start of the - kernel image. Other bootloaders will jump to the ELF start address. - Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, - so the first instruction immediately jumps to kernel_entry(). - - Similar to the arch/arm case (b), a DT-aware bootloader is expected to - set up the following registers: - - a0 : 0 - - a1 : 0xffffffff - - a2 : Physical pointer to the device tree block (defined in chapter - II) in RAM. The device tree can be located anywhere in the first - 512MB of the physical address space (0x00000000 - 0x1fffffff), - aligned on a 64 bit boundary. - - Legacy bootloaders do not use this convention, and they do not pass in a - DT block. In this case, Linux will look for a builtin DTB, selected via - CONFIG_DT_*. - - This convention is defined for 32-bit systems only, as there are not - currently any 64-bit BMIPS implementations. diff --git a/Documentation/mips/features.rst b/Documentation/mips/features.rst deleted file mode 100644 index 1973d729b29a..000000000000 --- a/Documentation/mips/features.rst +++ /dev/null @@ -1,3 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/mips/index.rst b/Documentation/mips/index.rst deleted file mode 100644 index 037f85a08fe3..000000000000 --- a/Documentation/mips/index.rst +++ /dev/null @@ -1,21 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -=========================== -MIPS-specific Documentation -=========================== - -.. toctree:: - :maxdepth: 2 - :numbered: - - booting - ingenic-tcu - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/mips/ingenic-tcu.rst b/Documentation/mips/ingenic-tcu.rst deleted file mode 100644 index 2ce4cb1314dc..000000000000 --- a/Documentation/mips/ingenic-tcu.rst +++ /dev/null @@ -1,71 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -=============================================== -Ingenic JZ47xx SoCs Timer/Counter Unit hardware -=============================================== - -The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function -hardware block. It features up to eight channels, that can be used as -counters, timers, or PWM. - -- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all - have eight channels. - -- JZ4725B introduced a separate channel, called Operating System Timer - (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is - 64-bit. - -- Each one of the TCU channels has its own clock, which can be reparented to three - different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. - - - The watchdog and OST hardware blocks also feature a TCSR register with the same - format in their register space. - - The TCU registers used to gate/ungate can also gate/ungate the watchdog and - OST clocks. - -- Each TCU channel works in one of two modes: - - - mode TCU1: channels cannot work in sleep mode, but are easier to - operate. - - mode TCU2: channels can work in sleep mode, but the operation is a bit - more complicated than with TCU1 channels. - -- The mode of each TCU channel depends on the SoC used: - - - On the oldest SoCs (up to JZ4740), all of the eight channels operate in - TCU1 mode. - - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. - - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the - others operate as TCU1. - -- Each channel can generate an interrupt. Some channels share an interrupt - line, some don't, and this changes between SoC versions: - - - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their - own interrupt line; channels 2-7 share the last interrupt line. - - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one - interrupt line; the OST uses the last interrupt line. - - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; - channels 0-4 and (if eight channels) 6-7 all share one interrupt line; - the OST uses the last interrupt line. - -Implementation -============== - -The functionalities of the TCU hardware are spread across multiple drivers: - -=========== ===== -clocks drivers/clk/ingenic/tcu.c -interrupts drivers/irqchip/irq-ingenic-tcu.c -timers drivers/clocksource/ingenic-timer.c -OST drivers/clocksource/ingenic-ost.c -PWM drivers/pwm/pwm-jz4740.c -watchdog drivers/watchdog/jz4740_wdt.c -=========== ===== - -Because various functionalities of the TCU that belong to different drivers -and frameworks can be controlled from the same registers, all of these -drivers access their registers through the same regmap. - -For more information regarding the devicetree bindings of the TCU drivers, -have a look at Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/Documentation/translations/zh_CN/arch/index.rst b/Documentation/translations/zh_CN/arch/index.rst index d4c1c729dde2..e3d273d7d599 100644 --- a/Documentation/translations/zh_CN/arch/index.rst +++ b/Documentation/translations/zh_CN/arch/index.rst @@ -8,7 +8,7 @@ .. toctree:: :maxdepth: 2 - ../mips/index + mips/index arm64/index ../riscv/index openrisc/index diff --git a/Documentation/translations/zh_CN/arch/mips/booting.rst b/Documentation/translations/zh_CN/arch/mips/booting.rst new file mode 100644 index 000000000000..485b57e0ca0b --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/booting.rst @@ -0,0 +1,34 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/booting.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_booting: + +BMIPS设备树引导 +------------------------ + + 一些bootloaders只支持在内核镜像开始地址处的单一入口点。而其它 + bootloaders将跳转到ELF的开始地址处。两种方案都支持的；因为 + CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, 所以第一条指令 + 会立即跳转到kernel_entry()入口处执行。 + + 与arch/arm情况(b)类似，dt感知的引导加载程序需要设置以下寄存器: + + a0 : 0 + + a1 : 0xffffffff + + a2 : RAM中指向设备树块的物理指针(在chapterII中定义)。 + 设备树可以位于前512MB物理地址空间(0x00000000 - + 0x1fffffff)的任何位置，以64位边界对齐。 + + 传统bootloaders不会使用这样的约定，并且它们不传入DT块。 + 在这种情况下，Linux将通过选中CONFIG_DT_*查找DTB。 + + 以上约定只在32位系统中定义，因为目前没有任何64位的BMIPS实现。 diff --git a/Documentation/translations/zh_CN/arch/mips/features.rst b/Documentation/translations/zh_CN/arch/mips/features.rst new file mode 100644 index 000000000000..da1b956e4a40 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/features.rst @@ -0,0 +1,13 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/features.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_features: + +.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/translations/zh_CN/arch/mips/index.rst b/Documentation/translations/zh_CN/arch/mips/index.rst new file mode 100644 index 000000000000..2a34217119ea --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/index.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/index.rst + +:翻译: + + 司延腾 Yanteng Si + +=========================== +MIPS特性文档 +=========================== + +.. toctree:: + :maxdepth: 2 + :numbered: + + booting + ingenic-tcu + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/arch/mips/ingenic-tcu.rst b/Documentation/translations/zh_CN/arch/mips/ingenic-tcu.rst new file mode 100644 index 000000000000..3d599a36b571 --- /dev/null +++ b/Documentation/translations/zh_CN/arch/mips/ingenic-tcu.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../../disclaimer-zh_CN.rst + +:Original: Documentation/arch/mips/ingenic-tcu.rst + +:翻译: + + 司延腾 Yanteng Si + +.. _cn_ingenic-tcu: + +=============================================== +君正 JZ47xx SoC定时器/计数器硬件单元 +=============================================== + +君正 JZ47xx SoC中的定时器/计数器单元(TCU)是一个多功能硬件块。它有多达 +8个通道，可以用作计数器，计时器，或脉冲宽度调制器。 + +- JZ4725B, JZ4750, JZ4755 只有６个TCU通道。其它SoC都有８个通道。 + +- JZ4725B引入了一个独立的通道，称为操作系统计时器(OST)。这是一个32位可 + 编程定时器。在JZ4760B及以上型号上，它是64位的。 + +- 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟 + 源（pclk、ext、rtc）、开关以及分频。 + + - 看门狗和OST硬件模块在它们的寄存器空间中也有相同形式的TCSR寄存器。 + - 用于关闭/开启的 TCU 寄存器也可以关闭/开启看门狗和 OST 时钟。 + +- 每个TCU通道在两种模式的其中一种模式下运行： + + - 模式 TCU1：通道无法在睡眠模式下运行，但更易于操作。 + - 模式 TCU2：通道可以在睡眠模式下运行，但操作比 TCU1 通道复杂一些。 + +- 每个 TCU 通道的模式取决于使用的SoC： + + - 在最老的SoC（高于JZ4740），八个通道都运行在TCU1模式。 + - 在 JZ4725B，通道5运行在TCU2,其它通道则运行在TCU1。 + - 在最新的SoC（JZ4750及之后），通道1-2运行在TCU2，其它通道则运行 + 在TCU1。 + +- 每个通道都可以生成中断。有些通道共享一条中断线，而有些没有，其在SoC型 + 号之间的变更： + + - 在很老的SoC（JZ4740及更低），通道0和通道1有它们自己的中断线；通 + 道2-7共享最后一条中断线。 + - 在 JZ4725B，通道0有它自己的中断线；通道1-5共享一条中断线；OST + 使用最后一条中断线。 + - 在比较新的SoC（JZ4750及以后），通道5有它自己的中断线；通 + 道0-4和（如果是8通道）6-7全部共享一条中断线；OST使用最后一条中 + 断线。 + +实现 +==== + +TCU硬件的功能分布在多个驱动程序： + +============== =================================== +时钟 drivers/clk/ingenic/tcu.c +中断 drivers/irqchip/irq-ingenic-tcu.c +定时器 drivers/clocksource/ingenic-timer.c +OST drivers/clocksource/ingenic-ost.c +脉冲宽度调制器 drivers/pwm/pwm-jz4740.c +看门狗 drivers/watchdog/jz4740_wdt.c +============== =================================== + +因为可以从相同的寄存器控制属于不同驱动程序和框架的TCU的各种功能，所以 +所有这些驱动程序都通过相同的控制总线通用接口访问它们的寄存器。 + +有关TCU驱动程序的设备树绑定的更多信息，请参阅: +Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/Documentation/translations/zh_CN/mips/booting.rst b/Documentation/translations/zh_CN/mips/booting.rst deleted file mode 100644 index e0bbd3f20862..000000000000 --- a/Documentation/translations/zh_CN/mips/booting.rst +++ /dev/null @@ -1,34 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/booting.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_booting: - -BMIPS设备树引导 ------------------------- - - 一些bootloaders只支持在内核镜像开始地址处的单一入口点。而其它 - bootloaders将跳转到ELF的开始地址处。两种方案都支持的；因为 - CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, 所以第一条指令 - 会立即跳转到kernel_entry()入口处执行。 - - 与arch/arm情况(b)类似，dt感知的引导加载程序需要设置以下寄存器: - - a0 : 0 - - a1 : 0xffffffff - - a2 : RAM中指向设备树块的物理指针(在chapterII中定义)。 - 设备树可以位于前512MB物理地址空间(0x00000000 - - 0x1fffffff)的任何位置，以64位边界对齐。 - - 传统bootloaders不会使用这样的约定，并且它们不传入DT块。 - 在这种情况下，Linux将通过选中CONFIG_DT_*查找DTB。 - - 以上约定只在32位系统中定义，因为目前没有任何64位的BMIPS实现。 diff --git a/Documentation/translations/zh_CN/mips/features.rst b/Documentation/translations/zh_CN/mips/features.rst deleted file mode 100644 index b61dab06ceaf..000000000000 --- a/Documentation/translations/zh_CN/mips/features.rst +++ /dev/null @@ -1,13 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/features.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_features: - -.. kernel-feat:: $srctree/Documentation/features mips diff --git a/Documentation/translations/zh_CN/mips/index.rst b/Documentation/translations/zh_CN/mips/index.rst deleted file mode 100644 index 192c6adbb72e..000000000000 --- a/Documentation/translations/zh_CN/mips/index.rst +++ /dev/null @@ -1,29 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/index.rst - -:翻译: - - 司延腾 Yanteng Si - -=========================== -MIPS特性文档 -=========================== - -.. toctree:: - :maxdepth: 2 - :numbered: - - booting - ingenic-tcu - - features - -.. only:: subproject and html - - Indices - ======= - - * :ref:`genindex` diff --git a/Documentation/translations/zh_CN/mips/ingenic-tcu.rst b/Documentation/translations/zh_CN/mips/ingenic-tcu.rst deleted file mode 100644 index ddbe149c517b..000000000000 --- a/Documentation/translations/zh_CN/mips/ingenic-tcu.rst +++ /dev/null @@ -1,72 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -.. include:: ../disclaimer-zh_CN.rst - -:Original: Documentation/mips/ingenic-tcu.rst - -:翻译: - - 司延腾 Yanteng Si - -.. _cn_ingenic-tcu: - -=============================================== -君正 JZ47xx SoC定时器/计数器硬件单元 -=============================================== - -君正 JZ47xx SoC中的定时器/计数器单元(TCU)是一个多功能硬件块。它有多达 -8个通道，可以用作计数器，计时器，或脉冲宽度调制器。 - -- JZ4725B, JZ4750, JZ4755 只有６个TCU通道。其它SoC都有８个通道。 - -- JZ4725B引入了一个独立的通道，称为操作系统计时器(OST)。这是一个32位可 - 编程定时器。在JZ4760B及以上型号上，它是64位的。 - -- 每个TCU通道都有自己的时钟源，可以通过 TCSR 寄存器设置通道的父级时钟 - 源（pclk、ext、rtc）、开关以及分频。 - - - 看门狗和OST硬件模块在它们的寄存器空间中也有相同形式的TCSR寄存器。 - - 用于关闭/开启的 TCU 寄存器也可以关闭/开启看门狗和 OST 时钟。 - -- 每个TCU通道在两种模式的其中一种模式下运行： - - - 模式 TCU1：通道无法在睡眠模式下运行，但更易于操作。 - - 模式 TCU2：通道可以在睡眠模式下运行，但操作比 TCU1 通道复杂一些。 - -- 每个 TCU 通道的模式取决于使用的SoC： - - - 在最老的SoC（高于JZ4740），八个通道都运行在TCU1模式。 - - 在 JZ4725B，通道5运行在TCU2,其它通道则运行在TCU1。 - - 在最新的SoC（JZ4750及之后），通道1-2运行在TCU2，其它通道则运行 - 在TCU1。 - -- 每个通道都可以生成中断。有些通道共享一条中断线，而有些没有，其在SoC型 - 号之间的变更： - - - 在很老的SoC（JZ4740及更低），通道0和通道1有它们自己的中断线；通 - 道2-7共享最后一条中断线。 - - 在 JZ4725B，通道0有它自己的中断线；通道1-5共享一条中断线；OST - 使用最后一条中断线。 - - 在比较新的SoC（JZ4750及以后），通道5有它自己的中断线；通 - 道0-4和（如果是8通道）6-7全部共享一条中断线；OST使用最后一条中 - 断线。 - -实现 -==== - -TCU硬件的功能分布在多个驱动程序： - -============== =================================== -时钟 drivers/clk/ingenic/tcu.c -中断 drivers/irqchip/irq-ingenic-tcu.c -定时器 drivers/clocksource/ingenic-timer.c -OST drivers/clocksource/ingenic-ost.c -脉冲宽度调制器 drivers/pwm/pwm-jz4740.c -看门狗 drivers/watchdog/jz4740_wdt.c -============== =================================== - -因为可以从相同的寄存器控制属于不同驱动程序和框架的TCU的各种功能，所以 -所有这些驱动程序都通过相同的控制总线通用接口访问它们的寄存器。 - -有关TCU驱动程序的设备树绑定的更多信息，请参阅: -Documentation/devicetree/bindings/timer/ingenic,tcu.yaml. diff --git a/MAINTAINERS b/MAINTAINERS index e481db8bd937..dccce01f3dc9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14161,7 +14161,7 @@ W: http://www.linux-mips.org/ Q: https://patchwork.kernel.org/project/linux-mips/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git F: Documentation/devicetree/bindings/mips/ -F: Documentation/mips/ +F: Documentation/arch/mips/ F: arch/mips/ F: drivers/platform/mips/ F: include/dt-bindings/mips/ -- cgit v1.2.3