From 1f6ccfff6314672743ad7252160654709e997a2a Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 13 May 2013 18:30:41 +0530 Subject: ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta --- arch/arc/include/asm/irqflags-arcv2.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arc/include/asm/irqflags-arcv2.h') diff --git a/arch/arc/include/asm/irqflags-arcv2.h b/arch/arc/include/asm/irqflags-arcv2.h index c946c56f141c..1eb41b00aac5 100644 --- a/arch/arc/include/asm/irqflags-arcv2.h +++ b/arch/arc/include/asm/irqflags-arcv2.h @@ -27,6 +27,9 @@ #define AUX_IRQ_SELECT 0x40b #define AUX_IRQ_ENABLE 0x40c +/* Was Intr taken in User Mode */ +#define AUX_IRQ_ACT_BIT_U 31 + /* 0 is highest level, but taken by FIRQs, if present in design */ #define ARCV2_IRQ_DEF_PRIO 0 -- cgit v1.2.3