From 368ccecd4e4a0ed8180ad76764fd6e6d516e151c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 15 Dec 2022 15:19:14 +0100 Subject: ARM: 9281/1: improve Cortex A8/A9 errata help text Document that !ARCH_MULTIPLATFORM is necessary because accessing the the errata workaround registers may not work in non-secure mode and mention that these erratas should be applied by the bootloader instead. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Arnd Bergmann Signed-off-by: Sebastian Reichel Signed-off-by: Russell King (Oracle) --- arch/arm/Kconfig | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43c7773b89ae..45af77e67973 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -661,7 +661,9 @@ config ARM_ERRATA_458693 hazard might then cause a processor deadlock. The workaround enables the L1 caching of the NEON accesses and disables the PLD instruction in the ACTLR register. Note that setting specific bits in the ACTLR - register may not be available in non-secure mode. + register may not be available in non-secure mode and thus is not + available on a multiplatform kernel. This should be applied by the + bootloader instead. config ARM_ERRATA_460075 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" @@ -674,7 +676,9 @@ config ARM_ERRATA_460075 and overwritten with stale memory contents from external memory. The workaround disables the write-allocate mode for the L2 cache via the ACTLR register. Note that setting specific bits in the ACTLR register - may not be available in non-secure mode. + may not be available in non-secure mode and thus is not available on + a multiplatform kernel. This should be applied by the bootloader + instead. config ARM_ERRATA_742230 bool "ARM errata: DMB operation may be faulty" @@ -687,7 +691,10 @@ config ARM_ERRATA_742230 ordering of the two writes. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which causes the DMB instruction to behave as a DSB, ensuring the correct behaviour of - the two writes. + the two writes. Note that setting specific bits in the diagnostics + register may not be available in non-secure mode and thus is not + available on a multiplatform kernel. This should be applied by the + bootloader instead. config ARM_ERRATA_742231 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" @@ -702,7 +709,10 @@ config ARM_ERRATA_742231 replaced from one of the CPUs at the same time as another CPU is accessing it. This workaround sets specific bits in the diagnostic register of the Cortex-A9 which reduces the linefill issuing - capabilities of the processor. + capabilities of the processor. Note that setting specific bits in the + diagnostics register may not be available in non-secure mode and thus + is not available on a multiplatform kernel. This should be applied by + the bootloader instead. config ARM_ERRATA_643719 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" @@ -739,7 +749,9 @@ config ARM_ERRATA_743622 register of the Cortex-A9 which disables the Store Buffer optimisation, preventing the defect from occurring. This has no visible impact on the overall performance or power consumption of the - processor. + processor. Note that setting specific bits in the diagnostics register + may not be available in non-secure mode and thus is not available on a + multiplatform kernel. This should be applied by the bootloader instead. config ARM_ERRATA_751472 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" @@ -751,6 +763,10 @@ config ARM_ERRATA_751472 completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. + Note that setting specific bits in the diagnostics register may + not be available in non-secure mode and thus is not available on + a multiplatform kernel. This should be applied by the bootloader + instead. config ARM_ERRATA_754322 bool "ARM errata: possible faulty MMU translations following an ASID switch" -- cgit v1.2.3 From 5eb6e280432ddc9b755193552f3a070da8d7455c Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Sun, 29 Jan 2023 15:49:07 +0100 Subject: ARM: 9289/1: Allow pre-ARMv5 builds with ld.lld 16.0.0 and newer Commit 6a7ee50f8f56 ("ARM: disallow pre-ARMv5 builds with ld.lld") prevented v4 or v4t kernels when ld.lld will link the kernel due to inserting unsupported blx instructions. ld.lld has been fixed in current main (16.0.0) to avoid inserting these instructions by inserting position independent thunks instead. Allow these configurations to be enabled when ld.lld 16.0.0 is used to link the kernel. Additionally, add a link to the upstream LLVM issue so that the reason for this dependency is clearly documented. Link: https://github.com/ClangBuiltLinux/linux/issues/964 Link: https://github.com/llvm/llvm-project/commit/6f9ff1beee9d12aca0c9caa9ae0051dc6d0a718c Suggested-by: Nick Desaulniers Tested-by: Arnd Bergmann Signed-off-by: Nathan Chancellor Signed-off-by: Russell King (Oracle) --- arch/arm/Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/Kconfig') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 45af77e67973..666a25d6147c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -345,14 +345,16 @@ comment "CPU Core family selection" config ARCH_MULTI_V4 bool "ARMv4 based platforms (FA526, StrongARM)" depends on !ARCH_MULTI_V6_V7 - depends on !LD_IS_LLD + # https://github.com/llvm/llvm-project/issues/50764 + depends on !LD_IS_LLD || LLD_VERSION >= 160000 select ARCH_MULTI_V4_V5 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) config ARCH_MULTI_V4T bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" depends on !ARCH_MULTI_V6_V7 - depends on !LD_IS_LLD + # https://github.com/llvm/llvm-project/issues/50764 + depends on !LD_IS_LLD || LLD_VERSION >= 160000 select ARCH_MULTI_V4_V5 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ -- cgit v1.2.3