From 83fb5b55cd0cf58038ad2caad02c70fc244d5c80 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 22 Nov 2022 16:06:20 -0600 Subject: arm64: dts: apple: Add t600x L1/L2 cache properties and nodes The t600x CPU nodes are missing the cache hierarchy information. The cache hierarchy on Arm can not be detected and needs to be described in DT. The OS scheduler can make use of this information for scheduling decisions. The cache size information is based on various articles about the processors. There's also an L3 system level cache (SLC). It's not described here because SLCs typically have some MMIO interface which would need to be described. Signed-off-by: Rob Herring Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t6002.dtsi | 51 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/apple/t600x-common.dtsi | 51 +++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) (limited to 'arch/arm64/boot/dts/apple') diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index 3b1677ba5262..731d61fbb05f 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -29,6 +29,9 @@ reg = <0x0 0x800>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_e11: cpu@801 { @@ -37,6 +40,9 @@ reg = <0x0 0x801>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_p20: cpu@10900 { @@ -45,6 +51,9 @@ reg = <0x0 0x10900>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p21: cpu@10901 { @@ -53,6 +62,9 @@ reg = <0x0 0x10901>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p22: cpu@10902 { @@ -61,6 +73,9 @@ reg = <0x0 0x10902>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p23: cpu@10903 { @@ -69,6 +84,9 @@ reg = <0x0 0x10903>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p30: cpu@10a00 { @@ -77,6 +95,9 @@ reg = <0x0 0x10a00>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p31: cpu@10a01 { @@ -85,6 +106,9 @@ reg = <0x0 0x10a01>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p32: cpu@10a02 { @@ -93,6 +117,9 @@ reg = <0x0 0x10a02>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p33: cpu@10a03 { @@ -101,6 +128,30 @@ reg = <0x0 0x10a03>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_4: l2-cache-4 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + }; + + l2_cache_5: l2-cache-5 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; }; }; diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/dts/apple/t600x-common.dtsi index f5fac1926a25..e2568d914719 100644 --- a/arch/arm64/boot/dts/apple/t600x-common.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-common.dtsi @@ -21,6 +21,9 @@ reg = <0x0 0x0>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_e01: cpu@1 { @@ -29,6 +32,9 @@ reg = <0x0 0x1>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_p00: cpu@10100 { @@ -37,6 +43,9 @@ reg = <0x0 0x10100>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p01: cpu@10101 { @@ -45,6 +54,9 @@ reg = <0x0 0x10101>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p02: cpu@10102 { @@ -53,6 +65,9 @@ reg = <0x0 0x10102>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p03: cpu@10103 { @@ -61,6 +76,9 @@ reg = <0x0 0x10103>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p10: cpu@10200 { @@ -69,6 +87,9 @@ reg = <0x0 0x10200>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p11: cpu@10201 { @@ -77,6 +98,9 @@ reg = <0x0 0x10201>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p12: cpu@10202 { @@ -85,6 +109,9 @@ reg = <0x0 0x10202>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p13: cpu@10203 { @@ -93,6 +120,30 @@ reg = <0x0 0x10203>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + }; + + l2_cache_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; }; }; -- cgit v1.2.3