From 7d7df014617ba8df7fbdacac54cafe0d13573dcb Mon Sep 17 00:00:00 2001 From: André Draszik Date: Tue, 26 Mar 2024 15:12:57 +0000 Subject: arm64: dts: exynos: gs101: reorder pinctrl-* properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Preferred order for these is pinctrl-0 pinctrl-names. Update the DTSI & DTS accordingly. Signed-off-by: André Draszik Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 55e6bcb3689e..5868c96c771f 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -393,8 +393,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; -- cgit v1.2.3 From 73618dfa705dc8f993a6829c895eaf5af8402ceb Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:12:58 +0000 Subject: arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinctrl nodes are coming from the shared gs101-pinctrl.dtsi, thus the pinctrl-0/names shall stay in dtsi. Move them. Reviewed-by: André Draszik Reviewed-by: Alim Akhtar Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-3-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 2 -- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 40de2b0aa086..6be15e990b65 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -103,8 +103,6 @@ }; &serial_0 { - pinctrl-0 = <&uart0_bus>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 5868c96c771f..a1aff219208a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -424,6 +424,8 @@ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; + pinctrl-0 = <&uart0_bus>; + pinctrl-names = "default"; samsung,uart-fifosize = <256>; status = "disabled"; }; -- cgit v1.2.3 From d978c70e8d4775c62db21f85947d12b4f874104a Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:12:59 +0000 Subject: arm64: dts: exynos: gs101: move pinctrl-* properties after clocks Move the pinctrl-* properties after clocks so that we keep alphabetic order and align with the other similar definitions. Reviewed-by: Alim Akhtar Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-4-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index a1aff219208a..cfb3ddc7f885 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -393,11 +393,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&hsi2c8_bus>; - pinctrl-names = "default"; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; status = "disabled"; }; }; @@ -473,11 +473,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&hsi2c12_bus>; - pinctrl-names = "default"; clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; clock-names = "hsi2c", "hsi2c_pclk"; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; status = "disabled"; }; }; -- cgit v1.2.3 From 028a87e91fcd8c485afcf8bd0d26ae34a0872438 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:13:00 +0000 Subject: arm64: dts: exynos: gs101: join lines close to 80 chars These lines fit 81 characters, which is pretty close to 80. Join the lines for better readability. Reviewed-by: Alim Akhtar Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index cfb3ddc7f885..690deca37e4f 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -374,8 +374,7 @@ }; usi8: usi@109700c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x109700c0 0x20>; ranges; #address-cells = <1>; @@ -403,8 +402,7 @@ }; usi_uart: usi@10a000c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10a000c0 0x20>; ranges; #address-cells = <1>; @@ -419,8 +417,7 @@ serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - interrupts = ; + interrupts = ; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; @@ -454,8 +451,7 @@ }; usi12: usi@10d500c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10d500c0 0x20>; ranges; #address-cells = <1>; -- cgit v1.2.3 From a45c3a9b1ef9571741d40bf10f22ce3c60bc5111 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:13:01 +0000 Subject: arm64: dts: exynos: gs101: define all PERIC USI nodes Universal Serial Interface (USI) supports three types of serial interface such as UART, SPI and I2C. Each protocol works independently. USI can be configured to work as one of these protocols. Define all the USI nodes from the PERIC blocks (USI0-14), in all their possible configurations. These blocks have the TX/RX FIFO depth of 64 bytes. Reviewed-by: Peter Griffin Reviewed-by: Alim Akhtar Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 769 +++++++++++++++++++++++++++ 1 file changed, 769 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 690deca37e4f..eddb6b326fde 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -373,6 +373,391 @@ interrupts = ; }; + usi1: usi@109000c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1000>; + status = "disabled"; + + hsi2c_1: i2c@10900000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_1: serial@10900000 { + compatible = "google,gs101-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart1_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_1: spi@10900000 { + compatible = "google,gs101-spi"; + reg = <0x10900000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@109100c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1004>; + status = "disabled"; + + hsi2c_2: i2c@10910000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@10910000 { + compatible = "google,gs101-uart"; + reg = <0x10910000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_2: spi@10910000 { + compatible = "google,gs101-spi"; + reg = <0x10910000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@109200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1008>; + status = "disabled"; + + hsi2c_3: i2c@10920000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@10920000 { + compatible = "google,gs101-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_3: spi@10920000 { + compatible = "google,gs101-spi"; + reg = <0x10920000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi4: usi@109300c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x100c>; + status = "disabled"; + + hsi2c_4: i2c@10930000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@10930000 { + compatible = "google,gs101-uart"; + reg = <0x10930000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_4: spi@10930000 { + compatible = "google,gs101-spi"; + reg = <0x10930000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@109400c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1010>; + status = "disabled"; + + hsi2c_5: i2c@10940000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@10940000 { + compatible = "google,gs101-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_5: spi@10940000 { + compatible = "google,gs101-spi"; + reg = <0x10940000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6: usi@109500c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1014>; + status = "disabled"; + + hsi2c_6: i2c@10950000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@10950000 { + compatible = "google,gs101-uart"; + reg = <0x10950000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_6: spi@10950000 { + compatible = "google,gs101-spi"; + reg = <0x10950000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi7: usi@109600c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1018>; + status = "disabled"; + + hsi2c_7: i2c@10960000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@10960000 { + compatible = "google,gs101-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_7: spi@10960000 { + compatible = "google,gs101-spi"; + reg = <0x10960000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + usi8: usi@109700c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x109700c0 0x20>; @@ -399,6 +784,33 @@ pinctrl-names = "default"; status = "disabled"; }; + + serial_8: serial@10970000 { + compatible = "google,gs101-uart"; + reg = <0x10970000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_8: spi@10970000 { + compatible = "google,gs101-spi"; + reg = <0x10970000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; }; usi_uart: usi@10a000c0 { @@ -428,6 +840,61 @@ }; }; + usi14: usi@10a200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10a200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1028>; + status = "disabled"; + + hsi2c_14: i2c@10a20000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10a20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@10a20000 { + compatible = "google,gs101-uart"; + reg = <0x10a20000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_14: spi@10a20000 { + compatible = "google,gs101-spi"; + reg = <0x10a20000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_peric1: clock-controller@10c00000 { compatible = "google,gs101-cmu-peric1"; reg = <0x10c00000 0x4000>; @@ -450,6 +917,226 @@ interrupts = ; }; + usi0: usi@10d100c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1000>; + status = "disabled"; + + hsi2c_0: i2c@10d10000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_usi0: serial@10d10000 { + compatible = "google,gs101-uart"; + reg = <0x10d10000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart0_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_0: spi@10d10000 { + compatible = "google,gs101-spi"; + reg = <0x10d10000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@10d200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1004>; + status = "disabled"; + + hsi2c_9: i2c@10d20000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@10d20000 { + compatible = "google,gs101-uart"; + reg = <0x10d20000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_9: spi@10d20000 { + compatible = "google,gs101-spi"; + reg = <0x10d20000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@10d300c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1008>; + status = "disabled"; + + hsi2c_10: i2c@10d30000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@10d30000 { + compatible = "google,gs101-uart"; + reg = <0x10d30000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_10: spi@10d30000 { + compatible = "google,gs101-spi"; + reg = <0x10d30000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@10d400c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x100c>; + status = "disabled"; + + hsi2c_11: i2c@10d40000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@10d40000 { + compatible = "google,gs101-uart"; + reg = <0x10d40000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_11: spi@10d40000 { + compatible = "google,gs101-spi"; + reg = <0x10d40000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + usi12: usi@10d500c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10d500c0 0x20>; @@ -476,6 +1163,88 @@ pinctrl-names = "default"; status = "disabled"; }; + + serial_12: serial@10d50000 { + compatible = "google,gs101-uart"; + reg = <0x10d50000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_12: spi@10d50000 { + compatible = "google,gs101-spi"; + reg = <0x10d50000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi13: usi@10d600c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1014>; + status = "disabled"; + + hsi2c_13: i2c@10d60000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@10d60000 { + compatible = "google,gs101-uart"; + reg = <0x10d60000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_13: spi@10d60000 { + compatible = "google,gs101-spi"; + reg = <0x10d60000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; }; pinctrl_hsi1: pinctrl@11840000 { -- cgit v1.2.3 From 4982a4a2092ee9f7334d8f119a6a15d8165f7a04 Mon Sep 17 00:00:00 2001 From: André Draszik Date: Fri, 26 Apr 2024 11:03:05 +0100 Subject: arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu-hsi0 clock controller. It feeds USB. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-2-2157da8b63e3@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index eddb6b326fde..9755a0bb70a1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1247,6 +1247,20 @@ }; }; + cmu_hsi0: clock-controller@11000000 { + compatible = "google,gs101-cmu-hsi0"; + reg = <0x11000000 0x4000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, + <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, + <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; + clock-names = "oscclk", "bus", "dpgtc", "usb31drd", + "usbdpdbg"; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; -- cgit v1.2.3 From 86124c76683e31033180f1d31e7543863ce6d850 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 29 Apr 2024 14:02:18 +0100 Subject: arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-2-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9755a0bb70a1..a0305555c4fd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1267,6 +1267,18 @@ interrupts = ; }; + cmu_hsi2: clock-controller@14400000 { + compatible = "google,gs101-cmu-hsi2"; + reg = <0x14400000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; -- cgit v1.2.3 From 14d15fcbe0f1fac5979a0b01160f3651340e38b4 Mon Sep 17 00:00:00 2001 From: André Draszik Date: Mon, 29 Apr 2024 11:35:49 +0100 Subject: arm64: dts: exynos: gs101: add USB & USB-phy nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for Google Tensor GS101. The USB 3.1 DRD controller has the following features: * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * DWC3 compatible * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-1-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index a0305555c4fd..e3b068c1a2c1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1261,6 +1261,47 @@ "usbdpdbg"; }; + usbdrd31_phy: phy@11100000 { + compatible = "google,gs101-usb31drd-phy"; + reg = <0x11100000 0x0100>, + <0x110f0000 0x0800>, + <0x110e0000 0x2800>; + reg-names = "phy", "pcs", "pma"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; + clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbdrd31: usb@11110000 { + compatible = "google,gs101-dwusb3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; + clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x11110000 0x10000>; + status = "disabled"; + + usbdrd31_dwc3: usb@0 { + compatible = "snps,dwc3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; + clock-names = "ref"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; -- cgit v1.2.3 From b5f5fe4b317c0fbda725a44d9c92d97930ad68e9 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:43 +0100 Subject: arm64: dts: exynos: gs101: Add the hsi2 sysreg node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin Reviewed-by: André Draszik Link: https://lore.kernel.org/r/20240430141445.2688499-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e3b068c1a2c1..9f7635a7928e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1320,6 +1320,12 @@ clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x10000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; -- cgit v1.2.3 From 4c65d7054b4ce8ceb30ba2b8aed90ceff6158d73 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:44 +0100 Subject: arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin Acked-by: André Draszik Link: https://lore.kernel.org/r/20240430141445.2688499-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9f7635a7928e..16e1c474e8dd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1332,6 +1332,42 @@ interrupts = ; }; + ufs_0: ufs@14700000 { + compatible = "google,gs101-ufs"; + reg = <0x14700000 0x200>, + <0x14701100 0x200>, + <0x14780000 0xa000>, + <0x14600000 0x100>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = ; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + clock-names = "core_clk", "sclk_unipro_main", "fmp", + "aclk", "pclk", "sysreg"; + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + pinctrl-names = "default"; + phys = <&ufs_0_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&sysreg_hsi2 0x710>; + status = "disabled"; + }; + + ufs_0_phy: phy@14704000 { + compatible = "google,gs101-ufs-phy"; + reg = <0x14704000 0x3000>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&ext_24_5m>; + clock-names = "ref_clk"; + status = "disabled"; + }; + cmu_apm: clock-controller@17400000 { compatible = "google,gs101-cmu-apm"; reg = <0x17400000 0x8000>; -- cgit v1.2.3 From 1665b303a00c1acb2fe126486c6256c755f0b7c4 Mon Sep 17 00:00:00 2001 From: André Draszik Date: Tue, 30 Apr 2024 10:49:46 +0100 Subject: arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-1-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 16e1c474e8dd..09f6b33cf5b4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1390,6 +1390,8 @@ pinctrl_gpio_alive: pinctrl@174d0000 { compatible = "google,gs101-pinctrl"; reg = <0x174d0000 0x00001000>; + clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; + clock-names = "pclk"; wakeup-interrupt-controller { compatible = "google,gs101-wakeup-eint", @@ -1401,6 +1403,8 @@ pinctrl_far_alive: pinctrl@174e0000 { compatible = "google,gs101-pinctrl"; reg = <0x174e0000 0x00001000>; + clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; + clock-names = "pclk"; wakeup-interrupt-controller { compatible = "google,gs101-wakeup-eint", -- cgit v1.2.3 From 42e3f188b238b7fb1c42dee8b4dc4107cbb321e2 Mon Sep 17 00:00:00 2001 From: André Draszik Date: Tue, 30 Apr 2024 10:49:47 +0100 Subject: arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-2-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 09f6b33cf5b4..878e05a865a0 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -370,6 +370,8 @@ pinctrl_peric0: pinctrl@10840000 { compatible = "google,gs101-pinctrl"; reg = <0x10840000 0x00001000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; + clock-names = "pclk"; interrupts = ; }; @@ -914,6 +916,8 @@ pinctrl_peric1: pinctrl@10c40000 { compatible = "google,gs101-pinctrl"; reg = <0x10c40000 0x00001000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; + clock-names = "pclk"; interrupts = ; }; -- cgit v1.2.3 From 8120dc4656aedf86c24e1b5776f84fdd9f8ece80 Mon Sep 17 00:00:00 2001 From: André Draszik Date: Tue, 30 Apr 2024 10:49:48 +0100 Subject: arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-3-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 878e05a865a0..9edda5b94abc 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1333,6 +1333,8 @@ pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; + clock-names = "pclk"; interrupts = ; }; -- cgit v1.2.3 From 4db286b0a29aa3576a401b637ac5910dac22117f Mon Sep 17 00:00:00 2001 From: André Draszik Date: Tue, 30 Apr 2024 10:49:49 +0100 Subject: arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinctrl instances hsi1, gsactrl, and gsacore need a clock for register access to work. Since we haven't implemented the relevant CMUs for the clocks required by these instances just add empty clocks for now so as to make the DT pass the validation checks. Once the clocks are implmented in the gs101 clock driver, these should be updated then. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot/dts/exynos/google/gs101.dtsi') diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9edda5b94abc..a66e996666b8 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1309,6 +1309,9 @@ pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; interrupts = ; }; @@ -1422,11 +1425,17 @@ pinctrl_gsactrl: pinctrl@17940000 { compatible = "google,gs101-pinctrl"; reg = <0x17940000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; }; pinctrl_gsacore: pinctrl@17a80000 { compatible = "google,gs101-pinctrl"; reg = <0x17a80000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; }; cmu_top: clock-controller@1e080000 { -- cgit v1.2.3