From 6196fe777513b0dc65c831bcec3adc678cfce6f6 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 18 Dec 2023 15:23:12 +0100 Subject: arm64: dts: imx8qxp: add GPU nodes Add the DT node for the GPU core found on the i.MX8QXP. etnaviv-gpu 53100000.gpu: model: GC7000, revision: 6214 [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0 Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi new file mode 100644 index 000000000000..9b8a44aa63d6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +#include + +gpu0_subsys: bus@53000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53000000 0x0 0x53000000 0x1000000>; + + gpu_3d0: gpu@53100000 { + compatible = "vivante,gc"; + reg = <0x53100000 0x40000>; + interrupts = ; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + }; +}; -- cgit v1.2.3