From f217d94fc632fece2a41030c2eebc4ed34a48b2a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:55 +0200 Subject: arm64: dts: microchip: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts/microchip') diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b..6f7651b06478 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,8 @@ }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; -- cgit v1.2.3