From d8a6c3b3427618dc7441ec9eb180405ec30f3413 Mon Sep 17 00:00:00 2001 From: James Tai Date: Tue, 12 Nov 2019 15:45:22 +0000 Subject: arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Device Trees for Realtek RTD1619 SoC family, RTD1619 SoC and Realtek Mjolnir EVB. Signed-off-by: James Tai [AF: Renamed r-bus node, modified UART comments, style cleanups] Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/Makefile | 2 + arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts | 43 +++++++ arch/arm64/boot/dts/realtek/rtd1619.dtsi | 12 ++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 159 ++++++++++++++++++++++++ 4 files changed, 216 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1619.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd16xx.dtsi (limited to 'arch/arm64/boot/dts/realtek') diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index 55690b14b98a..54bd02d11c02 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb + +dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts new file mode 100644 index 000000000000..44dd67e04335 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1619.dtsi" + +/ { + compatible = "realtek,mjolnir", "realtek,rtd1619"; + model = "Realtek Mjolnir EVB"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; +}; + +/* debug console (J1) */ +&uart0 { + status = "okay"; +}; + +/* M.2 slot (CON4) */ +&uart1 { + status = "disabled"; +}; + +/* GPIO connector (T1) */ +&uart2 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1619.dtsi b/arch/arm64/boot/dts/realtek/rtd1619.dtsi new file mode 100644 index 000000000000..e52bf708b04e --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1619.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619 SoC + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include "rtd16xx.dtsi" + +/ { + compatible = "realtek,rtd1619"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi new file mode 100644 index 000000000000..c7bbf2c7bb7c --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD16xx SoC family + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + l2: l2-cache { + compatible = "cache"; + next-level-cache = <&l3>; + + }; + + l3: l3-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + arm_pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, + <&cpu3>, <&cpu4>, <&cpu5>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "osc27M"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x98000000 0x98000000 0x68000000>; + + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + uart0: serial0@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <27000000>; + status = "disabled"; + }; + + uart1: serial1@1b200 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b200 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; + + uart2: serial2@1b400 { + compatible = "snps,dw-apb-uart"; + reg = <0x1b400 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + reg = <0xff100000 0x10000>, + <0xff140000 0xc0000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; -- cgit v1.2.3