From 5ec06904310da6441097c8f2d6e3fb196f42bca1 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 2 Aug 2022 13:44:55 +0300 Subject: arm64: dts: ti: k3-am64-main: Add GPMC memory controller node The GPMC is a unified memory controller dedicated for interfacing with external memory devices like - Asynchronous SRAM-like memories and ASICs - Asynchronous, synchronous, and page mode burst NOR flash - NAND flash - Pseudo-SRAM devices Signed-off-by: Roger Quadros Signed-off-by: Vignesh Raghavendra Reviewed-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220802104456.11069-2-rogerq@kernel.org --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64/boot/dts/ti/k3-am64-main.dtsi') diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 744629cb6725..14238bac71e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1328,4 +1328,23 @@ status = "disabled"; /* Used by OP-TEE */ }; }; + + gpmc0: memory-controller@3b000000 { + compatible = "ti,am64-gpmc"; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 80 0>; + clock-names = "fck"; + reg = <0x00 0x03b000000 0x00 0x400>, + <0x00 0x050000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = ; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; }; -- cgit v1.2.3