From 53072ba67e534ddd208697d3465004738f1d4d61 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 15 Sep 2022 17:52:55 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS Move including the rzg2ul-smarc-som.dtsi from the carrier board rzg2ul-smarc.dtsi to the actual RZ/G2UL SMARC EVK board dts r9a07g043u11-smarc.dts. Also move the SW_SW0_DEV_SEL and SW_ET0_EN_N macros to board dts as they are used by SoM and carrier board DTS/I. This is in preparation of re-using the SoM and carrier board DTSIs for RZ/Five SMARC EVK. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220915165256.352843-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 12 ++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 11 ----------- 2 files changed, 12 insertions(+), 11 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 121e55282d18..059885a01ede 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -6,7 +6,19 @@ */ /dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on the SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + #include "r9a07g043.dtsi" +#include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index f9835c12023e..2a1331ed1a5c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -5,17 +5,6 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ -/* - * DIP-Switch SW1 setting - * 1 : High; 0: Low - * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) - * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) - * Please change below macros according to SW1 setting - */ -#define SW_SW0_DEV_SEL 1 -#define SW_ET0_EN_N 1 - -#include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" -- cgit v1.2.3