From 6de298ff13a807d12300bd616c6d3039987e6e87 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 23 Jun 2023 02:27:48 -0500 Subject: arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram sram@ffe00000: 'ranges' is a required property sram@ffe00000: '#size-cells' is a required property sram@ffe00000: '#address-cells' is a required property Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +++ arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 3 +++ 2 files changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 41c9eb51d0ee..55abc578e0ec 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -331,6 +331,9 @@ ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xffe00000 0x100000>; }; pdma: dma-controller@ffda0000 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index f9674cc46764..34e65a9cae61 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -336,6 +336,9 @@ ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xffe00000 0x40000>; }; pdma: dma-controller@ffda0000 { -- cgit v1.2.3 From 5dad11fa36c088b10dc14688451e1205e2580dc4 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sat, 24 Jun 2023 10:10:12 -0500 Subject: arm64: dts: socfpga: stratix10: fix dtbs_check warning for usbphy soc: usbphy@0: 'anyOf' conditional failed, one must be fixed: Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 55abc578e0ec..1c846f13539c 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -487,12 +487,6 @@ status = "disabled"; }; - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - usb0: usb@ffb00000 { compatible = "snps,dwc2"; reg = <0xffb00000 0x40000>; @@ -639,4 +633,9 @@ }; }; }; + + usbphy0: usbphy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; }; -- cgit v1.2.3 From b2c62c39567ccd3315076c542b73f29e38d50aaa Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sun, 25 Jun 2023 14:12:56 -0500 Subject: arm64: dts: stratix10/agilex/n5x: fix dtbs_check warning for memory node Although, we expect the bootloader to full memory details but passing empty values can give warning, so add a default value. memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 4 ++-- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 4 ++-- arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts | 4 ++-- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 4 ++-- arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts | 4 ++-- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 4 ++-- 7 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 38ae674f2f02..b7b50db174ca 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -38,10 +38,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; ref_033v: regulator-v-ref { diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index ede99dcc0558..12beed7e7769 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -38,10 +38,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; ref_033v: regulator-v-ref { diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts index a8db58573954..ff413f8e3b07 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -29,7 +29,7 @@ linux,initrd-end = <0x125c8324>; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts index 6231a69204b1..1a32840c74e0 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts @@ -20,10 +20,10 @@ stdout-path = "serial0:115200n8"; }; - memory@0 { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; soc { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 07c3f8876613..80e6864fb051 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -37,10 +37,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts index 51f83f96ec65..0f9020bd0c52 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts @@ -37,10 +37,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 08c088571270..b3325d72ae1f 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -19,10 +19,10 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; soc { -- cgit v1.2.3 From c91e8f3373fe0d4f59c8fa39c9c4225ad1919927 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sun, 25 Jun 2023 15:12:40 -0500 Subject: arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr The bindings expect "altr,rst-mgr" as a fallback in the rstmgr compatible: rstmgr@ffd11000: compatible: 'oneOf' conditional failed, one must be fixed: ['altr,stratix10-rst-mgr'] is too short 'altr,rst-mgr' was expected Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 34e65a9cae61..fc047aef4911 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -376,9 +376,9 @@ }; rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; reg = <0xffd11000 0x100>; + #reset-cells = <1>; }; smmu: iommu@fa000000 { -- cgit v1.2.3 From e141277e326b81bc40ed67cc98ced0e2650f84b9 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 3 Jul 2023 16:36:27 +0800 Subject: arm64: dts: agilex/stratix10: Updated QSPI Flash layout for UBIFS Non-UBIFS related boot and fpga data should be stored in qspi_boot (mtd0) while keeping the rootfs with UBIFS in the root partition "mtd1". Thus, update the QSPI flash layout to support UBIFS in the mtd root partition. Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Kah Jing Lee Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 8 ++++---- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index b7b50db174ca..df34e390631b 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -202,12 +202,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x04200000>; }; - qspi_rootfs: partition@3FE0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + root: partition@4200000 { + label = "Root Filesystem - UBIFS"; + reg = <0x04200000 0x0BE00000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 80e6864fb051..053690657675 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -128,12 +128,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x04200000>; }; - qspi_rootfs: partition@3FE0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + root: partition@4200000 { + label = "Root Filesystem - UBIFS"; + reg = <0x04200000 0x0BE00000>; }; }; }; -- cgit v1.2.3 From 774acd59a2f281aacda12b3de223c35f8a897313 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 23 Jun 2023 00:38:12 -0500 Subject: arm64: dts: socfpga: n5x/stratix10: fix dtbs_check warning for partitions flash@0: partitions: Unevaluated properties are not allowed ('partition@3FE0000' was unexpected) Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 4 ++-- arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 12beed7e7769..bd6f78e0fe2f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -103,9 +103,9 @@ status = "okay"; flash@0 { + reg = <0>; #address-cells = <1>; #size-cells = <1>; - reg = <0>; nand-bus-width = <16>; partition@0 { @@ -194,7 +194,7 @@ reg = <0x0 0x03FE0000>; }; - qspi_rootfs: partition@3FE0000 { + qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; reg = <0x03FE0000 0x0C020000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index b3325d72ae1f..5ddfdff37c25 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -109,7 +109,7 @@ reg = <0x0 0x03FE0000>; }; - qspi_rootfs: partition@3FE0000 { + qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; reg = <0x03FE0000 0x0C020000>; }; -- cgit v1.2.3 From 331085a423b271a2dd940b3073a576744e72da7d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 27 Jun 2023 16:59:42 -0500 Subject: arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb" The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is the same as the "ahb" reset on a standard stmmac ethernet. commit ("843f603762a5 dt-bindings: net: snps,dwmac: Add 'ahb' reset/reset-name") documented the second reset signal as 'ahb' instead of 'stmmaceth-ocp'. Change the reset-names of the SoCFPGA DWMAC driver to 'ahb'. In order not to break ABI, we will keep support in thedwmac-socfpga driver to still make use of "stmmaceth-ocp". This also fixes the dtbs_check warning: ethernet@ff802000: reset-names:1: 'ahb' was expected Signed-off-by: Dinh Nguyen --- v2: update commit message to further describe the reason for the change --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 6 +++--- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 +++--- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 72c55e5187ca..f36063c57c7f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -440,7 +440,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -460,7 +460,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -480,7 +480,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 1c846f13539c..439497ab967d 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -153,7 +153,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; @@ -171,7 +171,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; @@ -189,7 +189,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index fc047aef4911..d3adb6a130ae 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -158,7 +158,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -176,7 +176,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -194,7 +194,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; -- cgit v1.2.3 From 2d599bc43813cbcceeb6b0bfe864671ab517c207 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Tue, 1 Aug 2023 09:02:34 +0800 Subject: arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA Add the initial device tree files for Intel Agilex5 SoCFPGA platform. Reviewed-by: Dinh Nguyen Signed-off-by: Niravkumar L Rabara Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 468 +++++++++++++++++++++ .../arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 39 ++ 3 files changed, 508 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index c2a723838344..d39cfb723f5b 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,5 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex5_socdk.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi new file mode 100644 index 000000000000..dcdaf7064953 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Intel Corporation + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +/ { + compatible = "intel,socfpga-agilex5"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x2000000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a76"; + reg = <0x200>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a76"; + reg = <0x300>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: interrupt-controller@1d000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x1d000000 0 0x10000>, + <0x0 0x1d060000 0 0x100000>; + ranges; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells =<2>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + + its: msi-controller@1d040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x1d040000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + /* Clock tree 5 main sources*/ + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + usbphy0: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + interrupt-parent = <&intc>; + + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; + + i2c0: i2c@10c02800 { + compatible = "snps,designware-i2c"; + reg = <0x10c02800 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@10c02900 { + compatible = "snps,designware-i2c"; + reg = <0x10c02900 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@10c02a00 { + compatible = "snps,designware-i2c"; + reg = <0x10c02a00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@10c02b00 { + compatible = "snps,designware-i2c"; + reg = <0x10c02b00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@10c02c00 { + compatible = "snps,designware-i2c"; + reg = <0x10c02c00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i3c0: i3c-master@10da0000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da0000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = ; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + i3c1: i3c-master@10da1000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da1000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = ; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + gpio1: gpio@10c03300 { + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03300 0x100>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + nand: nand-controller@10b80000 { + compatible = "cdns,hp-nfc"; + reg = <0x10b80000 0x10000>, + <0x10840000 0x10000>; + reg-names = "reg", "sdma"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; + cdns,board-delay-ps = <4830>; + status = "disabled"; + }; + + ocram: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0x80000>; + ranges = <0 0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + dmac0: dma-controller@10db0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x10db0000 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + }; + + dmac1: dma-controller@10dc0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x10dc0000 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + }; + + rst: rstmgr@10d11000 { + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; + reg = <0x10d11000 0x1000>; + #reset-cells = <1>; + }; + + spi0: spi@10da4000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x10da4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + resets = <&rst SPIM0_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names ="tx", "rx"; + status = "disabled"; + + }; + + spi1: spi@10da5000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x10da5000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + resets = <&rst SPIM1_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0x10d12000 0x500>; + }; + + timer0: timer0@10c03000 { + compatible = "snps,dw-apb-timer"; + reg = <0x10c03000 0x100>; + interrupts = ; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer1: timer1@10c03100 { + compatible = "snps,dw-apb-timer"; + reg = <0x10c03100 0x100>; + interrupts = ; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer2: timer2@10d00000 { + compatible = "snps,dw-apb-timer"; + reg = <0x10d00000 0x100>; + interrupts = ; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer3: timer3@10d00100 { + compatible = "snps,dw-apb-timer"; + reg = <0x10d00100 0x100>; + interrupts = ; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + uart0: serial@10c02000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + uart1: serial@10c02100 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02100 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + usb0: usb@10b00000 { + compatible = "snps,dwc2"; + reg = <0x10b00000 0x40000>; + interrupts = ; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; + clock-names = "otg"; + status = "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible = "snps,dw-wdt"; + reg = <0x10d00200 0x100>; + interrupts = ; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible = "snps,dw-wdt"; + reg = <0x10d00300 0x100>; + interrupts = ; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible = "snps,dw-wdt"; + reg = <0x10d00400 0x100>; + interrupts = ; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible = "snps,dw-wdt"; + reg = <0x10d00500 0x100>; + interrupts = ; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog4: watchdog@10d00600 { + compatible = "snps,dw-wdt"; + reg = <0x10d00600 0x100>; + interrupts = ; + resets = <&rst WATCHDOG4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + qspi: spi@108d2000 { + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + reg = <0x108d2000 0x100>, + <0x10900000 0x100000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts new file mode 100644 index 000000000000..c533e5a3a610 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK"; + compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.2.3