From c42d12ea105f67b0f137f1e52d5c59d13fe12b1f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 14 Dec 2023 08:43:17 +0100 Subject: arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts The USB DP/DM HS PHY interrupts need to be provided by the PDC interrupt controller in order to be able to wake the system up from low-power states and to be able to detect disconnect events, which requires triggering on falling edges. A recent commit updated the trigger type but failed to change the interrupt provider as required. This leads to the current Linux driver failing to probe instead of printing an error during suspend and USB wakeup not working as intended. Fixes: de3b3de30999 ("arm64: dts: qcom: sdm670: fix USB wakeup interrupt types") Fixes: 07c8ded6e373 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Cc: stable@vger.kernel.org # 6.2 Cc: Richard Acayan Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Tested-by: Richard Acayan Link: https://lore.kernel.org/r/20231214074319.11023-2-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 303082fd25b8..2038141f896f 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1320,10 +1320,10 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts = , - , - , - ; + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; -- cgit v1.2.3 From 047b2edc35b8db22354b4fba37818b548fc18896 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 14 Dec 2023 08:43:18 +0100 Subject: arm64: dts: qcom: sdm670: fix USB SS wakeup The USB SS PHY interrupt needs to be provided by the PDC interrupt controller in order to be able to wake the system up from low-power states. Fixes: 07c8ded6e373 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Cc: stable@vger.kernel.org # 6.2 Cc: Richard Acayan Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Tested-by: Richard Acayan Link: https://lore.kernel.org/r/20231214074319.11023-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 2038141f896f..4d7b77a23159 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1321,7 +1321,7 @@ assigned-clock-rates = <19200000>, <150000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", -- cgit v1.2.3 From 0afa885d42d05d30161ab8eab1ebacd993edb82b Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 14 Dec 2023 08:43:19 +0100 Subject: arm64: dts: qcom: sc8180x: fix USB SS wakeup The USB SS PHY interrupt needs to be provided by the PDC interrupt controller in order to be able to wake the system up from low-power states. Fixes: b080f53a8f44 ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes") Cc: stable@vger.kernel.org # 6.5 Cc: Vinod Koul Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231214074319.11023-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index fe761d6d0dd3..25e41d195374 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2554,7 +2554,7 @@ compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", @@ -2628,7 +2628,7 @@ resets = <&gcc GCC_USB30_SEC_BCR>; power-domains = <&gcc USB30_SEC_GDSC>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", -- cgit v1.2.3 From 827f5fc8d912203c1f971e47d61130b13c6820ba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Dec 2023 15:38:33 +0100 Subject: arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent The SDHCI hosts on SC7280 are cache-coherent, just like on most fairly recent Qualcomm SoCs. Mark them as such. Fixes: 298c81a7d44f ("arm64: dts: qcom: sc7280: Add nodes for eMMC and SD card") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231218-topic-7280_dmac_sdhci-v1-1-97af7efd64a1@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ff1e07171dc4..83b5b76ba179 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1000,6 +1000,7 @@ bus-width = <8>; supports-cqe; + dma-coherent; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; @@ -3458,6 +3459,7 @@ operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; + dma-coherent; qcom,dll-config = <0x0007642c>; -- cgit v1.2.3 From d336355492e4ab8c1fd78e582077146e065d1924 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Dec 2023 16:06:56 +0100 Subject: arm64: dts: qcom: x1e80100: align mem timer size cells with bindings The ARMv7 memory mapped architected timer bindings expect MMIO sizes up to 32-bit. Keep 64-bit addressing but change the size of memory mapping to 32-bit (size-cells=1) and adjust the ranges to match this. This fixes dtbs_check warnings like: x1e80100-qcp.dtb: timer@17800000: #size-cells:0:0: 1 was expected Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20231218150656.72892-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index da691e2f3209..6f75fc342ceb 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3418,12 +3418,12 @@ reg = <0 0x17800000 0 0x1000>; #address-cells = <2>; - #size-cells = <2>; - ranges; + #size-cells = <1>; + ranges = <0 0 0 0 0x20000000>; frame@17801000 { - reg = <0 0x17801000 0 0x1000>, - <0 0x17802000 0 0x1000>; + reg = <0 0x17801000 0x1000>, + <0 0x17802000 0x1000>; interrupts = , ; @@ -3432,7 +3432,7 @@ }; frame@17803000 { - reg = <0 0x17803000 0 0x1000>; + reg = <0 0x17803000 0x1000>; interrupts = ; @@ -3442,7 +3442,7 @@ }; frame@17805000 { - reg = <0 0x17805000 0 0x1000>; + reg = <0 0x17805000 0x1000>; interrupts = ; @@ -3452,7 +3452,7 @@ }; frame@17807000 { - reg = <0 0x17807000 0 0x1000>; + reg = <0 0x17807000 0x1000>; interrupts = ; @@ -3462,7 +3462,7 @@ }; frame@17809000 { - reg = <0 0x17809000 0 0x1000>; + reg = <0 0x17809000 0x1000>; interrupts = ; @@ -3472,7 +3472,7 @@ }; frame@1780b000 { - reg = <0 0x1780b000 0 0x1000>; + reg = <0 0x1780b000 0x1000>; interrupts = ; @@ -3482,7 +3482,7 @@ }; frame@1780d000 { - reg = <0 0x1780d000 0 0x1000>; + reg = <0 0x1780d000 0x1000>; interrupts = ; -- cgit v1.2.3 From 5c0dbe8b058436ad5daecb19c60869f832607ea3 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Dec 2023 23:08:05 +0800 Subject: arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK The downstream QSDK kernel [1] and GCC_USB1_MOCK_UTMI_CLK are both 24MHz. Adjust GCC_USB0_MOCK_UTMI_CLK to 24MHz to avoid the following error: clk: couldn't set gcc_usb0_mock_utmi_clk clk rate to 20000000 (-22), current rate: 24000000 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/486c8485f59 Fixes: 5726079cd486 ("arm64: dts: ipq6018: Use reference clock to set dwc3 period") Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20231218150805.1228160-1-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index ff25bcb38bc9..5e1277fea725 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -628,7 +628,7 @@ <&gcc GCC_USB0_MOCK_UTMI_CLK>; assigned-clock-rates = <133330000>, <133330000>, - <20000000>; + <24000000>; resets = <&gcc GCC_USB0_BCR>; status = "disabled"; -- cgit v1.2.3 From 28b735232d5e16a34f98dbac1e7b5401c1c16d89 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:12 +0100 Subject: arm64: dts: qcom: sm8550: Separate out X3 idle state The X3 core has different entry/exit/residency time requirements than the big cluster. Denote them to stop confusing the scheduler. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-11-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d707d15cea5b..541457909309 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -300,6 +300,16 @@ min-residency-us = <4791>; local-timer-stop; }; + + PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { + compatible = "arm,idle-state"; + idle-state-name = "goldplus-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + local-timer-stop; + }; }; domain-idle-states { @@ -401,7 +411,7 @@ CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; + domain-idle-states = <&PRIME_CPU_SLEEP_0>; }; CLUSTER_PD: power-domain-cluster { -- cgit v1.2.3 From ad6556fb45d4ab91ad786a2025cbe2b0f2e6cf77 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:13 +0100 Subject: arm64: dts: qcom: sm8550: Update idle state time requirements The idle state entry/exit/residency times differ from what shipped on production devices, mostly being overly optimistic in entry times and overly pessimistic in minimal residency times. Align them with downstream sources. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-12-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 541457909309..ee1ba5a8c8fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -285,9 +285,9 @@ compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; + entry-latency-us = <550>; exit-latency-us = <750>; - min-residency-us = <4090>; + min-residency-us = <6700>; local-timer-stop; }; @@ -296,8 +296,8 @@ idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; + exit-latency-us = <1300>; + min-residency-us = <8136>; local-timer-stop; }; @@ -316,17 +316,17 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; }; }; }; -- cgit v1.2.3 From 49b0f4f141465b6446c0ade851ac11b13a888fa9 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 18 Dec 2023 18:36:40 +0200 Subject: arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550 The LDOs 1, 4 and 10 from PM8550 share the same supply, the SMPS 4 from PM8550ve. This needs to be done through shared supply approach otherwise the parsing will fail. Also fix a bindings check failure. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20231218-x1e80100-qcp-dts-fix-pm8550-regulators-supplies-v1-1-0a313ce87745@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 3746e1de3623..a37ad9475c90 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -40,13 +40,11 @@ vdd-bob1-supply = <&vph_pwr>; vdd-bob2-supply = <&vph_pwr>; - vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; vdd-l2-l13-l14-supply = <&vreg_bob1>; - vdd-l4-supply = <&vreg_s4c_1p8>; vdd-l5-l16-supply = <&vreg_bob1>; vdd-l6-l7-supply = <&vreg_bob2>; vdd-l8-l9-supply = <&vreg_bob1>; - vdd-l10-supply = <&vreg_s4c_1p8>; vdd-l12-supply = <&vreg_s5j_1p2>; vdd-l15-supply = <&vreg_s4c_1p8>; vdd-l17-supply = <&vreg_bob2>; -- cgit v1.2.3 From 45e8c72712345263208f7c94f334fa718634f557 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 19 Dec 2023 19:40:21 +0100 Subject: arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent The PCIe controllers on 8180 are cache-coherent. Mark them as such. Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231219-topic-8180_pcie_dmac-v1-1-5d00fc1b23fd@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 25e41d195374..953179e70c9b 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1751,6 +1751,7 @@ phys = <&pcie0_phy>; phy-names = "pciephy"; + dma-coherent; status = "disabled"; }; @@ -1847,6 +1848,7 @@ phys = <&pcie3_phy>; phy-names = "pciephy"; + dma-coherent; status = "disabled"; }; @@ -1944,6 +1946,7 @@ phys = <&pcie1_phy>; phy-names = "pciephy"; + dma-coherent; status = "disabled"; }; @@ -2041,6 +2044,7 @@ phys = <&pcie2_phy>; phy-names = "pciephy"; + dma-coherent; status = "disabled"; }; -- cgit v1.2.3 From 78403b37f6770441f80a78d13772394731afe055 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 19 Dec 2023 14:05:06 +0100 Subject: arm64: dts: qcom: sc8180x: Fix up PCIe nodes Duplicated clock output names cause probe errors and wrong clocks cause hardware not to work. Fix such issues. Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231219-topic-8180_pcie-v1-1-c2acbba4723c@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 953179e70c9b..0430d99091e3 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1762,7 +1762,7 @@ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "aux", "cfg_ahb", @@ -1859,7 +1859,7 @@ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_3_CFG_AHB_CLK>, <&gcc GCC_PCIE_3_CLKREF_CLK>, - <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_3_PIPE_CLK>; clock-names = "aux", "cfg_ahb", @@ -2063,7 +2063,7 @@ "refgen", "pipe"; #clock-cells = <0>; - clock-output-names = "pcie_3_pipe_clk"; + clock-output-names = "pcie_2_pipe_clk"; #phy-cells = <0>; -- cgit v1.2.3