From a3fd10732d276d7cf372c6746a78a1c8b6aa7541 Mon Sep 17 00:00:00 2001 From: Zev Weiss Date: Thu, 23 Feb 2023 16:03:58 -0800 Subject: ARM: dts: aspeed: romed8hm3: Fix GPIO polarity of system-fault LED Turns out it's in fact not the same as the heartbeat LED. Signed-off-by: Zev Weiss Cc: stable@vger.kernel.org # v5.18+ Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC") Link: https://lore.kernel.org/r/20230224000400.12226-2-zev@bewilderbeest.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts index ff4c07c69af1..00efe1a93a69 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts @@ -31,7 +31,7 @@ }; system-fault { - gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; panic-indicator; }; }; -- cgit v1.2.3 From 8bc5ae1d2b207b855010591adeace94f9ec4caf2 Mon Sep 17 00:00:00 2001 From: Zev Weiss Date: Thu, 23 Feb 2023 16:03:59 -0800 Subject: ARM: dts: aspeed: e3c246d4i: Add PECI device Now that we've got driver support for it, we might as well enable and use it. Signed-off-by: Zev Weiss Link: https://lore.kernel.org/r/20230224000400.12226-3-zev@bewilderbeest.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index 9b4cf5ebe6d5..67a75aeafc2b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -202,3 +202,7 @@ status = "okay"; aspeed,lpc-io-reg = <0xca2>; }; + +&peci0 { + status = "okay"; +}; -- cgit v1.2.3 From 9dedb724446913ea7b1591b4b3d2e3e909090980 Mon Sep 17 00:00:00 2001 From: Zev Weiss Date: Thu, 23 Feb 2023 16:04:00 -0800 Subject: ARM: dts: aspeed: asrock: Correct firmware flash SPI clocks While I'm not aware of any problems that have occurred running these at 100 MHz, the official word from ASRock is that 50 MHz is the correct speed to use, so let's be safe and use that instead. Signed-off-by: Zev Weiss Cc: stable@vger.kernel.org Fixes: 2b81613ce417 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC") Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC") Link: https://lore.kernel.org/r/20230224000400.12226-4-zev@bewilderbeest.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index 67a75aeafc2b..c4b2efbfdf56 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -63,7 +63,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-max-frequency = <100000000>; /* 100 MHz */ + spi-max-frequency = <50000000>; /* 50 MHz */ #include "openbmc-flash-layout.dtsi" }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts index 00efe1a93a69..4554abf0c7cd 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts @@ -51,7 +51,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-max-frequency = <100000000>; /* 100 MHz */ + spi-max-frequency = <50000000>; /* 50 MHz */ #include "openbmc-flash-layout-64.dtsi" }; }; -- cgit v1.2.3 From 695cb117ac2a3624eb4381c271a0376d9233df44 Mon Sep 17 00:00:00 2001 From: Chanh Nguyen Date: Tue, 28 Feb 2023 17:28:20 +0700 Subject: ARM: dts: aspeed: mtmitchell: Enable NCSI Use MAC3 (RGMII4) with the NC-SI stack instead of as an MDIO PHY. The OCP slot #0 and OCP slot #1 use a common BMC_NCSI signal, so we use only one of them at a time. The OCP slot #0 will be enabled by PCA9539's setting by default. Enable the OCP Auxiliary Power during booting to make the NCSI feature work. Signed-off-by: Chanh Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20230228102820.18477-1-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts | 37 +++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts index 4b91600eaf62..1e0e88465254 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts @@ -251,6 +251,14 @@ pinctrl-0 = <&pinctrl_rgmii1_default>; }; +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + &fmc { status = "okay"; flash@0 { @@ -439,6 +447,26 @@ status = "okay"; }; +&i2c8 { + status = "okay"; + + gpio@77 { + compatible = "nxp,pca9539"; + reg = <0x77>; + gpio-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <2>; + + bmc-ocp0-en-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-high; + line-name = "bmc-ocp0-en-n"; + }; + }; +}; + &i2c9 { status = "okay"; }; @@ -530,13 +558,20 @@ /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", "host0-reboot-ack-n","host0-ready","host0-shd-req-n", "host0-shd-ack-n","s0-overtemp-n", - /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","", + /*W0-W7*/ "","ocp-main-pwren","ocp-pgood","", "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok", "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n", "s1-overtemp-n","s1-spi-auth-fail-n", /*Y0-Y7*/ "","","","","","","","host0-special-boot", /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","",""; + + ocp-aux-pwren-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "ocp-aux-pwren"; + }; }; &gpio1 { -- cgit v1.2.3 From ed6f068330494e849b77a32b23842c6f73f57aa9 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Tue, 21 Feb 2023 19:50:56 -0600 Subject: ARM: dts: aspeed: everest: Add reserved memory for TPM event log Trusted boot support requires the platform event log passed up from the bootloader. In U-Boot, this can now be accomplished with a reserved memory region, so add a region for this purpose to the Everest BMC devicetree. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20230222015056.3903734-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index c3b0cd61ac85..c6f8f20914d1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -162,6 +162,11 @@ #size-cells = <1>; ranges; + event_log: tcg_event_log@b3d00000 { + no-map; + reg = <0xb3d00000 0x100000>; + }; + ramoops@b3e00000 { compatible = "ramoops"; reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ @@ -1887,6 +1892,7 @@ tpm@2e { compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; reg = <0x2e>; + memory-region = <&event_log>; }; }; -- cgit v1.2.3 From f90f462964ff92eb28a469574df7eda1b2da595d Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Mar 2023 16:24:03 -0600 Subject: ARM: dts: aspeed: bonnell: Remove MAC3 Bonnell is populated with only one ethernet controller. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20230308222403.1848795-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index a5be0ee048ec..97dacbe75182 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -884,16 +884,6 @@ use-ncsi; }; -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, - <&syscon ASPEED_CLK_MAC4RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - &wdt1 { aspeed,reset-type = "none"; aspeed,external-signal; -- cgit v1.2.3 From bb13bd587d53033f1151699b7522f979e2930ea6 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 23 Feb 2023 09:48:26 -0600 Subject: ARM: dts: aspeed: bonnell: Update eeprom size An eeprom had an incorrect size. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index 97dacbe75182..79516dc21c01 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -686,7 +686,7 @@ }; eeprom@50 { - compatible = "atmel,24c64"; + compatible = "atmel,24c128"; reg = <0x50>; }; -- cgit v1.2.3 From 9bdc19fb94581fb805f5033825f41c363f5c3e85 Mon Sep 17 00:00:00 2001 From: Lakshmi Yadlapati Date: Wed, 12 Apr 2023 00:23:05 -0500 Subject: ARM: dts: aspeed: p10bmc: Change power supply info Bonnell system supports new ACBEL FSG032 power supply on I2C addresses 5A and 5B. Update the device tree with new power supply information and device addresses. Signed-off-by: Lakshmi Yadlapati Reviewed-by: Eddie James Link: https://lore.kernel.org/r/20230412052305.1369521-6-lakshmiy@us.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index 79516dc21c01..81902cbe662c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -552,14 +552,14 @@ &i2c3 { status = "okay"; - power-supply@58 { - compatible = "ibm,cffps"; - reg = <0x58>; + power-supply@5a { + compatible = "acbel,fsg032"; + reg = <0x5a>; }; - power-supply@59 { - compatible = "ibm,cffps"; - reg = <0x59>; + power-supply@5b { + compatible = "acbel,fsg032"; + reg = <0x5b>; }; }; -- cgit v1.2.3 From 2ecdcd68e3871af219793e4ae35f9e96f3feb9a6 Mon Sep 17 00:00:00 2001 From: Delphine CC Chiu Date: Wed, 29 Mar 2023 16:32:34 +0800 Subject: ARM: dts: aspeed: greatlakes: Add gpio names Add GPIO names for SOC lines. Signed-off-by: Delphine CC Chiu Link: https://lore.kernel.org/r/20230329083235.24123-2-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-facebook-greatlakes.dts | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts index 8c05bd56ce1e..59819115c39d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts @@ -238,4 +238,53 @@ &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "power-bmc-nic","presence-ocp-debug", + "power-bmc-slot1","power-bmc-slot2", + "power-bmc-slot3","power-bmc-slot4","","", + /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary", + "reset-cause-nic-secondary","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button", + "slot3-bmc-reset-button","slot4-bmc-reset-button", + "","","","presence-emmc", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","", + "presence-mb-slot1","presence-mb-slot2", + "presence-mb-slot3","presence-mb-slot4", + /*I0-I7*/ "","","","","","","bb-bmc-button","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","", + /*N0-N7*/ "","","","","bmc-ready","","","", + /*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable", + /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable", + "reset-cause-pcie-slot1","reset-cause-pcie-slot2", + "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","GND", + /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button", + "bmc-slot3-ac-button","bmc-slot4-ac-button", + "","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","reset-cause-emmc","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&gpio1 { + status = "okay"; + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","","", + /*18C0-18C7*/ "","","","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","","","","","",""; }; -- cgit v1.2.3 From 8d250f34cd2678acfa249a10b92fa5976b61336f Mon Sep 17 00:00:00 2001 From: Delphine CC Chiu Date: Wed, 29 Mar 2023 16:32:35 +0800 Subject: ARM: dts: aspeed: greatlakes: add mctp device Add mctp node on I2C bus Signed-off-by: Delphine CC Chiu Link: https://lore.kernel.org/r/20230329083235.24123-3-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts index 59819115c39d..7a53f54833a0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts @@ -156,6 +156,7 @@ &i2c8 { status = "okay"; + mctp-controller; temperature-sensor@1f { compatible = "ti,tmp421"; reg = <0x1f>; @@ -165,6 +166,10 @@ compatible = "st,24c32"; reg = <0x50>; }; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; }; &i2c9 { @@ -238,7 +243,7 @@ &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; - status = "okay"; + gpio-line-names = /*A0-A7*/ "","","","","","","","", /*B0-B7*/ "power-bmc-nic","presence-ocp-debug", @@ -280,7 +285,6 @@ }; &gpio1 { - status = "okay"; gpio-line-names = /*18A0-18A7*/ "","","","","","","","", /*18B0-18B7*/ "","","","","","","","", -- cgit v1.2.3 From 7d4f0b0df7c5ec0cec834f87591423a7bbd1bab2 Mon Sep 17 00:00:00 2001 From: Chia-Wei Wang Date: Mon, 20 Mar 2023 16:11:33 +0800 Subject: ARM: dts: aspeed-g6: Add UDMA node Add the device tree node for the UART DMA (UDMA) controller. Signed-off-by: Chia-Wei Wang Link: https://lore.kernel.org/r/20230320081133.23655-6-chiawei_wang@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 8246a60de0d0..172dd748d807 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -863,6 +863,15 @@ clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; status = "disabled"; }; + + udma: dma-controller@1e79e000 { + compatible = "aspeed,ast2600-udma"; + reg = <0x1e79e000 0x1000>; + interrupts = ; + dma-channels = <28>; + #dma-cells = <1>; + status = "disabled"; + }; }; }; }; -- cgit v1.2.3