From 79e94aa19736ec8f38ec02880eeec37cc5900bd8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Mar 2023 13:25:04 +0800 Subject: ARM64: dts: imx7ulp: update usb compatible Per binding doc, update the compatible Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20230322052504.2629429-11-peng.fan@oss.nxp.com Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/imx7ulp.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 7f7d2d5122fb..f91bf719d4e2 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -189,7 +189,7 @@ }; usbotg1: usb@40330000 { - compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x40330000 0x200>; interrupts = ; clocks = <&pcc2 IMX7ULP_CLK_USB0>; @@ -202,7 +202,8 @@ }; usbmisc1: usbmisc@40330200 { - compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; #index-cells = <1>; reg = <0x40330200 0x200>; }; -- cgit v1.2.3 From 21d018b75f4f1c183be565d302fde7a01ae79fb0 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 14 Apr 2023 10:41:37 +0200 Subject: ARM: dts: stm32: add USB OTG UTMI clock on stm32mp151 It's needed on STM32MP15, when using the integrated full-speed PHY. This clock is an output of USBPHYC, and the HS USBPHYC is not attached as PHY in this case (managed directly by dwc2 ggpio glue): &usbotg_hs { compatible = "st,stm32mp15-fsotg", "snps,dwc2"; pinctrl-names = "default"; pinctrl-0 = <&usbotg_hs_pins_a &usbotg_fs_dp_dm_pins_a>; vbus-supply = <&vbus_otg>; status = "okay"; }; USBPHYC clock output must be used, so it can be properly enabled as a clock provider. Without this, currently, when the dualport High-Speed USBPHYC isn't requested by either USBH or OTG, it remains uninitialized when probing OTG: OTG configured with full-speed PHY isn't properly clocked, resulting in error log like: [ 2.383138] dwc2 49000000.usb-otg: dwc2_core_reset: HANG! Soft Reset timeout GRSTCTL_CSFTRST. Signed-off-by: Fabrice Gasnier Link: https://lore.kernel.org/r/20230414084137.1050487-5-fabrice.gasnier@foss.st.com Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 4e437d3f2ed6..63f4c78fcc1d 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1130,8 +1130,8 @@ usbotg_hs: usb-otg@49000000 { compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi"; resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = ; -- cgit v1.2.3