From 08ccf57283f89adbc2ff897ad82d6ad4560db7cd Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 23 Jul 2011 01:20:12 +0200 Subject: bcm47xx: prepare to support different buses Prepare bcm47xx to support different System buses. Before adding support for bcma it should be possible to build bcm47xx without the need of ssb. With this patch bcm47xx does not directly contain a ssb_bus, but a union contain all the supported system buses. As a SoC just uses one system bus a union is a good choice. Signed-off-by: Hauke Mehrtens Acked-by: Ralf Baechle Signed-off-by: John W. Linville --- arch/mips/bcm47xx/gpio.c | 56 +++++++++++++++++++++++++++------------------ arch/mips/bcm47xx/nvram.c | 15 ++++++++---- arch/mips/bcm47xx/serial.c | 13 +++++++++-- arch/mips/bcm47xx/setup.c | 33 ++++++++++++++++++++------ arch/mips/bcm47xx/time.c | 9 ++++++-- arch/mips/bcm47xx/wgt634u.c | 14 ++++++++---- 6 files changed, 98 insertions(+), 42 deletions(-) (limited to 'arch/mips/bcm47xx') diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c index e4a5ee9c9721..99e1c50caf6b 100644 --- a/arch/mips/bcm47xx/gpio.c +++ b/arch/mips/bcm47xx/gpio.c @@ -20,42 +20,54 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); int gpio_request(unsigned gpio, const char *tag) { - if (ssb_chipco_available(&ssb_bcm47xx.chipco) && - ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) - return -EINVAL; + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && + ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) + return -EINVAL; - if (ssb_extif_available(&ssb_bcm47xx.extif) && - ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) - return -EINVAL; + if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && + ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) + return -EINVAL; - if (test_and_set_bit(gpio, gpio_in_use)) - return -EBUSY; + if (test_and_set_bit(gpio, gpio_in_use)) + return -EBUSY; - return 0; + return 0; + } + return -EINVAL; } EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned gpio) { - if (ssb_chipco_available(&ssb_bcm47xx.chipco) && - ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) - return; + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && + ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) + return; - if (ssb_extif_available(&ssb_bcm47xx.extif) && - ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) - return; + if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && + ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) + return; - clear_bit(gpio, gpio_in_use); + clear_bit(gpio, gpio_in_use); + return; + } } EXPORT_SYMBOL(gpio_free); int gpio_to_irq(unsigned gpio) { - if (ssb_chipco_available(&ssb_bcm47xx.chipco)) - return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2; - else if (ssb_extif_available(&ssb_bcm47xx.extif)) - return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2; - else - return -EINVAL; + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) + return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; + else if (ssb_extif_available(&bcm47xx_bus.ssb.extif)) + return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; + else + return -EINVAL; + } + return -EINVAL; } EXPORT_SYMBOL_GPL(gpio_to_irq); diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index 54db815bc86c..bcac2ffd1248 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -26,14 +26,21 @@ static char nvram_buf[NVRAM_SPACE]; /* Probe for NVRAM header */ static void early_nvram_init(void) { - struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; + struct ssb_mipscore *mcore_ssb; struct nvram_header *header; int i; - u32 base, lim, off; + u32 base = 0; + u32 lim = 0; + u32 off; u32 *src, *dst; - base = mcore->flash_window; - lim = mcore->flash_window_size; + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + mcore_ssb = &bcm47xx_bus.ssb.mipscore; + base = mcore_ssb->flash_window; + lim = mcore_ssb->flash_window_size; + break; + } off = FLASH_MIN; while (off <= lim) { diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c index 59c11afdb2ab..17c67e24b549 100644 --- a/arch/mips/bcm47xx/serial.c +++ b/arch/mips/bcm47xx/serial.c @@ -23,10 +23,10 @@ static struct platform_device uart8250_device = { }, }; -static int __init uart8250_init(void) +static int __init uart8250_init_ssb(void) { int i; - struct ssb_mipscore *mcore = &(ssb_bcm47xx.mipscore); + struct ssb_mipscore *mcore = &(bcm47xx_bus.ssb.mipscore); memset(&uart8250_data, 0, sizeof(uart8250_data)); @@ -45,6 +45,15 @@ static int __init uart8250_init(void) return platform_device_register(&uart8250_device); } +static int __init uart8250_init(void) +{ + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + return uart8250_init_ssb(); + } + return -EINVAL; +} + module_init(uart8250_init); MODULE_AUTHOR("Aurelien Jarno "); diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index cfae81571ded..271cedb339ae 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -35,15 +35,22 @@ #include #include -struct ssb_bus ssb_bcm47xx; -EXPORT_SYMBOL(ssb_bcm47xx); +union bcm47xx_bus bcm47xx_bus; +EXPORT_SYMBOL(bcm47xx_bus); + +enum bcm47xx_bus_type bcm47xx_bus_type; +EXPORT_SYMBOL(bcm47xx_bus_type); static void bcm47xx_machine_restart(char *command) { printk(KERN_ALERT "Please stand by while rebooting the system...\n"); local_irq_disable(); /* Set the watchdog timer to reset immediately */ - ssb_watchdog_timer_set(&ssb_bcm47xx, 1); + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1); + break; + } while (1) cpu_relax(); } @@ -52,7 +59,11 @@ static void bcm47xx_machine_halt(void) { /* Disable interrupts and watchdog and spin forever */ local_irq_disable(); - ssb_watchdog_timer_set(&ssb_bcm47xx, 0); + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); + break; + } while (1) cpu_relax(); } @@ -247,7 +258,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus, return 0; } -void __init plat_mem_setup(void) +static void __init bcm47xx_register_ssb(void) { int err; char buf[100]; @@ -258,12 +269,12 @@ void __init plat_mem_setup(void) printk(KERN_WARNING "bcm47xx: someone else already registered" " a ssb SPROM callback handler (err %d)\n", err); - err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE, + err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE, bcm47xx_get_invariants); if (err) panic("Failed to initialize SSB bus (err %d)\n", err); - mcore = &ssb_bcm47xx.mipscore; + mcore = &bcm47xx_bus.ssb.mipscore; if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) { if (strstr(buf, "console=ttyS1")) { struct ssb_serial_port port; @@ -276,6 +287,14 @@ void __init plat_mem_setup(void) memcpy(&mcore->serial_ports[1], &port, sizeof(port)); } } +} + +void __init plat_mem_setup(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; + bcm47xx_register_ssb(); _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index 0c6f47b3fd94..50aea2e1808c 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -30,7 +30,7 @@ void __init plat_time_init(void) { - unsigned long hz; + unsigned long hz = 0; /* * Use deterministic values for initial counter interrupt @@ -39,7 +39,12 @@ void __init plat_time_init(void) write_c0_count(0); write_c0_compare(0xffff); - hz = ssb_cpu_clock(&ssb_bcm47xx.mipscore) / 2; + switch (bcm47xx_bus_type) { + case BCM47XX_BUS_TYPE_SSB: + hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; + break; + } + if (!hz) hz = 100000000; diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c index 74d06965326f..e9f9ec8d443b 100644 --- a/arch/mips/bcm47xx/wgt634u.c +++ b/arch/mips/bcm47xx/wgt634u.c @@ -108,7 +108,7 @@ static irqreturn_t gpio_interrupt(int irq, void *ignored) /* Interrupts are shared, check if the current one is a GPIO interrupt. */ - if (!ssb_chipco_irq_status(&ssb_bcm47xx.chipco, + if (!ssb_chipco_irq_status(&bcm47xx_bus.ssb.chipco, SSB_CHIPCO_IRQ_GPIO)) return IRQ_NONE; @@ -132,22 +132,26 @@ static int __init wgt634u_init(void) * machine. Use the MAC address as an heuristic. Netgear Inc. has * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx. */ + u8 *et0mac; - u8 *et0mac = ssb_bcm47xx.sprom.et0mac; + if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) + return -ENODEV; + + et0mac = bcm47xx_bus.ssb.sprom.et0mac; if (et0mac[0] == 0x00 && ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) || (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) { - struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; + struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore; printk(KERN_INFO "WGT634U machine detected.\n"); if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET), gpio_interrupt, IRQF_SHARED, - "WGT634U GPIO", &ssb_bcm47xx.chipco)) { + "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { gpio_direction_input(WGT634U_GPIO_RESET); gpio_intmask(WGT634U_GPIO_RESET, 1); - ssb_chipco_irq_mask(&ssb_bcm47xx.chipco, + ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco, SSB_CHIPCO_IRQ_GPIO, SSB_CHIPCO_IRQ_GPIO); } -- cgit v1.2.3 From a656ffcbc7a98a80d2136ae6bbdd8ae2eb48c78a Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 23 Jul 2011 01:20:13 +0200 Subject: bcm47xx: make it possible to build bcm47xx without ssb. Signed-off-by: Hauke Mehrtens Acked-by: Ralf Baechle Signed-off-by: John W. Linville --- arch/mips/Kconfig | 8 +------- arch/mips/bcm47xx/Kconfig | 18 ++++++++++++++++++ arch/mips/bcm47xx/Makefile | 3 ++- arch/mips/bcm47xx/gpio.c | 6 ++++++ arch/mips/bcm47xx/nvram.c | 4 ++++ arch/mips/bcm47xx/serial.c | 4 ++++ arch/mips/bcm47xx/setup.c | 8 ++++++++ arch/mips/bcm47xx/time.c | 2 ++ arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 4 ++++ arch/mips/include/asm/mach-bcm47xx/gpio.h | 12 ++++++++++++ arch/mips/pci/pci-bcm47xx.c | 6 ++++++ drivers/watchdog/bcm47xx_wdt.c | 4 ++++ 12 files changed, 71 insertions(+), 8 deletions(-) create mode 100644 arch/mips/bcm47xx/Kconfig (limited to 'arch/mips/bcm47xx') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 177cdaf83564..0dbb4edc2dd1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -91,15 +91,8 @@ config BCM47XX select DMA_NONCOHERENT select HW_HAS_PCI select IRQ_CPU - select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select SSB - select SSB_DRIVER_MIPS - select SSB_DRIVER_EXTIF - select SSB_EMBEDDED - select SSB_B43_PCI_BRIDGE if PCI - select SSB_PCICORE_HOSTMODE if PCI select GENERIC_GPIO select SYS_HAS_EARLY_PRINTK select CFE @@ -788,6 +781,7 @@ endchoice source "arch/mips/alchemy/Kconfig" source "arch/mips/ath79/Kconfig" +source "arch/mips/bcm47xx/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/jz4740/Kconfig" diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig new file mode 100644 index 000000000000..0346f92d12a2 --- /dev/null +++ b/arch/mips/bcm47xx/Kconfig @@ -0,0 +1,18 @@ +if BCM47XX + +config BCM47XX_SSB + bool "SSB Support for Broadcom BCM47XX" + select SYS_HAS_CPU_MIPS32_R1 + select SSB + select SSB_DRIVER_MIPS + select SSB_DRIVER_EXTIF + select SSB_EMBEDDED + select SSB_B43_PCI_BRIDGE if PCI + select SSB_PCICORE_HOSTMODE if PCI + default y + help + Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. + + This will generate an image with support for SSB and MIPS32 R1 instruction set. + +endif diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index 7465e8a72d9a..4add17349ff9 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -3,4 +3,5 @@ # under Linux. # -obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o +obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o +obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c index 99e1c50caf6b..2b804c36750b 100644 --- a/arch/mips/bcm47xx/gpio.c +++ b/arch/mips/bcm47xx/gpio.c @@ -21,6 +21,7 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES); int gpio_request(unsigned gpio, const char *tag) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) @@ -34,6 +35,7 @@ int gpio_request(unsigned gpio, const char *tag) return -EBUSY; return 0; +#endif } return -EINVAL; } @@ -42,6 +44,7 @@ EXPORT_SYMBOL(gpio_request); void gpio_free(unsigned gpio) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) @@ -53,6 +56,7 @@ void gpio_free(unsigned gpio) clear_bit(gpio, gpio_in_use); return; +#endif } } EXPORT_SYMBOL(gpio_free); @@ -60,6 +64,7 @@ EXPORT_SYMBOL(gpio_free); int gpio_to_irq(unsigned gpio) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; @@ -67,6 +72,7 @@ int gpio_to_irq(unsigned gpio) return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; else return -EINVAL; +#endif } return -EINVAL; } diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index bcac2ffd1248..4e994edb1425 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -26,7 +26,9 @@ static char nvram_buf[NVRAM_SPACE]; /* Probe for NVRAM header */ static void early_nvram_init(void) { +#ifdef CONFIG_BCM47XX_SSB struct ssb_mipscore *mcore_ssb; +#endif struct nvram_header *header; int i; u32 base = 0; @@ -35,11 +37,13 @@ static void early_nvram_init(void) u32 *src, *dst; switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: mcore_ssb = &bcm47xx_bus.ssb.mipscore; base = mcore_ssb->flash_window; lim = mcore_ssb->flash_window_size; break; +#endif } off = FLASH_MIN; diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c index 17c67e24b549..fcef68836979 100644 --- a/arch/mips/bcm47xx/serial.c +++ b/arch/mips/bcm47xx/serial.c @@ -23,6 +23,7 @@ static struct platform_device uart8250_device = { }, }; +#ifdef CONFIG_BCM47XX_SSB static int __init uart8250_init_ssb(void) { int i; @@ -44,12 +45,15 @@ static int __init uart8250_init_ssb(void) } return platform_device_register(&uart8250_device); } +#endif static int __init uart8250_init(void) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: return uart8250_init_ssb(); +#endif } return -EINVAL; } diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 271cedb339ae..142cf1bc8884 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -47,9 +47,11 @@ static void bcm47xx_machine_restart(char *command) local_irq_disable(); /* Set the watchdog timer to reset immediately */ switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1); break; +#endif } while (1) cpu_relax(); @@ -60,14 +62,17 @@ static void bcm47xx_machine_halt(void) /* Disable interrupts and watchdog and spin forever */ local_irq_disable(); switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); break; +#endif } while (1) cpu_relax(); } +#ifdef CONFIG_BCM47XX_SSB #define READ_FROM_NVRAM(_outvar, name, buf) \ if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\ sprom->_outvar = simple_strtoul(buf, NULL, 0); @@ -288,13 +293,16 @@ static void __init bcm47xx_register_ssb(void) } } } +#endif void __init plat_mem_setup(void) { struct cpuinfo_mips *c = ¤t_cpu_data; +#ifdef CONFIG_BCM47XX_SSB bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; bcm47xx_register_ssb(); +#endif _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index 50aea2e1808c..03dfc65b1b60 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -40,9 +40,11 @@ void __init plat_time_init(void) write_c0_compare(0xffff); switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; break; +#endif } if (!hz) diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h index 7cf481bb1a05..d037afb6677e 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h @@ -22,11 +22,15 @@ #include enum bcm47xx_bus_type { +#ifdef CONFIG_BCM47XX_SSB BCM47XX_BUS_TYPE_SSB, +#endif }; union bcm47xx_bus { +#ifdef CONFIG_BCM47XX_SSB struct ssb_bus ssb; +#endif }; extern union bcm47xx_bus bcm47xx_bus; diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h index 6b78827dd140..1d5f5af56b5f 100644 --- a/arch/mips/include/asm/mach-bcm47xx/gpio.h +++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h @@ -22,8 +22,10 @@ extern int gpio_to_irq(unsigned gpio); static inline int gpio_get_value(unsigned gpio) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio); +#endif } return -EINVAL; } @@ -31,18 +33,22 @@ static inline int gpio_get_value(unsigned gpio) static inline void gpio_set_value(unsigned gpio, int value) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, value ? 1 << gpio : 0); +#endif } } static inline int gpio_direction_input(unsigned gpio) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0); return 0; +#endif } return -EINVAL; } @@ -50,6 +56,7 @@ static inline int gpio_direction_input(unsigned gpio) static inline int gpio_direction_output(unsigned gpio, int value) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: /* first set the gpio out value */ ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, @@ -57,6 +64,7 @@ static inline int gpio_direction_output(unsigned gpio, int value) /* then set the gpio mode */ ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio); return 0; +#endif } return -EINVAL; } @@ -64,10 +72,12 @@ static inline int gpio_direction_output(unsigned gpio, int value) static inline int gpio_intmask(unsigned gpio, int value) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio, value ? 1 << gpio : 0); return 0; +#endif } return -EINVAL; } @@ -75,10 +85,12 @@ static inline int gpio_intmask(unsigned gpio, int value) static inline int gpio_polarity(unsigned gpio, int value) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio, value ? 1 << gpio : 0); return 0; +#endif } return -EINVAL; } diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c index 455f8e50a007..400535a955d0 100644 --- a/arch/mips/pci/pci-bcm47xx.c +++ b/arch/mips/pci/pci-bcm47xx.c @@ -25,6 +25,7 @@ #include #include #include +#include int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { @@ -33,9 +34,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) int pcibios_plat_dev_init(struct pci_dev *dev) { +#ifdef CONFIG_BCM47XX_SSB int res; u8 slot, pin; + if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) + return 0; + res = ssb_pcibios_plat_dev_init(dev); if (res < 0) { printk(KERN_ALERT "PCI: Failed to init device %s\n", @@ -55,5 +60,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev) } dev->irq = res; +#endif return 0; } diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index c43406c48613..6b037024464f 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -55,17 +55,21 @@ static inline void bcm47xx_wdt_hw_start(void) { /* this is 2,5s on 100Mhz clock and 2s on 133 Mhz */ switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff); break; +#endif } } static inline int bcm47xx_wdt_hw_stop(void) { switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); +#endif } return -EINVAL; } -- cgit v1.2.3 From c1d1c5d4213ee96e054c4d195117368972a4c01f Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 23 Jul 2011 01:20:14 +0200 Subject: bcm47xx: add support for bcma bus This patch add support for the bcma bus. Broadcom uses only Mips 74K CPUs on the new SoC and on the old ons using ssb bus there are no Mips 74K CPUs. Signed-off-by: Hauke Mehrtens Acked-by: Ralf Baechle Signed-off-by: John W. Linville --- arch/mips/bcm47xx/Kconfig | 13 +++++++ arch/mips/bcm47xx/gpio.c | 22 ++++++++++++ arch/mips/bcm47xx/nvram.c | 10 ++++++ arch/mips/bcm47xx/serial.c | 29 +++++++++++++++ arch/mips/bcm47xx/setup.c | 53 ++++++++++++++++++++++++++-- arch/mips/bcm47xx/time.c | 5 +++ arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 8 +++++ arch/mips/include/asm/mach-bcm47xx/gpio.h | 41 +++++++++++++++++++++ drivers/watchdog/bcm47xx_wdt.c | 11 ++++++ 9 files changed, 190 insertions(+), 2 deletions(-) (limited to 'arch/mips/bcm47xx') diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index 0346f92d12a2..6210b8d84109 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig @@ -15,4 +15,17 @@ config BCM47XX_SSB This will generate an image with support for SSB and MIPS32 R1 instruction set. +config BCM47XX_BCMA + bool "BCMA Support for Broadcom BCM47XX" + select SYS_HAS_CPU_MIPS32_R2 + select BCMA + select BCMA_HOST_SOC + select BCMA_DRIVER_MIPS + select BCMA_DRIVER_PCI_HOSTMODE if PCI + default y + help + Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus. + + This will generate an image with support for BCMA and MIPS32 R2 instruction set. + endif diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c index 2b804c36750b..57b425fd4d41 100644 --- a/arch/mips/bcm47xx/gpio.c +++ b/arch/mips/bcm47xx/gpio.c @@ -36,6 +36,16 @@ int gpio_request(unsigned gpio, const char *tag) return 0; #endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) + return -EINVAL; + + if (test_and_set_bit(gpio, gpio_in_use)) + return -EBUSY; + + return 0; +#endif } return -EINVAL; } @@ -57,6 +67,14 @@ void gpio_free(unsigned gpio) clear_bit(gpio, gpio_in_use); return; #endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) + return; + + clear_bit(gpio, gpio_in_use); + return; +#endif } } EXPORT_SYMBOL(gpio_free); @@ -72,6 +90,10 @@ int gpio_to_irq(unsigned gpio) return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; else return -EINVAL; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2; #endif } return -EINVAL; diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c index 4e994edb1425..a84e3bb7387f 100644 --- a/arch/mips/bcm47xx/nvram.c +++ b/arch/mips/bcm47xx/nvram.c @@ -28,6 +28,9 @@ static void early_nvram_init(void) { #ifdef CONFIG_BCM47XX_SSB struct ssb_mipscore *mcore_ssb; +#endif +#ifdef CONFIG_BCM47XX_BCMA + struct bcma_drv_cc *bcma_cc; #endif struct nvram_header *header; int i; @@ -43,6 +46,13 @@ static void early_nvram_init(void) base = mcore_ssb->flash_window; lim = mcore_ssb->flash_window_size; break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc; + base = bcma_cc->pflash.window; + lim = bcma_cc->pflash.window_size; + break; #endif } diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c index fcef68836979..57981e4fe2bc 100644 --- a/arch/mips/bcm47xx/serial.c +++ b/arch/mips/bcm47xx/serial.c @@ -47,12 +47,41 @@ static int __init uart8250_init_ssb(void) } #endif +#ifdef CONFIG_BCM47XX_BCMA +static int __init uart8250_init_bcma(void) +{ + int i; + struct bcma_drv_cc *cc = &(bcm47xx_bus.bcma.bus.drv_cc); + + memset(&uart8250_data, 0, sizeof(uart8250_data)); + + for (i = 0; i < cc->nr_serial_ports; i++) { + struct plat_serial8250_port *p = &(uart8250_data[i]); + struct bcma_serial_port *bcma_port; + bcma_port = &(cc->serial_ports[i]); + + p->mapbase = (unsigned int) bcma_port->regs; + p->membase = (void *) bcma_port->regs; + p->irq = bcma_port->irq + 2; + p->uartclk = bcma_port->baud_base; + p->regshift = bcma_port->reg_shift; + p->iotype = UPIO_MEM; + p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; + } + return platform_device_register(&uart8250_device); +} +#endif + static int __init uart8250_init(void) { switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: return uart8250_init_ssb(); +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return uart8250_init_bcma(); #endif } return -EINVAL; diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index 142cf1bc8884..17c3d14d7c49 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,11 @@ static void bcm47xx_machine_restart(char *command) case BCM47XX_BUS_TYPE_SSB: ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1); break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1); + break; #endif } while (1) @@ -66,6 +72,11 @@ static void bcm47xx_machine_halt(void) case BCM47XX_BUS_TYPE_SSB: ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0); + break; #endif } while (1) @@ -295,16 +306,54 @@ static void __init bcm47xx_register_ssb(void) } #endif +#ifdef CONFIG_BCM47XX_BCMA +static void __init bcm47xx_register_bcma(void) +{ + int err; + + err = bcma_host_soc_register(&bcm47xx_bus.bcma); + if (err) + panic("Failed to initialize BCMA bus (err %d)\n", err); +} +#endif + void __init plat_mem_setup(void) { struct cpuinfo_mips *c = ¤t_cpu_data; + if (c->cputype == CPU_74K) { + printk(KERN_INFO "bcm47xx: using bcma bus\n"); +#ifdef CONFIG_BCM47XX_BCMA + bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA; + bcm47xx_register_bcma(); +#endif + } else { + printk(KERN_INFO "bcm47xx: using ssb bus\n"); #ifdef CONFIG_BCM47XX_SSB - bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; - bcm47xx_register_ssb(); + bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; + bcm47xx_register_ssb(); #endif + } _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; pm_power_off = bcm47xx_machine_halt; } + +static int __init bcm47xx_register_bus_complete(void) +{ + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + /* Nothing to do */ + break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_bus_register(&bcm47xx_bus.bcma.bus); + break; +#endif + } + return 0; +} +device_initcall(bcm47xx_register_bus_complete); diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index 03dfc65b1b60..536374dcba78 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -44,6 +44,11 @@ void __init plat_time_init(void) case BCM47XX_BUS_TYPE_SSB: hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2; + break; #endif } diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h index d037afb6677e..de95e0723e2b 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h @@ -20,17 +20,25 @@ #define __ASM_BCM47XX_H #include +#include +#include enum bcm47xx_bus_type { #ifdef CONFIG_BCM47XX_SSB BCM47XX_BUS_TYPE_SSB, #endif +#ifdef CONFIG_BCM47XX_BCMA + BCM47XX_BUS_TYPE_BCMA, +#endif }; union bcm47xx_bus { #ifdef CONFIG_BCM47XX_SSB struct ssb_bus ssb; #endif +#ifdef CONFIG_BCM47XX_BCMA + struct bcma_soc bcma; +#endif }; extern union bcm47xx_bus bcm47xx_bus; diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h index 1d5f5af56b5f..76961cabeedf 100644 --- a/arch/mips/include/asm/mach-bcm47xx/gpio.h +++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h @@ -10,6 +10,7 @@ #define __BCM47XX_GPIO_H #include +#include #include #define BCM47XX_EXTIF_GPIO_LINES 5 @@ -25,6 +26,11 @@ static inline int gpio_get_value(unsigned gpio) #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio); +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, + 1 << gpio); #endif } return -EINVAL; @@ -37,6 +43,13 @@ static inline void gpio_set_value(unsigned gpio, int value) case BCM47XX_BUS_TYPE_SSB: ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio, value ? 1 << gpio : 0); + return; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, + value ? 1 << gpio : 0); + return; #endif } } @@ -48,6 +61,12 @@ static inline int gpio_direction_input(unsigned gpio) case BCM47XX_BUS_TYPE_SSB: ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0); return 0; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, + 0); + return 0; #endif } return -EINVAL; @@ -64,6 +83,16 @@ static inline int gpio_direction_output(unsigned gpio, int value) /* then set the gpio mode */ ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio); return 0; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + /* first set the gpio out value */ + bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, + value ? 1 << gpio : 0); + /* then set the gpio mode */ + bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio, + 1 << gpio); + return 0; #endif } return -EINVAL; @@ -77,6 +106,12 @@ static inline int gpio_intmask(unsigned gpio, int value) ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio, value ? 1 << gpio : 0); return 0; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc, + 1 << gpio, value ? 1 << gpio : 0); + return 0; #endif } return -EINVAL; @@ -90,6 +125,12 @@ static inline int gpio_polarity(unsigned gpio, int value) ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio, value ? 1 << gpio : 0); return 0; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc, + 1 << gpio, value ? 1 << gpio : 0); + return 0; #endif } return -EINVAL; diff --git a/drivers/watchdog/bcm47xx_wdt.c b/drivers/watchdog/bcm47xx_wdt.c index 6b037024464f..5c5f4b14fd05 100644 --- a/drivers/watchdog/bcm47xx_wdt.c +++ b/drivers/watchdog/bcm47xx_wdt.c @@ -59,6 +59,12 @@ static inline void bcm47xx_wdt_hw_start(void) case BCM47XX_BUS_TYPE_SSB: ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff); break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, + 0xfffffff); + break; #endif } } @@ -69,6 +75,11 @@ static inline int bcm47xx_wdt_hw_stop(void) #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0); +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0); + return 0; #endif } return -EINVAL; -- cgit v1.2.3 From a3e72cd2974a4b178d4edf6737ae51d1ea83b5d8 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sat, 23 Jul 2011 01:20:15 +0200 Subject: bcm47xx: fix irq assignment for new SoCs. Signed-off-by: Hauke Mehrtens Acked-by: Ralf Baechle Signed-off-by: John W. Linville --- arch/mips/bcm47xx/irq.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/mips/bcm47xx') diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c index 325757acd020..8cf3833b2d29 100644 --- a/arch/mips/bcm47xx/irq.c +++ b/arch/mips/bcm47xx/irq.c @@ -26,6 +26,7 @@ #include #include #include +#include void plat_irq_dispatch(void) { @@ -51,5 +52,16 @@ void plat_irq_dispatch(void) void __init arch_init_irq(void) { +#ifdef CONFIG_BCM47XX_BCMA + if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) { + bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core, + BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31); + /* + * the kernel reads the timer irq from some register and thinks + * it's #5, but we offset it by 2 and route to #7 + */ + cp0_compare_irq = 7; + } +#endif mips_cpu_irq_init(); } -- cgit v1.2.3