From 294b2111ff1027a942c362d523b847d73d91b70c Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 3 Jun 2022 09:45:35 +0100 Subject: riscv: dts: microchip: remove spi-max-frequency property spi-max-frequency property is supposed to be a per SPI peripheral device property, not a SPI controller property, so remove it. Reported-by: Rob Herring Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 8c3259134194..fb963559ba96 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -290,7 +290,6 @@ interrupt-parent = <&plic>; interrupts = <55>; clocks = <&clkcfg CLK_SPI1>; - spi-max-frequency = <25000000>; status = "disabled"; }; @@ -302,7 +301,6 @@ interrupt-parent = <&plic>; interrupts = <85>; clocks = <&clkcfg CLK_QSPI>; - spi-max-frequency = <25000000>; status = "disabled"; }; -- cgit v1.2.3 From 3f8ccf5f1a8c349364055b73caf1bb0314229976 Mon Sep 17 00:00:00 2001 From: Nagasuresh Relli Date: Thu, 16 Jun 2022 12:12:51 +0530 Subject: riscv: dts: microchip: remove spi-max-frequency property Remove the spi-max-frequency property from the spi0 controller node as it is supposed to be a per SPI peripheral device property. Reported-by: Rob Herring Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Signed-off-by: Nagasuresh Relli Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index fb963559ba96..1a5aa8836099 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -278,7 +278,6 @@ interrupt-parent = <&plic>; interrupts = <54>; clocks = <&clkcfg CLK_SPI0>; - spi-max-frequency = <25000000>; status = "disabled"; }; -- cgit v1.2.3 From 88d319c6abaeb37f0e2323275eaf57a8388e0265 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 20:04:35 +0100 Subject: riscv: dts: microchip: Add mpfs' topology information The mpfs has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley Reviewed-by: Sudeep Holla --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 1a5aa8836099..6b20828c919f 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -138,6 +138,30 @@ interrupt-controller; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; }; refclk: mssrefclk { -- cgit v1.2.3 From ef09fa67dc7dc7d839d8f9bee43ecacc83401de5 Mon Sep 17 00:00:00 2001 From: Jonas Hahnfeld Date: Tue, 5 Jul 2022 20:04:32 +0100 Subject: riscv: dts: starfive: Add JH7100 CPU topology Add cpu-map binding to inform the kernel about the hardware topology of the CPU cores. Before this change, lstopo would report 1 core with 2 threads: Machine (7231MB total) Package L#0 NUMANode L#0 (P#0 7231MB) L2 L#0 (2048KB) + Core L#0 L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1) After this change, it correctly identifies two cores: Machine (7231MB total) Package L#0 NUMANode L#0 (P#0 7231MB) L2 L#0 (2048KB) L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) Signed-off-by: Jonas Hahnfeld Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705190435.1790466-2-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 69f22f9aad9d..c617a61e26e2 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -17,7 +17,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + U74_0: cpu@0 { compatible = "sifive,u74-mc", "riscv"; reg = <0>; d-cache-block-size = <64>; @@ -42,7 +42,7 @@ }; }; - cpu@1 { + U74_1: cpu@1 { compatible = "sifive,u74-mc", "riscv"; reg = <1>; d-cache-block-size = <64>; @@ -66,6 +66,18 @@ #interrupt-cells = <1>; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&U74_0>; + }; + + core1 { + cpu = <&U74_1>; + }; + }; + }; }; osc_sys: osc_sys { -- cgit v1.2.3 From af8f260abc608c06e4466a282b53f1e2dc09f042 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 20:04:33 +0100 Subject: riscv: dts: sifive: Add fu540 topology information The fu540 has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705190435.1790466-3-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index e3172d0ffac4..24bba83bec77 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -133,6 +133,30 @@ interrupt-controller; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; }; soc { #address-cells = <2>; -- cgit v1.2.3 From bf6cd1c01c959a31002dfa6784c0d8caffed4cf1 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 20:04:34 +0100 Subject: riscv: dts: sifive: Add fu740 topology information The fu740 has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220705190435.1790466-4-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 7b77c13496d8..43bed6c0a84f 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -134,6 +134,30 @@ interrupt-controller; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; }; soc { #address-cells = <2>; -- cgit v1.2.3 From d9d193dea8666bbf69fc21c5bdcdabaa34a466e3 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Jul 2022 20:04:36 +0100 Subject: riscv: dts: canaan: Add k210 topology information The k210 has no cpu-map node, so tools like hwloc cannot correctly parse the topology. Add the node using the existing node labels. Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Signed-off-by: Conor Dooley Reviewed-by: Damien Le Moal Link: https://lore.kernel.org/r/20220705190435.1790466-6-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/canaan/k210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..ec944d1537dc 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -65,6 +65,18 @@ compatible = "riscv,cpu-intc"; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + }; }; sram: memory@80000000 { -- cgit v1.2.3 From b49816611eaceb66a00c8b18e6d7bcee63eba86b Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 6 Jun 2022 21:13:44 +0100 Subject: riscv: dts: sifive: "fix" pmic watchdog node name After converting the pmic watchdog binding to yaml, dtbs_check complains that the node name doesn't match the binding. "Fix" it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220606201343.514391-5-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/riscv/boot') diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts index c4ed9efdff03..1f386b07a832 100644 --- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts @@ -90,7 +90,7 @@ compatible = "dlg,da9063-rtc"; }; - wdt { + watchdog { compatible = "dlg,da9063-watchdog"; }; -- cgit v1.2.3