From e50db34efdc8cac2f17b8f5d32fddd7b58914ce6 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Mon, 19 Jun 2023 10:21:01 -0700 Subject: RISC-V: Fix up some vector state related build failures MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I get a few build failures along the lines of ./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type 19 | struct __riscv_v_ext_state v_state; | ^~~~~~~ ./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type 32 | struct __riscv_extra_ext_header sc_extdesc; The V structures in question are defined for !assembly, so let's just do so for the others. Fixes: 8ee0b41898fa ("riscv: signal: Add sigcontext save/restore for vector") Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230619172101.18692-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/uapi/asm/sigcontext.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/riscv/include/uapi/asm/sigcontext.h') diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h index 8b8a8541673a..8c8712aa9551 100644 --- a/arch/riscv/include/uapi/asm/sigcontext.h +++ b/arch/riscv/include/uapi/asm/sigcontext.h @@ -15,6 +15,8 @@ /* The size of END signal context header. */ #define END_HDR_SIZE 0x0 +#ifndef __ASSEMBLY__ + struct __sc_riscv_v_state { struct __riscv_v_ext_state v_state; } __attribute__((aligned(16))); @@ -33,4 +35,6 @@ struct sigcontext { }; }; +#endif /*!__ASSEMBLY__*/ + #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */ -- cgit v1.2.3