From a9bb5a4bf9f84256499c802fd397d56d55227e4f Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 13 Jan 2012 22:56:32 +0000 Subject: PCMCIA: pxa: convert PXA socket drivers to use new irq/gpio management Convert all the PXA platform socket drivers to use the new irq/gpio management provided by soc_common. This relieves these drivers from having to do anything with these GPIOs other than provide the numbers to soc_common. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-pxa/include/mach/balloon3.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index f02fa1e6ba86..954641e6c8b1 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -174,7 +174,6 @@ enum balloon3_features { #define BALLOON3_AUX_NIRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ) #define BALLOON3_CODEC_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ) -#define BALLOON3_S0_CD_IRQ PXA_GPIO_TO_IRQ(BALLOON3_GPIO_S0_CD) #define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) -- cgit v1.2.3 From 03e0092c85e34b6f84bb3b852579b78a17496be2 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 13 Jan 2012 23:02:15 +0000 Subject: PCMCIA: sa11x0: assabet: convert to use new irq/gpio management Convert Assabet socket driver to use the new irq/gpio management. This is slightly more involved because we have to touch the private platform header file to modify the GPIO bitmasks to be GPIO numbers. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-sa1100/include/mach/assabet.h | 15 +++---- drivers/pcmcia/sa1100_assabet.c | 64 +++++++---------------------- 2 files changed, 21 insertions(+), 58 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h index 28c2cf50c259..307391488c22 100644 --- a/arch/arm/mach-sa1100/include/mach/assabet.h +++ b/arch/arm/mach-sa1100/include/mach/assabet.h @@ -85,21 +85,18 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); #define ASSABET_BSR_RAD_RI (1 << 31) -/* GPIOs for which the generic definition doesn't say much */ +/* GPIOs (bitmasks) for which the generic definition doesn't say much */ #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ -#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */ -#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */ -#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */ #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ -#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */ #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ -#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 -#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 -#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 -#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 +/* These are gpiolib GPIO numbers, not bitmasks */ +#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */ +#define ASSABET_GPIO_CF_CD 22 /* CF CD */ +#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */ +#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */ #endif diff --git a/drivers/pcmcia/sa1100_assabet.c b/drivers/pcmcia/sa1100_assabet.c index f1e882272ab0..618f546e19c1 100644 --- a/drivers/pcmcia/sa1100_assabet.c +++ b/drivers/pcmcia/sa1100_assabet.c @@ -10,45 +10,30 @@ #include #include #include +#include -#include #include -#include -#include #include #include "sa1100_generic.h" -static struct pcmcia_irqs irqs[] = { - { 1, ASSABET_IRQ_GPIO_CF_CD, "CF CD" }, - { 1, ASSABET_IRQ_GPIO_CF_BVD2, "CF BVD2" }, - { 1, ASSABET_IRQ_GPIO_CF_BVD1, "CF BVD1" }, -}; - static int assabet_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { - skt->socket.pci_irq = ASSABET_IRQ_GPIO_CF_IRQ; - - return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} + skt->stat[SOC_STAT_CD].gpio = ASSABET_GPIO_CF_CD; + skt->stat[SOC_STAT_CD].name = "CF CD"; + skt->stat[SOC_STAT_BVD1].gpio = ASSABET_GPIO_CF_BVD1; + skt->stat[SOC_STAT_BVD1].name = "CF BVD1"; + skt->stat[SOC_STAT_BVD2].gpio = ASSABET_GPIO_CF_BVD2; + skt->stat[SOC_STAT_BVD2].name = "CF BVD2"; + skt->stat[SOC_STAT_RDY].gpio = ASSABET_GPIO_CF_IRQ; + skt->stat[SOC_STAT_RDY].name = "CF RDY"; -/* - * Release all resources. - */ -static void assabet_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); + return 0; } static void assabet_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) { - unsigned long levels = GPLR; - - state->detect = (levels & ASSABET_GPIO_CF_CD) ? 0 : 1; - state->ready = (levels & ASSABET_GPIO_CF_IRQ) ? 1 : 0; - state->bvd1 = (levels & ASSABET_GPIO_CF_BVD1) ? 1 : 0; - state->bvd2 = (levels & ASSABET_GPIO_CF_BVD2) ? 1 : 0; state->wrprot = 0; /* Not available on Assabet. */ state->vs_3v = 1; /* Can only apply 3.3V on Assabet. */ state->vs_Xv = 0; @@ -78,38 +63,24 @@ assabet_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_stat return -1; } - /* Silently ignore Vpp, output enable, speaker enable. */ + /* Silently ignore Vpp, speaker enable. */ if (state->flags & SS_RESET) mask |= ASSABET_BCR_CF_RST; + if (!(state->flags & SS_OUTPUT_ENA)) + mask |= ASSABET_BCR_CF_BUS_OFF; - ASSABET_BCR_frob(ASSABET_BCR_CF_RST | ASSABET_BCR_CF_PWR, mask); + ASSABET_BCR_frob(ASSABET_BCR_CF_RST | ASSABET_BCR_CF_PWR | + ASSABET_BCR_CF_BUS_OFF, mask); return 0; } -/* - * Enable card status IRQs on (re-)initialisation. This can - * be called at initialisation, power management event, or - * pcmcia event. - */ -static void assabet_pcmcia_socket_init(struct soc_pcmcia_socket *skt) -{ - /* - * Enable CF bus - */ - ASSABET_BCR_clear(ASSABET_BCR_CF_BUS_OFF); - - soc_pcmcia_enable_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} - /* * Disable card status IRQs on suspend. */ static void assabet_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) { - soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs)); - /* * Tristate the CF bus signals. Also assert CF * reset as per user guide page 4-11. @@ -119,14 +90,9 @@ static void assabet_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) static struct pcmcia_low_level assabet_pcmcia_ops = { .owner = THIS_MODULE, - .hw_init = assabet_pcmcia_hw_init, - .hw_shutdown = assabet_pcmcia_hw_shutdown, - .socket_state = assabet_pcmcia_socket_state, .configure_socket = assabet_pcmcia_configure_socket, - - .socket_init = assabet_pcmcia_socket_init, .socket_suspend = assabet_pcmcia_socket_suspend, }; -- cgit v1.2.3 From f793e3ab9f4cfbdba6269c8a6c522c5d665289b1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 13 Jan 2012 23:03:57 +0000 Subject: PCMCIA: sa11x0: cerf: convert to use new irq/gpio management Convert Cerf socket driver to use the new irq/gpio management. This is slightly more involved because we have to touch the private platform header file to modify the GPIO bitmasks to be GPIO numbers. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-sa1100/include/mach/cerf.h | 13 +++------- drivers/pcmcia/sa1100_cerf.c | 42 +++++++------------------------- 2 files changed, 13 insertions(+), 42 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h index c3ac3d0f9465..0e49545a3723 100644 --- a/arch/arm/mach-sa1100/include/mach/cerf.h +++ b/arch/arm/mach-sa1100/include/mach/cerf.h @@ -14,15 +14,10 @@ #define CERF_ETH_IO 0xf0000000 #define CERF_ETH_IRQ IRQ_GPIO26 -#define CERF_GPIO_CF_BVD2 GPIO_GPIO (19) -#define CERF_GPIO_CF_BVD1 GPIO_GPIO (20) +#define CERF_GPIO_CF_BVD2 19 +#define CERF_GPIO_CF_BVD1 20 #define CERF_GPIO_CF_RESET GPIO_GPIO (21) -#define CERF_GPIO_CF_IRQ GPIO_GPIO (22) -#define CERF_GPIO_CF_CD GPIO_GPIO (23) - -#define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19 -#define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20 -#define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22 -#define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23 +#define CERF_GPIO_CF_IRQ 22 +#define CERF_GPIO_CF_CD 23 #endif // _INCLUDE_CERF_H_ diff --git a/drivers/pcmcia/sa1100_cerf.c b/drivers/pcmcia/sa1100_cerf.c index 30560df8c76b..9d0424ea9a4f 100644 --- a/drivers/pcmcia/sa1100_cerf.c +++ b/drivers/pcmcia/sa1100_cerf.c @@ -19,33 +19,23 @@ #define CERF_SOCKET 1 -static struct pcmcia_irqs irqs[] = { - { CERF_SOCKET, CERF_IRQ_GPIO_CF_CD, "CF_CD" }, - { CERF_SOCKET, CERF_IRQ_GPIO_CF_BVD2, "CF_BVD2" }, - { CERF_SOCKET, CERF_IRQ_GPIO_CF_BVD1, "CF_BVD1" } -}; - static int cerf_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { - skt->socket.pci_irq = CERF_IRQ_GPIO_CF_IRQ; - - return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} + skt->stat[SOC_STAT_CD].gpio = CERF_GPIO_CF_CD; + skt->stat[SOC_STAT_CD].name = "CF_CD"; + skt->stat[SOC_STAT_BVD1].gpio = CERF_GPIO_CF_BVD1; + skt->stat[SOC_STAT_BVD1].name = "CF_BVD1"; + skt->stat[SOC_STAT_BVD2].gpio = CERF_GPIO_CF_BVD2; + skt->stat[SOC_STAT_BVD2].name = "CF_BVD2"; + skt->stat[SOC_STAT_RDY].gpio = CERF_GPIO_CF_IRQ; + skt->stat[SOC_STAT_RDY].name = "CF_IRQ"; -static void cerf_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); + return 0; } static void cerf_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) { - unsigned long levels = GPLR; - - state->detect = (levels & CERF_GPIO_CF_CD) ?0:1; - state->ready = (levels & CERF_GPIO_CF_IRQ) ?1:0; - state->bvd1 = (levels & CERF_GPIO_CF_BVD1)?1:0; - state->bvd2 = (levels & CERF_GPIO_CF_BVD2)?1:0; state->wrprot = 0; state->vs_3v = 1; state->vs_Xv = 0; @@ -76,25 +66,11 @@ cerf_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, return 0; } -static void cerf_pcmcia_socket_init(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_enable_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} - -static void cerf_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} - static struct pcmcia_low_level cerf_pcmcia_ops = { .owner = THIS_MODULE, .hw_init = cerf_pcmcia_hw_init, - .hw_shutdown = cerf_pcmcia_hw_shutdown, .socket_state = cerf_pcmcia_socket_state, .configure_socket = cerf_pcmcia_configure_socket, - - .socket_init = cerf_pcmcia_socket_init, - .socket_suspend = cerf_pcmcia_socket_suspend, }; int __devinit pcmcia_cerf_init(struct device *dev) -- cgit v1.2.3 From bbb58a1210c6fdc68b09f7b9e12096c2a1886aa1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 18 Jan 2012 12:32:37 +0000 Subject: PCMCIA: sa11x0: cerf: convert reset handling to use GPIO subsystem Rather than accessing GPSR and GPCR directly, use the GPIO subsystem instead. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-sa1100/include/mach/cerf.h | 2 +- drivers/pcmcia/sa1100_cerf.c | 19 ++++++++++++++----- 2 files changed, 15 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h index 0e49545a3723..88fd9c006ce0 100644 --- a/arch/arm/mach-sa1100/include/mach/cerf.h +++ b/arch/arm/mach-sa1100/include/mach/cerf.h @@ -16,7 +16,7 @@ #define CERF_GPIO_CF_BVD2 19 #define CERF_GPIO_CF_BVD1 20 -#define CERF_GPIO_CF_RESET GPIO_GPIO (21) +#define CERF_GPIO_CF_RESET 21 #define CERF_GPIO_CF_IRQ 22 #define CERF_GPIO_CF_CD 23 diff --git a/drivers/pcmcia/sa1100_cerf.c b/drivers/pcmcia/sa1100_cerf.c index 9d0424ea9a4f..50df0e682b68 100644 --- a/drivers/pcmcia/sa1100_cerf.c +++ b/drivers/pcmcia/sa1100_cerf.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -21,6 +22,12 @@ static int cerf_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { + int ret; + + ret = gpio_request_one(CERF_GPIO_CF_RESET, GPIOF_OUT_INIT_LOW, "CF_RESET"); + if (ret) + return ret; + skt->stat[SOC_STAT_CD].gpio = CERF_GPIO_CF_CD; skt->stat[SOC_STAT_CD].name = "CF_CD"; skt->stat[SOC_STAT_BVD1].gpio = CERF_GPIO_CF_BVD1; @@ -33,6 +40,11 @@ static int cerf_pcmcia_hw_init(struct soc_pcmcia_socket *skt) return 0; } +static void cerf_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free(CERF_GPIO_CF_RESET); +} + static void cerf_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) { @@ -57,11 +69,7 @@ cerf_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, return -1; } - if (state->flags & SS_RESET) { - GPSR = CERF_GPIO_CF_RESET; - } else { - GPCR = CERF_GPIO_CF_RESET; - } + gpio_set_value(CERF_GPIO_CF_RESET, !!(state->flags & SS_RESET)); return 0; } @@ -69,6 +77,7 @@ cerf_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, static struct pcmcia_low_level cerf_pcmcia_ops = { .owner = THIS_MODULE, .hw_init = cerf_pcmcia_hw_init, + .hw_shutdown = cerf_pcmcia_hw_shutdown, .socket_state = cerf_pcmcia_socket_state, .configure_socket = cerf_pcmcia_configure_socket, }; -- cgit v1.2.3 From 7cf779cb8ddeef797a3a265889c7f088d42a12f7 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 13 Jan 2012 23:05:12 +0000 Subject: PCMCIA: sa11x0: nanoengine: convert to use new irq/gpio management Convert Nanoengine socket driver to use the new irq/gpio management. This is slightly more involved because we have to touch the private platform header file to modify the GPIO bitmasks to be GPIO numbers. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-sa1100/include/mach/nanoengine.h | 8 +- drivers/pcmcia/sa1100_nanoengine.c | 101 +++---------------------- 2 files changed, 15 insertions(+), 94 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h index 14f8382d0665..ad24c6c37402 100644 --- a/arch/arm/mach-sa1100/include/mach/nanoengine.h +++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h @@ -16,10 +16,10 @@ #include -#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/ -#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */ -#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */ -#define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */ +#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ +#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ +#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ +#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ #define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */ #define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */ diff --git a/drivers/pcmcia/sa1100_nanoengine.c b/drivers/pcmcia/sa1100_nanoengine.c index 93b9c9ba57c3..b19b8161395b 100644 --- a/drivers/pcmcia/sa1100_nanoengine.c +++ b/drivers/pcmcia/sa1100_nanoengine.c @@ -34,43 +34,24 @@ #include "sa1100_generic.h" -static struct pcmcia_irqs irqs_skt0[] = { - /* socket, IRQ, name */ - { 0, NANOENGINE_IRQ_GPIO_PC_CD0, "PC CD0" }, -}; - -static struct pcmcia_irqs irqs_skt1[] = { - /* socket, IRQ, name */ - { 1, NANOENGINE_IRQ_GPIO_PC_CD1, "PC CD1" }, -}; - struct nanoengine_pins { - unsigned input_pins; unsigned output_pins; unsigned clear_outputs; - unsigned transition_pins; - unsigned pci_irq; - struct pcmcia_irqs *pcmcia_irqs; - unsigned pcmcia_irqs_size; + int gpio_cd; + int gpio_rdy; }; static struct nanoengine_pins nano_skts[] = { { - .input_pins = GPIO_PC_READY0 | GPIO_PC_CD0, .output_pins = GPIO_PC_RESET0, .clear_outputs = GPIO_PC_RESET0, - .transition_pins = NANOENGINE_IRQ_GPIO_PC_CD0, - .pci_irq = NANOENGINE_IRQ_GPIO_PC_READY0, - .pcmcia_irqs = irqs_skt0, - .pcmcia_irqs_size = ARRAY_SIZE(irqs_skt0) + .gpio_cd = GPIO_PC_CD0, + .gpio_rdy = GPIO_PC_READY0, }, { - .input_pins = GPIO_PC_READY1 | GPIO_PC_CD1, .output_pins = GPIO_PC_RESET1, .clear_outputs = GPIO_PC_RESET1, - .transition_pins = NANOENGINE_IRQ_GPIO_PC_CD1, - .pci_irq = NANOENGINE_IRQ_GPIO_PC_READY1, - .pcmcia_irqs = irqs_skt1, - .pcmcia_irqs_size = ARRAY_SIZE(irqs_skt1) + .gpio_cd = GPIO_PC_CD1, + .gpio_rdy = GPIO_PC_READY1, } }; @@ -83,28 +64,15 @@ static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt) if (i >= num_nano_pcmcia_sockets) return -ENXIO; - GPDR &= ~nano_skts[i].input_pins; GPDR |= nano_skts[i].output_pins; GPCR = nano_skts[i].clear_outputs; - irq_set_irq_type(nano_skts[i].transition_pins, IRQ_TYPE_EDGE_BOTH); - skt->socket.pci_irq = nano_skts[i].pci_irq; - return soc_pcmcia_request_irqs(skt, - nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size); -} + skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd; + skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0"; + skt->stat[SOC_STAT_RDY].gpio = nano_skts[i].gpio_rdy; + skt->stat[SOC_STAT_RDY].name = i ? "PC RDY1" : "PC RDY0"; -/* - * Release all resources. - */ -static void nanoengine_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) -{ - unsigned i = skt->nr; - - if (i >= num_nano_pcmcia_sockets) - return; - - soc_pcmcia_free_irqs(skt, - nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size); + return 0; } static int nanoengine_pcmcia_configure_socket( @@ -138,25 +106,11 @@ static int nanoengine_pcmcia_configure_socket( static void nanoengine_pcmcia_socket_state( struct soc_pcmcia_socket *skt, struct pcmcia_state *state) { - unsigned long levels = GPLR; unsigned i = skt->nr; if (i >= num_nano_pcmcia_sockets) return; - memset(state, 0, sizeof(struct pcmcia_state)); - switch (i) { - case 0: - state->ready = (levels & GPIO_PC_READY0) ? 1 : 0; - state->detect = !(levels & GPIO_PC_CD0) ? 1 : 0; - break; - case 1: - state->ready = (levels & GPIO_PC_READY1) ? 1 : 0; - state->detect = !(levels & GPIO_PC_CD1) ? 1 : 0; - break; - default: - return; - } state->bvd1 = 1; state->bvd2 = 1; state->wrprot = 0; /* Not available */ @@ -164,46 +118,13 @@ static void nanoengine_pcmcia_socket_state( state->vs_Xv = 0; } -/* - * Enable card status IRQs on (re-)initialisation. This can - * be called at initialisation, power management event, or - * pcmcia event. - */ -static void nanoengine_pcmcia_socket_init(struct soc_pcmcia_socket *skt) -{ - unsigned i = skt->nr; - - if (i >= num_nano_pcmcia_sockets) - return; - - soc_pcmcia_enable_irqs(skt, - nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size); -} - -/* - * Disable card status IRQs on suspend. - */ -static void nanoengine_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) -{ - unsigned i = skt->nr; - - if (i >= num_nano_pcmcia_sockets) - return; - - soc_pcmcia_disable_irqs(skt, - nano_skts[i].pcmcia_irqs, nano_skts[i].pcmcia_irqs_size); -} - static struct pcmcia_low_level nanoengine_pcmcia_ops = { .owner = THIS_MODULE, .hw_init = nanoengine_pcmcia_hw_init, - .hw_shutdown = nanoengine_pcmcia_hw_shutdown, .configure_socket = nanoengine_pcmcia_configure_socket, .socket_state = nanoengine_pcmcia_socket_state, - .socket_init = nanoengine_pcmcia_socket_init, - .socket_suspend = nanoengine_pcmcia_socket_suspend, }; int pcmcia_nanoengine_init(struct device *dev) -- cgit v1.2.3 From 76346a4eabf85a44dc425c0197ba46a8884e6090 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 18 Jan 2012 12:37:20 +0000 Subject: PCMCIA: sa11x0: nanoengine: convert reset handling to use GPIO subsystem Rather than accessing GPSR and GPCR directly, use the GPIO subsystem instead. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-sa1100/include/mach/nanoengine.h | 4 +-- drivers/pcmcia/sa1100_nanoengine.c | 38 +++++++++++--------------- 2 files changed, 18 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h index ad24c6c37402..5ebd469a31f2 100644 --- a/arch/arm/mach-sa1100/include/mach/nanoengine.h +++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h @@ -20,8 +20,8 @@ #define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ #define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ #define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ -#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */ -#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */ +#define GPIO_PC_RESET0 15 /* reset socket 0 */ +#define GPIO_PC_RESET1 16 /* reset socket 1 */ #define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 #define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 diff --git a/drivers/pcmcia/sa1100_nanoengine.c b/drivers/pcmcia/sa1100_nanoengine.c index b19b8161395b..cb43e39aef3f 100644 --- a/drivers/pcmcia/sa1100_nanoengine.c +++ b/drivers/pcmcia/sa1100_nanoengine.c @@ -19,6 +19,7 @@ */ #include #include +#include #include #include #include @@ -37,19 +38,18 @@ struct nanoengine_pins { unsigned output_pins; unsigned clear_outputs; + int gpio_rst; int gpio_cd; int gpio_rdy; }; static struct nanoengine_pins nano_skts[] = { { - .output_pins = GPIO_PC_RESET0, - .clear_outputs = GPIO_PC_RESET0, + .gpio_rst = GPIO_PC_RESET0, .gpio_cd = GPIO_PC_CD0, .gpio_rdy = GPIO_PC_READY0, }, { - .output_pins = GPIO_PC_RESET1, - .clear_outputs = GPIO_PC_RESET1, + .gpio_rst = GPIO_PC_RESET1, .gpio_cd = GPIO_PC_CD1, .gpio_rdy = GPIO_PC_READY1, } @@ -60,12 +60,15 @@ unsigned num_nano_pcmcia_sockets = ARRAY_SIZE(nano_skts); static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { unsigned i = skt->nr; + int ret; if (i >= num_nano_pcmcia_sockets) return -ENXIO; - GPDR |= nano_skts[i].output_pins; - GPCR = nano_skts[i].clear_outputs; + ret = gpio_request_one(nano_skts[i].gpio_rst, GPIOF_OUT_INIT_LOW, + i ? "PC RST1" : "PC RST0"); + if (ret) + return ret; skt->stat[SOC_STAT_CD].gpio = nano_skts[i].gpio_cd; skt->stat[SOC_STAT_CD].name = i ? "PC CD1" : "PC CD0"; @@ -75,30 +78,20 @@ static int nanoengine_pcmcia_hw_init(struct soc_pcmcia_socket *skt) return 0; } +static void nanoengine_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) +{ + gpio_free(nano_skts[skt->nr].gpio_rst); +} + static int nanoengine_pcmcia_configure_socket( struct soc_pcmcia_socket *skt, const socket_state_t *state) { - unsigned reset; unsigned i = skt->nr; if (i >= num_nano_pcmcia_sockets) return -ENXIO; - switch (i) { - case 0: - reset = GPIO_PC_RESET0; - break; - case 1: - reset = GPIO_PC_RESET1; - break; - default: - return -ENXIO; - } - - if (state->flags & SS_RESET) - GPSR = reset; - else - GPCR = reset; + gpio_set_value(nano_skts[skt->nr].gpio_rst, !!(state->flags & SS_RESET)); return 0; } @@ -122,6 +115,7 @@ static struct pcmcia_low_level nanoengine_pcmcia_ops = { .owner = THIS_MODULE, .hw_init = nanoengine_pcmcia_hw_init, + .hw_shutdown = nanoengine_pcmcia_hw_shutdown, .configure_socket = nanoengine_pcmcia_configure_socket, .socket_state = nanoengine_pcmcia_socket_state, -- cgit v1.2.3 From 3b61436a792517848ee386bd2ccf4fc3a75f1a0f Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 13 Jan 2012 23:06:09 +0000 Subject: PCMCIA: sa11x0: shannon: convert to use new irq/gpio management Convert Shannon socket driver to use the new irq/gpio management. This is slightly more involved because we have to touch the private platform header file to modify the GPIO bitmasks to be GPIO numbers. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-sa1100/include/mach/shannon.h | 12 +++---- drivers/pcmcia/sa1100_shannon.c | 54 +++++++++-------------------- 2 files changed, 21 insertions(+), 45 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h index ec27d6e12140..019f857a7938 100644 --- a/arch/arm/mach-sa1100/include/mach/shannon.h +++ b/arch/arm/mach-sa1100/include/mach/shannon.h @@ -23,14 +23,10 @@ #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ #define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ /* XXX GPIO 23 unaccounted for */ -#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ -#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 -#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ -#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 -#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */ -#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26 -#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */ -#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27 +#define SHANNON_GPIO_EJECT_0 24 /* in */ +#define SHANNON_GPIO_EJECT_1 25 /* in */ +#define SHANNON_GPIO_RDY_0 26 /* in */ +#define SHANNON_GPIO_RDY_1 27 /* in */ /* MCP UCB codec GPIO pins... */ diff --git a/drivers/pcmcia/sa1100_shannon.c b/drivers/pcmcia/sa1100_shannon.c index 7ff1b43540b8..7552d8591a29 100644 --- a/drivers/pcmcia/sa1100_shannon.c +++ b/drivers/pcmcia/sa1100_shannon.c @@ -15,39 +15,35 @@ #include #include "sa1100_generic.h" -static struct pcmcia_irqs irqs[] = { - { 0, SHANNON_IRQ_GPIO_EJECT_0, "PCMCIA_CD_0" }, - { 1, SHANNON_IRQ_GPIO_EJECT_1, "PCMCIA_CD_1" }, -}; - static int shannon_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { /* All those are inputs */ - GPDR &= ~(SHANNON_GPIO_EJECT_0 | SHANNON_GPIO_EJECT_1 | - SHANNON_GPIO_RDY_0 | SHANNON_GPIO_RDY_1); - GAFR &= ~(SHANNON_GPIO_EJECT_0 | SHANNON_GPIO_EJECT_1 | - SHANNON_GPIO_RDY_0 | SHANNON_GPIO_RDY_1); - - skt->socket.pci_irq = skt->nr ? SHANNON_IRQ_GPIO_RDY_1 : SHANNON_IRQ_GPIO_RDY_0; - - return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} + GAFR &= ~(GPIO_GPIO(SHANNON_GPIO_EJECT_0) | + GPIO_GPIO(SHANNON_GPIO_EJECT_1) | + GPIO_GPIO(SHANNON_GPIO_RDY_0) | + GPIO_GPIO(SHANNON_GPIO_RDY_1)); + + if (skt->nr == 0) { + skt->stat[SOC_STAT_CD].gpio = SHANNON_GPIO_EJECT_0; + skt->stat[SOC_STAT_CD].name = "PCMCIA_CD_0"; + skt->stat[SOC_STAT_RDY].gpio = SHANNON_GPIO_RDY_0; + skt->stat[SOC_STAT_RDY].name = "PCMCIA_RDY_0"; + } else { + skt->stat[SOC_STAT_CD].gpio = SHANNON_GPIO_EJECT_1; + skt->stat[SOC_STAT_CD].name = "PCMCIA_CD_1"; + skt->stat[SOC_STAT_RDY].gpio = SHANNON_GPIO_RDY_1; + skt->stat[SOC_STAT_RDY].name = "PCMCIA_RDY_1"; + } -static void shannon_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); + return 0; } static void shannon_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) { - unsigned long levels = GPLR; - switch (skt->nr) { case 0: - state->detect = (levels & SHANNON_GPIO_EJECT_0) ? 0 : 1; - state->ready = (levels & SHANNON_GPIO_RDY_0) ? 1 : 0; state->wrprot = 0; /* Not available on Shannon. */ state->bvd1 = 1; state->bvd2 = 1; @@ -56,8 +52,6 @@ shannon_pcmcia_socket_state(struct soc_pcmcia_socket *skt, break; case 1: - state->detect = (levels & SHANNON_GPIO_EJECT_1) ? 0 : 1; - state->ready = (levels & SHANNON_GPIO_RDY_1) ? 1 : 0; state->wrprot = 0; /* Not available on Shannon. */ state->bvd1 = 1; state->bvd2 = 1; @@ -92,25 +86,11 @@ shannon_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, return 0; } -static void shannon_pcmcia_socket_init(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_enable_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} - -static void shannon_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} - static struct pcmcia_low_level shannon_pcmcia_ops = { .owner = THIS_MODULE, .hw_init = shannon_pcmcia_hw_init, - .hw_shutdown = shannon_pcmcia_hw_shutdown, .socket_state = shannon_pcmcia_socket_state, .configure_socket = shannon_pcmcia_configure_socket, - - .socket_init = shannon_pcmcia_socket_init, - .socket_suspend = shannon_pcmcia_socket_suspend, }; int __devinit pcmcia_shannon_init(struct device *dev) -- cgit v1.2.3 From b1d8a5f91796179f33de9cd7fb26052fcc47b4fa Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 13 Jan 2012 23:06:48 +0000 Subject: PCMCIA: sa11x0: simpad: convert to use new irq/gpio management Convert Simpad socket driver to use the new irq/gpio management. This is slightly more involved because we have to touch the private platform header file to modify the GPIO bitmasks to be GPIO numbers. Acked-by: Dominik Brodowski Signed-off-by: Russell King --- arch/arm/mach-sa1100/include/mach/simpad.h | 6 ++---- drivers/pcmcia/sa1100_simpad.c | 26 ++++++++------------------ 2 files changed, 10 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h index db28118103eb..cdea671e8931 100644 --- a/arch/arm/mach-sa1100/include/mach/simpad.h +++ b/arch/arm/mach-sa1100/include/mach/simpad.h @@ -39,10 +39,8 @@ /*--- PCMCIA ---*/ -#define GPIO_CF_CD GPIO_GPIO24 -#define GPIO_CF_IRQ GPIO_GPIO1 -#define IRQ_GPIO_CF_IRQ IRQ_GPIO1 -#define IRQ_GPIO_CF_CD IRQ_GPIO24 +#define GPIO_CF_CD 24 +#define GPIO_CF_IRQ 1 /*--- SmartCard ---*/ #define GPIO_SMART_CARD GPIO_GPIO10 diff --git a/drivers/pcmcia/sa1100_simpad.c b/drivers/pcmcia/sa1100_simpad.c index 0fac9658b020..39d2241b9d80 100644 --- a/drivers/pcmcia/sa1100_simpad.c +++ b/drivers/pcmcia/sa1100_simpad.c @@ -15,24 +15,21 @@ #include #include "sa1100_generic.h" -static struct pcmcia_irqs irqs[] = { - { 1, IRQ_GPIO_CF_CD, "CF_CD" }, -}; - static int simpad_pcmcia_hw_init(struct soc_pcmcia_socket *skt) { simpad_clear_cs3_bit(VCC_3V_EN|VCC_5V_EN|EN0|EN1); - skt->socket.pci_irq = IRQ_GPIO_CF_IRQ; + skt->stat[SOC_STAT_CD].gpio = GPIO_CF_CD; + skt->stat[SOC_STAT_CD].name = "CF_CD"; + skt->stat[SOC_STAT_RDY].gpio = GPIO_CF_IRQ; + skt->stat[SOC_STAT_RDY].name = "CF_RDY"; - return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); + return 0; } static void simpad_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) { - soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); - /* Disable CF bus: */ /*simpad_set_cs3_bit(PCMCIA_BUFF_DIS);*/ simpad_clear_cs3_bit(PCMCIA_RESET); @@ -42,11 +39,11 @@ static void simpad_pcmcia_socket_state(struct soc_pcmcia_socket *skt, struct pcmcia_state *state) { - unsigned long levels = GPLR; long cs3reg = simpad_get_cs3_ro(); - state->detect=((levels & GPIO_CF_CD)==0)?1:0; - state->ready=(levels & GPIO_CF_IRQ)?1:0; + /* the detect signal is inverted - fix that up here */ + state->detect = !state->detect; + state->bvd1 = 1; /* Might be cs3reg & PCMCIA_BVD1 */ state->bvd2 = 1; /* Might be cs3reg & PCMCIA_BVD2 */ state->wrprot=0; /* Not available on Simpad. */ @@ -99,14 +96,8 @@ simpad_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, return 0; } -static void simpad_pcmcia_socket_init(struct soc_pcmcia_socket *skt) -{ - soc_pcmcia_enable_irqs(skt, irqs, ARRAY_SIZE(irqs)); -} - static void simpad_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) { - soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs)); simpad_set_cs3_bit(PCMCIA_RESET); } @@ -116,7 +107,6 @@ static struct pcmcia_low_level simpad_pcmcia_ops = { .hw_shutdown = simpad_pcmcia_hw_shutdown, .socket_state = simpad_pcmcia_socket_state, .configure_socket = simpad_pcmcia_configure_socket, - .socket_init = simpad_pcmcia_socket_init, .socket_suspend = simpad_pcmcia_socket_suspend, }; -- cgit v1.2.3