From d8b1c3d0d700f7995607fde333a992de28636178 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Thu, 27 Jan 2022 15:06:35 -0500 Subject: arm64: dts: zynqmp: Move USB clocks to dwc3 node These clocks are not used by the dwc3-xilinx driver except to enable/disable them. Move them to the dwc3 node so its driver can use them to configure the reference clock period. Tested-by: Robert Hancock Reviewed-by: Robert Hancock Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220127200636.1456175-7-sean.anderson@seco.com Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 1e0b1bca7c94..8493dd7d5f1f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -223,11 +223,11 @@ clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; -&usb0 { +&dwc3_0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; -&usb1 { +&dwc3_1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 74e66443e4ce..ba68fb8529ee 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -811,7 +811,6 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; - clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, @@ -825,6 +824,7 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 65 4>, <0 69 4>; + clock-names = "bus_early", "ref"; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; @@ -838,7 +838,6 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; - clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, @@ -852,6 +851,7 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 70 4>, <0 74 4>; + clock-names = "bus_early", "ref"; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; -- cgit v1.2.3 From 5726079cd4860c190722445e01e1007e40a9ccb4 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Thu, 27 Jan 2022 15:06:36 -0500 Subject: arm64: dts: ipq6018: Use reference clock to set dwc3 period Instead of manually setting snps,ref-clock-period-ns, we can let the driver calculate it automatically from the "ref" clock. I haven't reviewed this board's schematics, so please let me know if this is the wrong 24MHz clock to use. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20220127200636.1456175-8-sean.anderson@seco.com Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 66ec5615651d..a614b9f73e2c 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -743,12 +743,13 @@ interrupts = ; phys = <&qusb_phy_0>, <&usb0_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + clocks = <&xo>; + clock-names = "ref"; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; - snps,ref-clock-period-ns = <0x32>; dr_mode = "host"; }; }; -- cgit v1.2.3 From 325b820fa97f40704439674421a55b443810938d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 25 Jan 2022 10:18:21 -0600 Subject: arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg" The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg" compatible. Signed-off-by: Dinh Nguyen Link: https://lore.kernel.org/r/20220125161821.1951906-3-dinguyen@kernel.org Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 0dd2d2ee765a..f4270cf18996 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -502,7 +502,7 @@ }; usb0: usb@ffb00000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb00000 0x40000>; interrupts = ; phys = <&usbphy0>; @@ -515,7 +515,7 @@ }; usb1: usb@ffb40000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb40000 0x40000>; interrupts = ; phys = <&usbphy0>; -- cgit v1.2.3 From a0c68e493007a8c72b6b00f6ac95590a86edc937 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 8 Feb 2022 23:24:27 +0530 Subject: arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector Add the Embedded USB Debugger(EUD) device tree node. The node contains EUD base register region and EUD mode manager register regions along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. Also add the role-switch property to dwc3 node. Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/b2b6bdf0e7589a7b6a6f9b390b227339636e0da9.1644339918.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 937c2e0e93eb..96917fe81d43 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2583,6 +2583,12 @@ phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; + usb-role-switch; + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; }; @@ -2624,6 +2630,36 @@ interrupts = ; }; + eud: eud@88e0000 { + compatible = "qcom,sc7280-eud","qcom,eud"; + reg = <0 0x88e0000 0 0x2000>, + <0 0x88e2000 0 0x1000>; + interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; + ports { + port@0 { + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + port@1 { + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; + + eud_typec: connector { + compatible = "usb-c-connector"; + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + nsp_noc: interconnect@a0c0000 { reg = <0 0x0a0c0000 0 0x10000>; compatible = "qcom,sc7280-nsp-noc"; -- cgit v1.2.3 From c18553956f34819e224a79c9890eba2ba0604e15 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 8 Feb 2022 23:24:28 +0530 Subject: arm64: dts: qcom: sc7280: Set the default dr_mode for usb2 Set the default dr_mode for usb2 node to "otg" to enable role-switch for EUD(Embedded USB Debugger) connector node. Reviewed-by: Bjorn Andersson Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/22fb3bbc16f3a0ae894068e4420e08ea86389817.1644339918.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 9b991ba5daaf..f40eaa51b5bc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -61,6 +61,10 @@ modem-init; }; +&usb_2_dwc3 { + dr_mode = "otg"; +}; + &pmk8350_rtc { status = "okay"; }; -- cgit v1.2.3 From 45a7dbf484aa13e2ac7ce909096e2fddae2b13f0 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Fri, 25 Feb 2022 18:33:00 +0530 Subject: Revert "arm64: dts: qcom: sc7280: Set the default dr_mode for usb2" This reverts commit c18553956f34819e224a79c9890eba2ba0604e15. Revert the change to set dr_mode for usb2 in case of Embedded USB Debugger(EUD). This change needs to be reverted as the DT changes for QCOM should go through the QCOM tree and not the USB tree. Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/87008876afb33d8e1b7fd78d2fd5b6d9ec343d7d.1645793187.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index f40eaa51b5bc..9b991ba5daaf 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -61,10 +61,6 @@ modem-init; }; -&usb_2_dwc3 { - dr_mode = "otg"; -}; - &pmk8350_rtc { status = "okay"; }; -- cgit v1.2.3 From bced4afc536dcfc98e4dd32dcaecdb17be03315d Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Fri, 25 Feb 2022 18:33:01 +0530 Subject: Revert "arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector" This reverts commit a0c68e493007a8c72b6b00f6ac95590a86edc937. Revert all the changes to add the Embedded USB Debugger(EUD) Node in the device tree, the connector node and also changes to usb2 Node associated with this.The changes need to be reverted as DT changes for QCOM should go through the QCOM tree and not the USB tree. Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/8c863e7e76003511dff36383b518ab66d2dd6552.1645793187.git.quic_schowdhu@quicinc.com Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ------------------------------------ 1 file changed, 36 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 96917fe81d43..937c2e0e93eb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2583,12 +2583,6 @@ phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; - usb-role-switch; - port { - usb2_role_switch: endpoint { - remote-endpoint = <&eud_ep>; - }; - }; }; }; @@ -2630,36 +2624,6 @@ interrupts = ; }; - eud: eud@88e0000 { - compatible = "qcom,sc7280-eud","qcom,eud"; - reg = <0 0x88e0000 0 0x2000>, - <0 0x88e2000 0 0x1000>; - interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; - ports { - port@0 { - eud_ep: endpoint { - remote-endpoint = <&usb2_role_switch>; - }; - }; - port@1 { - eud_con: endpoint { - remote-endpoint = <&con_eud>; - }; - }; - }; - }; - - eud_typec: connector { - compatible = "usb-c-connector"; - ports { - port@0 { - con_eud: endpoint { - remote-endpoint = <&eud_con>; - }; - }; - }; - }; - nsp_noc: interconnect@a0c0000 { reg = <0 0x0a0c0000 0 0x10000>; compatible = "qcom,sc7280-nsp-noc"; -- cgit v1.2.3 From 290918c72a2973ffc876d8efb4da304bf7aaea8f Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 18 Feb 2022 16:27:07 +0100 Subject: arm64: dts: imx8mp: Add memory for USB3 glue layer to usb3 nodes The USB3 glue layer has 2 areas in the register set, see RM Rev.1 section 11.2.5.2.1 GLUE_usb3 memory map: * USB3 control/status * PHY control/status Provide the memory area to the usb3 nodes for accessing the features in the USB3 control area. Reviewed-by: Li Jun Signed-off-by: Alexander Stein Link: https://lore.kernel.org/r/20220218152707.2198357-5-alexander.stein@ew.tq-group.com Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6b840c05dd77..61ef0e6d49ca 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -921,7 +921,8 @@ usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10100 0x8>; + reg = <0x32f10100 0x8>, + <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; @@ -962,7 +963,8 @@ usb3_1: usb@32f10108 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10108 0x8>; + reg = <0x32f10108 0x8>, + <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; -- cgit v1.2.3 From 69f8aeab437c6bae1394673154917e0a218edb44 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 4 Mar 2022 16:19:54 +0100 Subject: x86/tsc: Be consistent about use_tsc_delay() Currently loops_per_jiffy is set in tsc_early_init(), but then don't switch to delay_tsc, with the result that delay_loop is used with loops_per_jiffy set for delay_tsc. Then in (late) tsc_init() lpj_fine is set (which is mostly unused) and after which use_tsc_delay() is finally called. Move both loops_per_jiffy and use_tsc_delay() into tsc_enable_sched_clock() which is called the moment tsc_khz is determined, be it early or late. Keeping the lot consistent. Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20220304152135.914397165@infradead.org Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/tsc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a698196377be..cafacb2e58cc 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1487,6 +1487,9 @@ static unsigned long __init get_loops_per_jiffy(void) static void __init tsc_enable_sched_clock(void) { + loops_per_jiffy = get_loops_per_jiffy(); + use_tsc_delay(); + /* Sanitize TSC ADJUST before cyc2ns gets initialized */ tsc_store_and_check_tsc_adjust(true); cyc2ns_init_boot_cpu(); @@ -1502,8 +1505,6 @@ void __init tsc_early_init(void) return; if (!determine_cpu_tsc_frequencies(true)) return; - loops_per_jiffy = get_loops_per_jiffy(); - tsc_enable_sched_clock(); } @@ -1537,7 +1538,6 @@ void __init tsc_init(void) enable_sched_clock_irqtime(); lpj_fine = get_loops_per_jiffy(); - use_tsc_delay(); check_system_tsc_reliable(); -- cgit v1.2.3 From b0ae33a2d2fb6c55117b377ec4ae3f2c84eab6a2 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 4 Mar 2022 16:19:55 +0100 Subject: usb: early: xhci-dbc: Remove duplicate keep parsing The generic earlyprintk= parsing already parses the optional ",keep", no need to duplicate that in the xdbc driver. Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/20220304152135.975568860@infradead.org Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/early_printk.c | 2 +- drivers/usb/early/xhci-dbc.c | 5 ++--- include/linux/usb/xhci-dbgp.h | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c index d3c531d3b244..68b38925a74f 100644 --- a/arch/x86/kernel/early_printk.c +++ b/arch/x86/kernel/early_printk.c @@ -387,7 +387,7 @@ static int __init setup_early_printk(char *buf) #endif #ifdef CONFIG_EARLY_PRINTK_USB_XDBC if (!strncmp(buf, "xdbc", 4)) - early_xdbc_parse_parameter(buf + 4); + early_xdbc_parse_parameter(buf + 4, keep); #endif buf++; diff --git a/drivers/usb/early/xhci-dbc.c b/drivers/usb/early/xhci-dbc.c index 4502108069cd..100a45d26b5a 100644 --- a/drivers/usb/early/xhci-dbc.c +++ b/drivers/usb/early/xhci-dbc.c @@ -599,7 +599,7 @@ static int __init xdbc_early_setup(void) return 0; } -int __init early_xdbc_parse_parameter(char *s) +int __init early_xdbc_parse_parameter(char *s, int keep_early) { unsigned long dbgp_num = 0; u32 bus, dev, func, offset; @@ -608,8 +608,7 @@ int __init early_xdbc_parse_parameter(char *s) if (!early_pci_allowed()) return -EPERM; - if (strstr(s, "keep")) - early_console_keep = true; + early_console_keep = keep_early; if (xdbc.xdbc_reg) return 0; diff --git a/include/linux/usb/xhci-dbgp.h b/include/linux/usb/xhci-dbgp.h index 0a37f1283bf0..01fe768873f9 100644 --- a/include/linux/usb/xhci-dbgp.h +++ b/include/linux/usb/xhci-dbgp.h @@ -15,7 +15,7 @@ #define __LINUX_XHCI_DBGP_H #ifdef CONFIG_EARLY_PRINTK_USB_XDBC -int __init early_xdbc_parse_parameter(char *s); +int __init early_xdbc_parse_parameter(char *s, int keep_early); int __init early_xdbc_setup_hardware(void); void __init early_xdbc_register_console(void); #else -- cgit v1.2.3