From 64fc984a8a54163a5c44e15a54b574a2c5564d8f Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Thu, 30 Nov 2023 16:19:25 +0100 Subject: riscv: errata: Add StarFive JH7100 errata This not really an errata, but since the JH7100 was made before the standard Zicbom extension it needs the DMA_GLOBAL_POOL and RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. Acked-by: Conor Dooley Signed-off-by: Emil Renner Berthing Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.errata | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e2c731cfed8c..692de149141f 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE_JH7100 + bool "StarFive JH7100 support" + depends on ARCH_STARFIVE && NONPORTABLE + select DMA_GLOBAL_POOL + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + select SIFIVE_CCACHE + default n + help + The StarFive JH7100 was a test chip for the JH7110 and has + caches that are non-coherent with respect to peripheral DMAs. + It was designed before the Zicbom extension so needs non-standard + cache operations through the SiFive cache controller. + + Say "Y" if you want to support the BeagleV Starlight and/or + StarFive VisionFive V1 boards. + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE -- cgit v1.2.3 From 9a9e8d8d2b6e61a516cbb8a43c5cec51c065ffa4 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Fri, 15 Dec 2023 20:09:09 +0100 Subject: riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP Similar to the Renesas RZ/Five[1] the JH7100 SoC needs the non-portable CONFIG_DMA_GLOBAL_POOL enabled which is incompatible with DMA_DIRECT_REMAP selected by RISCV_ISA_ZICBOM. [1]: commit 31b2daea0764 ("soc: renesas: Make RZ/Five depend on !DMA_DIRECT_REMAP") Link: https://lore.kernel.org/all/24942b4d-d16a-463f-b39a-f9dfcb89d742@infradead.org/ Fixes: 64fc984a8a54 ("riscv: errata: Add StarFive JH7100 errata") Signed-off-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.errata | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 692de149141f..f5c432b005e7 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -55,7 +55,9 @@ config ERRATA_SIFIVE_CIP_1200 config ERRATA_STARFIVE_JH7100 bool "StarFive JH7100 support" - depends on ARCH_STARFIVE && NONPORTABLE + depends on ARCH_STARFIVE + depends on !DMA_DIRECT_REMAP + depends on NONPORTABLE select DMA_GLOBAL_POOL select RISCV_DMA_NONCOHERENT select RISCV_NONSTANDARD_CACHE_OPS -- cgit v1.2.3